; -------------------------------------------------------------------------------- ; @Title: S6J34x On-Chip Peripherals ; @Props: Released ; @Author: BAN, RAJ, DAM ; @Changelog: 2019-08-01 BAN ; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation ; @Doc: 32-BIT_MICROCONTROLLER_TRAVEO_TM_FAMILY_HARDWARE_MANUAL_PLATFORM_PART.pdf (Rev. *D) ; 001-97829_S6J3400_SERIES_32-bit_ARM_Cortex_-R5F_Traveo_Microcontroller.pdf (Rev. *K) ; 002-09919_S6J34X8_9_A_32-bit_Microcontroller_S6J3400_SERIES_HARDWARE_MANUAL_TRAVEO_TM_FAMILY.pdf (Rev. *E) ; @Core: Cortex-R5 ; @Chip: S6J3428FS, S6J3428FT, S6J3428FU, S6J3428FV, S6J3428HS, S6J3428HT, ; S6J3428HU, S6J3428HV, S6J3428JS, S6J3428JT, S6J3428JU, S6J3428JV, ; S6J3429FS, S6J3429FT, S6J3429FU, S6J3429FV, S6J3429HS, S6J3429HT, ; S6J3429HU, S6J3429HV, S6J3429JS, S6J3429JT, S6J3429JU, S6J3429JV, ; S6J342AFS, S6J342AFT, S6J342AFU, S6J342AFV, S6J342AHS, S6J342AHT, ; S6J342AHU, S6J342AHV, S6J342AJS, S6J342AJT, S6J342AJU, S6J342AJV ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: pers6j34x.per 15964 2023-04-13 11:46:29Z bschroefel $ ; Known problems: ; MODULE REGISTER DESCRIPTION ; BT There is no information about which channel is missing in which chassis ; DDRHSSPI No base address ; EBI No base address config 16. 8. tree "Core Registers (Cortex-R5F)" AUTOINDENT.PUSH AUTOINDENT.OFF width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x00++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x400--0x400 line.long 0x0 "MPUIR,MPU type register" hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions" bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated" rgroup.long c15:0x500++0x00 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system" textline " " hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0" textline " " rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..." bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c15:0x020++0x00 line.long 0x00 "ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x120++0x00 line.long 0x00 "ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x220++0x00 line.long 0x00 "ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x320++0x00 line.long 0x00 "ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x420++0x00 line.long 0x00 "ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup.long c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup.long c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup.long c15:0x010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup.long c15:0x210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c15:0x310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x02f++0x00 line.long 0x00 "BO1R,Build Options 1 Register" hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM" bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented" textline " " bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented" group.long c15:0x12f++0x00 line.long 0x00 "BO2R,Build Options 2 Register" bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2" bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included" textline " " bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No" bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No" textline " " bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection" bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..." textline " " bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No" bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No" textline " " bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions" bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No" textline " " bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No" bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No" textline " " bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes" bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No" textline " " bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC" bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..." textline " " bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No" bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes" textline " " bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes" bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes" textline " " bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes" group.long c15:0x72f++0x00 line.long 0x00 "POR,Pin Options Register" bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High" bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High" textline " " bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High" bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High" textline " " bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High" tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x101++0x00 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable" bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable" bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable" bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" textline " " bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable" bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable" textline " " bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable" bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable" bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable" textline " " bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable" bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable" bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..." textline " " bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable" bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable" bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable" textline " " bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable" bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced" bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced" textline " " bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced" bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled" bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable" textline " " bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..." textline " " bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable" bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable" bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable" textline " " group.long c15:0x0f++0x00 line.long 0x00 "SACTLR,Secondary Auxiliary Control Register" bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable" bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable" bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable" bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable" bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable" textline " " bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable" bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate" bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate" bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate" bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate" bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable" bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable" textline " " bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable" bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable" textline " " group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x000b++0x00 line.long 0x00 "SPCR,Slave Port Control Register" bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only" bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled" tree.end width 0x8 tree "MPU Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x05++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x15++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x06++0x00 line.long 0x00 "DFAR,Data Fault Address Register" textline " " group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" textline " " group.long c15:0x0016++0x00 line.long 0x00 "RBAR,Region Base Address Register" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group.long c15:0x0216++0x00 line.long 0x00 "RSER,Region Size and Enable Register" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group.long c15:0x0416++0x00 line.long 0x00 "RACR,Region Access Control Register" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" group.long c15:0x0026++0x00 line.long 0x00 "MRNR,Memory Region Number Register" bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long c15:0x010d++0x00 line.long 0x00 "CIDR,Context ID Register" group.long c15:0x20d++0x00 line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register" group.long c15:0x30d++0x00 line.long 0x00 "TIDRURO,User read only Thread and Process ID Register" group.long c15:0x40d++0x00 line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register" width 0x08 tree "MPU regions" group c15:0x0016++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RBAR0,Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RSER0,Region Size and Enable Register 0" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RACR0,Region Access Control Register 0" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RBAR1,Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RSER1,Region Size and Enable Register 1" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RACR1,Region Access Control Register 1" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RBAR2,Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RSER2,Region Size and Enable Register 2" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RACR2,Region Access Control Register 2" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RBAR3,Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RSER3,Region Size and Enable Register 3" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RACR3,Region Access Control Register 3" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RBAR4,Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RSER4,Region Size and Enable Register 4" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RACR4,Region Access Control Register 4" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RBAR5,Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RSER5,Region Size and Enable Register 5" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RACR5,Region Access Control Register 5" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RBAR6,Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RSER6,Region Size and Enable Register 6" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RACR6,Region Access Control Register 6" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RBAR7,Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RSER7,Region Size and Enable Register 7" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RACR7,Region Access Control Register 7" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RBAR8,Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RSER8,Region Size and Enable Register 8" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RACR8,Region Access Control Register 8" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RBAR9,Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RSER9,Region Size and Enable Register 9" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RACR9,Region Access Control Register 9" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RBAR10,Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RSER10,Region Size and Enable Register 10" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RACR10,Region Access Control Register 10" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RBAR11,Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RSER11,Region Size and Enable Register 11" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RACR11,Region Access Control Register 11" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RBAR12,Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RSER12,Region Size and Enable Register 12" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RACR12,Region Access Control Register 12" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RBAR13,Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RSER13,Region Size and Enable Register 13" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RACR13,Region Access Control Register 13" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RBAR14,Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RSER14,Region Size and Enable Register 14" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RACR14,Region Access Control Register 14" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RBAR15,Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RSER15,Region Size and Enable Register 15" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RACR15,Region Access Control Register 15" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " tree.end tree.end width 0x9 tree "TCM Control and Configuration" rgroup.long c15:0x200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7" group.long c15:0x019++0x00 line.long 0x00 "BTCMRR,BTCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" group.long c15:0x119++0x00 line.long 0x00 "ATCMRR,ATCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" rgroup.long c15:0x29++0x00 line.long 0x00 "TCMSEL,TCM Selection Register" textline " " group.long c15:0x10f++0x00 line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x20f++0x00 line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x30f++0x00 line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7" group.long c15:0x2000++0x00 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction" group.long c15:0x03f++0x00 line.long 0x00 "CFLR,Correctable Fault Location Register" bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred" bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP" group.long c15:0x5f++0x00 line.long 0x00 "IADCR,Invalidate All Data Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" group.long c15:0xef++0x00 line.long 0x00 "CSOR,Cache Size Override Register" bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes" textline " " bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset" bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Cycle Count Register" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "ESR0,Event Selection Register 0" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "PMCR0,Performance Monitor Count Register 0" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "ESR1,Event Selection Register 1" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "PMCR1,Performance Monitor Count Register 1" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "ESR2,Event Selection Register 2" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "PMCR2,Performance Monitor Count Register 2" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree "Validation Registers" group.long c15:0x01f++0x00 line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x11f++0x00 line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x21f++0x00 line.long 0x00 "RESR,nVAL Reset Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x31f++0x00 line.long 0x00 "RESR,VAL Debug Request Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" group.long c15:0x41f++0x00 line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x51f++0x00 line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x61f++0x00 line.long 0x00 "RECR,nVAL Reset Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x71f++0x00 line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" tree.end tree.end width 11. width 18. tree "Debug Registers" tree "Processor Identifier Registers" rgroup.long c14:832.++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup.long c14:833.++0x00 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup.long c14:834.++0x00 line.long 0x00 "TCMTR,TCM Type Register" group.long c14:835.++0x00 line.long 0x00 "AMIDR,Alias of MIDR" rgroup.long c14:836.++0x00 line.long 0x00 "MPUTR,MPU Type Register" rgroup.long c14:837.++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" group.long c14:838.++0x00 line.long 0x00 "AMIDR0,Alias of MIDR" group.long c14:839.++0x00 line.long 0x00 "AMIDR1,Alias of MIDR" rgroup.long c14:840.++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c14:841.++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c14:842.++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c14:843.++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c14:844.++0x00 line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c14:845.++0x00 line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c14:846.++0x00 line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c14:847.++0x00 line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c14:848.++0x00 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:849.++0x00 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c14:850.++0x00 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:851.++0x00 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c14:852.++0x00 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c14:853.++0x00 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end width 15. tree "Coresight Management Registers" group.long c14:960.++0x00 line.long 0x00 "DBGITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration" group.long c14:1000.++0x00 line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register" hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set" group.long c14:1001.++0x00 line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register" hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes" textline " " bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked" rgroup.long c14:1006.++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register" bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled" rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype" hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class" tree.end textline " " width 12. rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" textline " " bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High" textline " " hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" group.long c14:34.++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" textline " " bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled" hgroup.long c14:32.++0x0 hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register" in group.long c14:35.++0x00 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" group.long c14:10.++0x0 line.long 0x00 "DBGDSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes" bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes" textline " " bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Instruction Transfer Register" wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" textline " " bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" textline " " rgroup.long c14:193.++0x0 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented" group.long c14:196.++0x0 line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register" bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held" textline " " bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested" bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset" bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset" textline " " bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset" bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up" tree.end width 7. tree "Breakpoint Registers" group.long c14:64.++0x0 line.long 0x00 "BVR0,Breakpoint Value 0 Register" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group.long c14:80.++0x0 line.long 0x00 "BCR0,Breakpoint Control 0 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:65.++0x0 line.long 0x00 "BVR1,Breakpoint Value 1 Register" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group.long c14:81.++0x0 line.long 0x00 "BCR1,Breakpoint Control 1 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:66.++0x0 line.long 0x00 "BVR2,Breakpoint Value 2 Register" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group.long c14:82.++0x0 line.long 0x00 "BCR2,Breakpoint Control 2 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:67.++0x0 line.long 0x00 "BVR3,Breakpoint Value 3 Register" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group.long c14:83.++0x0 line.long 0x00 "BCR3,Breakpoint Control 3 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:68.++0x0 line.long 0x00 "BVR4,Breakpoint Value 4 Register" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group.long c14:84.++0x0 line.long 0x00 "BCR4,Breakpoint Control 4 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:69.++0x0 line.long 0x00 "BVR5,Breakpoint Value 5 Register" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group.long c14:85.++0x0 line.long 0x00 "BCR5,Breakpoint Control 5 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:70.++0x0 line.long 0x00 "BVR6,Breakpoint Value 6 Register" hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6" group.long c14:86.++0x0 line.long 0x00 "BCR6,Breakpoint Control 6 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:71.++0x0 line.long 0x00 "BVR7,Breakpoint Value 7 Register" hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7" group.long c14:87.++0x0 line.long 0x00 "BCR7,Breakpoint Control 7 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.long c14:96.++0x0 line.long 0x00 "WVR0,Watchpoint Value 0 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:112.++0x0 line.long 0x00 "WCR0,Watchpoint Control 0 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:97.++0x0 line.long 0x00 "WVR1,Watchpoint Value 1 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:113.++0x0 line.long 0x00 "WCR1,Watchpoint Control 1 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:98.++0x0 line.long 0x00 "WVR2,Watchpoint Value 2 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:114.++0x0 line.long 0x00 "WCR2,Watchpoint Control 2 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:99.++0x0 line.long 0x00 "WVR3,Watchpoint Value 3 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:115.++0x0 line.long 0x00 "WCR3,Watchpoint Control 3 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:100.++0x0 line.long 0x00 "WVR4,Watchpoint Value 4 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:116.++0x0 line.long 0x00 "WCR4,Watchpoint Control 4 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:101.++0x0 line.long 0x00 "WVR5,Watchpoint Value 5 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:117.++0x0 line.long 0x00 "WCR5,Watchpoint Control 5 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:102.++0x0 line.long 0x00 "WVR6,Watchpoint Value 6 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:118.++0x0 line.long 0x00 "WCR6,Watchpoint Control 6 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:103.++0x0 line.long 0x00 "WVR7,Watchpoint Value 7 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:119.++0x0 line.long 0x00 "WCR7,Watchpoint Control 7 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:6.++0x0 line.long 0x00 "WFAR ,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction" tree.end width 11. AUTOINDENT.POP tree.end tree "MODEC (Operation Mode)" base ad:0xB0600800 width 7. rgroup.long 0x00++0x03 line.long 0x00 "MODER,Mode Register" bitfld.long 0x00 31. " USERMODE ,User mode bit" "Board,User" bitfld.long 0x00 12. " MD ,Mode bit" "0,1" width 0x0B tree.end tree "RST (Reset)" base ad:0xB0600380 width 17. group.long 0x0++0x03 line.long 0x00 "RSTCNTR,Reset Control Register" hexmask.long.byte 0x00 24.--31. 1. " DBGR ,Software debugger reset register bit" hexmask.long.byte 0x00 16.--23. 1. " SWHRST ,Software trigger hard reset register bit" hexmask.long.byte 0x00 0.--7. 1. " SWRST ,Software reset register bit" group.long 0x10++0x0B line.long 0x00 "RSTCAUSEUR,User Factor Register" bitfld.long 0x00 31. " LVDL2R ,Extended internal power supply low-voltage detection reset detection bit" "Not detected,Detected" bitfld.long 0x00 30. " LVDL1R ,Internal power supply low-voltage detection reset detection bit" "Not detected,Detected" sif cpuis("S6J342*")||cpuis("S6J351*") newline bitfld.long 0x00 29. " CSVSCRR ,Slow CR clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 28. " CSVFCRR ,Fast CR clock supervisor reset detection bit" "Not detected,Detected" endif bitfld.long 0x00 27. " CSVSR0 ,Clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 26. " CSVPR0 ,PLL0 clock supervisor reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 25. " CSVSOR ,Sub clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 24. " CSVMOR ,Main clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 20. " SHRST ,Software trigger hard reset detection bit" "Not detected,Detected" bitfld.long 0x00 16. " SRST ,Software reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 12. " SWDR ,Software watchdog reset detection bit" "Not detected,Detected" bitfld.long 0x00 11. " HWDR ,Hardware watchdog reset detection bit" "Not detected,Detected" bitfld.long 0x00 10. " PRFERR ,Profile error reset detection bit" "Not detected,Detected" bitfld.long 0x00 9. " SRSTX ,NSRST pin input reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 8. " IMR ,Illegal mode reset detection bit" "Not detected,Detected" bitfld.long 0x00 7. " LVDH2R ,Extended external power supply low-voltage detection reset detection bit" "Not detected,Detected" bitfld.long 0x00 6. " LVDH1R ,External power supply low-voltage detection reset detection bit" "Not detected,Detected" bitfld.long 0x00 4. " RSTX ,RSTX pin input reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 3. " CKTOR ,Clock stop wait timeout reset detection bit" "Not detected,Detected" bitfld.long 0x00 2. " INITX ,INITX detection bit" "Not detected,Detected" bitfld.long 0x00 1. " RVD ,RAM retention low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 0. " PONR ,Power-on reset detection bit" "Not detected,Detected" line.long 0x04 "EXCSVRSTCAUSEUR,User Extended SCV Reset Factor Register" bitfld.long 0x04 7. " CSVSR3 ,SSCG3 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 6. " CSVSR2 ,SSCG2 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 5. " CSVSR1 ,SSCG1 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 3. " CSVPR3 ,PLL3 clock supervisor reset detection bit" "Not detected,Detected" newline bitfld.long 0x04 2. " CSVPR2 ,PLL2 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 1. " CSVPR1 ,PLL1 clock supervisor reset detection bit" "Not detected,Detected" line.long 0x08 "PDRSTCAUSEUR,User PowerDomain Reset Factor Register" bitfld.long 0x08 17. " PD6R1 ,PowerDomain6_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 16. " PD6R0 ,PowerDomain6_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 15. " PD5R3 ,PowerDomain5_3 reset detection bit" "Not detected,Detected" bitfld.long 0x08 14. " PD5R2 ,PowerDomain5_2 reset detection bit" "Not detected,Detected" newline bitfld.long 0x08 13. " PD5R1 ,PowerDomain5_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 12. " PD5R0 ,PowerDomain5_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 9. " PD4R1 ,PowerDomain4_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 8. " PD4R0 ,PowerDomain4_0 reset detection bit" "Not detected,Detected" newline bitfld.long 0x08 4. " PD3R0 ,PowerDomain3_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 0. " PD2R0 ,PowerDomain2_0 reset detection bit" "Not detected,Detected" group.long 0x20++0x0B line.long 0x00 "RSTCAUSEBT,BootROM Reset Factor Register" bitfld.long 0x00 31. " LVDL2R ,Extended internal power supply low-voltage detection reset detection bit" "Not detected,Detected" bitfld.long 0x00 30. " LVDL1R ,Internal power supply low-voltage reset detection bit" "Not detected,Detected" sif cpuis("S6J342*")||cpuis("S6J351*") newline bitfld.long 0x00 29. " CSVSCRR ,Slow CR clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 28. " CSVFCRR ,Fast CR clock supervisor reset detection bit" "Not detected,Detected" endif bitfld.long 0x00 27. " CSVSR0 ,SSCG0 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 26. " CSVPR0 ,PLL0 clock supervisor reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 25. " CSVSOR ,Sub clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 24. " CSVMOR ,Main clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x00 20. " SHRST ,Software trigger hard reset detection bit" "Not detected,Detected" bitfld.long 0x00 16. " SRST ,Software reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 12. " SWDR ,Software watchdog reset detection bit" "Not detected,Detected" bitfld.long 0x00 11. " HWDR ,Hardware watchdog reset detection bit" "Not detected,Detected" bitfld.long 0x00 10. " PRFERR ,Profile error reset detection bit" "Not detected,Detected" bitfld.long 0x00 9. " SRSTX ,NSRST pin input reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 8. " IMR ,Illegal mode reset detection bit" "Not detected,Detected" bitfld.long 0x00 7. " LVDH2R ,Extended external power supply low-voltage detection reset detection bit" "Not detected,Detected" bitfld.long 0x00 6. " LVDH1R ,External power supply low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 4. " RSTX ,RSTX pin input reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 3. " CKTOR ,Clock stop wait timeout reset detection bit" "Not detected,Detected" bitfld.long 0x00 2. " INITX ,INITX reset detection bit" "Not detected,Detected" bitfld.long 0x00 1. " RVD ,RAM retention low-voltage reset detection bit" "Not detected,Detected" bitfld.long 0x00 0. " PONR ,Power-on reset detection bit" "Not detected,Detected" line.long 0x04 "EXCSVRSTCAUSEBT,BootROM Extended CSV Reset Factor Register" bitfld.long 0x04 7. " CSVSR3 ,SSCG3 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 6. " CSVSR2 ,SSCG2 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 5. " CSVSR1 ,SSCG1 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 3. " CSVPR3 ,PLL3 clock supervisor reset detection bit" "Not detected,Detected" newline bitfld.long 0x04 2. " CSVPR2 ,PLL2 clock supervisor reset detection bit" "Not detected,Detected" bitfld.long 0x04 1. " CSVPR1 ,PLL1 clock supervisor reset detection bit" "Not detected,Detected" line.long 0x08 "PDRSTCAUSEBT,BootROM PowerDomain Reset Factor Register" bitfld.long 0x08 17. " PD6R1 ,PowerDomain6_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 16. " PD6R0 ,PowerDomain6_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 15. " PD5R3 ,PowerDomain5_3 reset detection bit" "Not detected,Detected" bitfld.long 0x08 14. " PD5R2 ,PowerDomain5_2 reset detection bit" "Not detected,Detected" newline bitfld.long 0x08 13. " PD5R1 ,PowerDomain5_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 12. " PD5R0 ,PowerDomain5_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 9. " PD4R1 ,PowerDomain4_1 reset detection bit" "Not detected,Detected" bitfld.long 0x08 8. " PD4R0 ,PowerDomain4_0 reset detection bit" "Not detected,Detected" newline bitfld.long 0x08 4. " PD3R0 ,PowerDomain3_0 reset detection bit" "Not detected,Detected" bitfld.long 0x08 0. " PD2R0 ,PowerDomain2_0 reset detection bit" "Not detected,Detected" rgroup.long 0x34++0x03 line.long 0x00 "PDRSTATUS,PowerDomain Reset Status Register" bitfld.long 0x00 17. " PD6RS1 ,PowerDomain6_1 reset detection bit" "Not detected,Detected" bitfld.long 0x00 16. " PD6RS0 ,PowerDomain6_0 reset detection bit" "Not detected,Detected" bitfld.long 0x00 15. " PD5RS3 ,PowerDomain5_3 reset detection bit" "Not detected,Detected" bitfld.long 0x00 14. " PD5RS2 ,PowerDomain5_2 reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 13. " PD5RS1 ,PowerDomain5_1 reset detection bit" "Not detected,Detected" bitfld.long 0x00 12. " PD5RS0 ,PowerDomain5_0 reset detection bit" "Not detected,Detected" bitfld.long 0x00 9. " PD4RS1 ,PowerDomain4_1 reset detection bit" "Not detected,Detected" bitfld.long 0x00 8. " PD4RS0 ,PowerDomain4_0 reset detection bit" "Not detected,Detected" newline bitfld.long 0x00 4. " PD3RS0 ,PowerDomain3_0 reset detection bit" "Not detected,Detected" bitfld.long 0x00 0. " PD2RS0 ,PowerDomain2_0 reset detection bit" "Not detected,Detected" width 0x0B tree.end tree "CS (Clock System)" base ad:0xB0600600 width 15. group.long 0x00++0x03 line.long 0x00 "CRCNTR,CR Clock Control Register" bitfld.long 0x00 24. " CALIBCSEL ,CR calibration clock select bit (LP Type only)" "Fast-CR,Slow-CR" bitfld.long 0x00 16.--20. " TRV ,Voltage trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TRC ,Coarse trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TRF ,Fine trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x34++0x03 line.long 0x00 "SCRCNTR,Slow-CR Clock Control Register" bitfld.long 0x00 8.--10. " TRC ,Coarse trimming bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " TRF ,Fine trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x04++0x0B line.long 0x00 "MOSCCNTR,Main Oscillator Control Register" bitfld.long 0x00 31. " MCMODE ,Main clock amplifier oscillation mode bit" "Oscillation mode,Stop mode" bitfld.long 0x00 26.--27. " MCGAIN ,Main clock gain bit" "4(3.6)MHz,8MHz,16MHz,25MHz" bitfld.long 0x00 8. " DIV2SEL ,Select bit" "Main Clock,Main Clk/2" newline bitfld.long 0x00 0. " FCIMEN ,Fast main clock input enable control bit" "Disabled,Enabled" line.long 0x04 "SOSCCNTR,Sub Oscillator Control Register" bitfld.long 0x04 16. " SUBPORT ,This bit is used to set Port function for sub clock input" "Disabled,Enabled" line.long 0x08 "PLLSSCGSTCNTR,PLL/SSCG Stabilization Time Control Register" bitfld.long 0x08 4.--7. " SSCGSTABS ,Stabilization time for SSCG PLL0/1/2/3 clock" ",,,,,,,,2^9 Cycle,2^10 Cycle,2^11 Cycle,2^12 Cycle,2^13 Cycle,2^14 Cycle,2^15 Cycle,2^16 Cycle" bitfld.long 0x08 0.--3. " PLLSTABS ,Stabilization time for PLL0/1/2/3 clock" ",,,,,,,,2^9 Cycle,2^10 Cycle,2^11 Cycle,2^12 Cycle,2^13 Cycle,2^14 Cycle,2^15 Cycle,2^16 Cycle" group.long 0x10++0x03 line.long 0x00 "PLL0CGCNTR,PLL0 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " PLLCGLP ,PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " PLLCGSTP ,PLL clock gear step configuration bit" "1 Step,2 Steps,3 Steps,4 Steps" bitfld.long 0x00 8.--13. " PLLCGSSN ,PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" bitfld.long 0x00 1. " PLLCGSTR ,PLL clock gear start bit" "No operation,Started" bitfld.long 0x00 0. " PLLCGEN ,PLL clock gear enable bit" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "PLL1CGCNTR,PLL1 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " PLLCGLP ,PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " PLLCGSTP ,PLL clock gear step configuration bit" "1 Step,2 Steps,3 Steps,4 Steps" bitfld.long 0x00 8.--13. " PLLCGSSN ,PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" bitfld.long 0x00 1. " PLLCGSTR ,PLL clock gear start bit" "No operation,Started" bitfld.long 0x00 0. " PLLCGEN ,PLL clock gear enable bit" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "PLL2CGCNTR,PLL2 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " PLLCGLP ,PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " PLLCGSTP ,PLL clock gear step configuration bit" "1 Step,2 Steps,3 Steps,4 Steps" bitfld.long 0x00 8.--13. " PLLCGSSN ,PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" bitfld.long 0x00 1. " PLLCGSTR ,PLL clock gear start bit" "No operation,Started" bitfld.long 0x00 0. " PLLCGEN ,PLL clock gear enable bit" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "PLL3CGCNTR,PLL3 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " PLLCGLP ,PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " PLLCGSTP ,PLL clock gear step configuration bit" "1 Step,2 Steps,3 Steps,4 Steps" bitfld.long 0x00 8.--13. " PLLCGSSN ,PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down" bitfld.long 0x00 1. " PLLCGSTR ,PLL clock gear start bit" "No operation,Started" bitfld.long 0x00 0. " PLLCGEN ,PLL clock gear enable bit" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "SSCG0CGCNTR,SSCG PPL0 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " SSCGCGLP ,SSCG PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " SSCGCGSTP ,SSCG PLL clock gear step configuration bit" "1 Step,2 Steps,3 Steps,4 Steps" bitfld.long 0x00 8.--13. " SSCGCGSSN ,SSCG PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at nin.,Gear up,Stop at max.,Gear down" bitfld.long 0x00 1. " SSCGCGSTR ,SSCG PLL clock gear start bit" "No operation,Started" bitfld.long 0x00 0. " SSCGCGEN ,SSCG PLL clock gear enable bit" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "SSCG1CGCNTR,SSCG PPL1 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " SSCGCGLP ,SSCG PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " SSCGCGSTP ,SSCG PLL clock gear step configuration bit" "1 Step,2 Steps,3 Steps,4 Steps" bitfld.long 0x00 8.--13. " SSCGCGSSN ,SSCG PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at nin.,Gear up,Stop at max.,Gear down" bitfld.long 0x00 1. " SSCGCGSTR ,SSCG PLL clock gear start bit" "No operation,Started" bitfld.long 0x00 0. " SSCGCGEN ,SSCG PLL clock gear enable bit" "Disabled,Enabled" group.long 0x28++0x03 line.long 0x00 "SSCG2CGCNTR,SSCG PPL2 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " SSCGCGLP ,SSCG PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " SSCGCGSTP ,SSCG PLL clock gear step configuration bit" "1 Step,2 Steps,3 Steps,4 Steps" bitfld.long 0x00 8.--13. " SSCGCGSSN ,SSCG PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at nin.,Gear up,Stop at max.,Gear down" bitfld.long 0x00 1. " SSCGCGSTR ,SSCG PLL clock gear start bit" "No operation,Started" bitfld.long 0x00 0. " SSCGCGEN ,SSCG PLL clock gear enable bit" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "SSCG3CGCNTR,SSCG PPL3 Clock Gear Control Register" hexmask.long.byte 0x00 16.--23. 1. " SSCGCGLP ,SSCG PLL clock gear loop configuration bit" bitfld.long 0x00 14.--15. " SSCGCGSTP ,SSCG PLL clock gear step configuration bit" "1 Step,2 Steps,3 Steps,4 Steps" bitfld.long 0x00 8.--13. " SSCGCGSSN ,SSCG PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at nin.,Gear up,Stop at max.,Gear down" bitfld.long 0x00 1. " SSCGCGSTR ,SSCG PLL clock gear start bit" "No operation,Started" bitfld.long 0x00 0. " SSCGCGEN ,SSCG PLL clock gear enable bit" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "CKOTCNTR,Clock Output Function Control Register" bitfld.long 0x00 24. " ENCLKO ,Enable/Disable clock output function" "Disabled,Enabled" bitfld.long 0x00 8.--10. " CKOUTDIV ,Clock Division bits" "Not divided,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 0.--3. " CKSEL ,Clock Select bits" "Fast-CR,Slow-CR,Main,Sub,PLL0,PLL1,PLL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,Prohibit(Fast-CR),Prohibit(Fast-CR),Prohibit(Fast-CR),Tied to low" width 0x0B tree.end tree.open "LPC (Low-power Consumption)" tree "SYSC0 (System Controller 0)" base ad:0xB0600000 width 15. tree "Protection Register Group" group.long 0x00++0x03 line.long 0x00 "PROTKEYR,Protection Key Setting Register" tree.end tree "RUN Profile Register Group" group.long 0x80++0x0B line.long 0x00 "RUNPDCFGR,RUN Power Domain Setting Register" rbitfld.long 0x00 25. " PD6_1EN ,Power domain 6_1 power supply control bit" "No supply,Supply" rbitfld.long 0x00 24. " PD6_0EN ,Power domain 6_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 23. " PD5_3EN ,Power domain 5_3 power supply control bit" "No supply,Supply" bitfld.long 0x00 22. " PD5_2EN ,Power domain 5_2 power supply control bit" "No supply,Supply" bitfld.long 0x00 21. " PD5_1EN ,Power domain 5_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 20. " PD5_0EN ,Power domain 5_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 17. " PD4_1EN ,Power domain 4_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 16. " PD4_0EN ,Power domain 4_0 power supply control bit" "No supply,Supply" newline rbitfld.long 0x00 12. " PD3EN ,Power domain 3 power supply control bit" "No supply,Supply" newline rbitfld.long 0x00 8. " PD2EN ,Power domain 2 power supply control bit" "No supply,Supply" line.long 0x04 "RUNCKSRER,RUN Clock Source Enable Register" bitfld.long 0x04 19. " SSCG3EN ,SSCG PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2EN ,SSCG PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1EN ,SSCG PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0EN ,SSCG PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 11. " PLL3EN ,PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2EN ,PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1EN ,PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0EN ,PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x04 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" ",Enabled" rbitfld.long 0x04 0. " CROSCEN ,High-speed CR clock oscillation enable bit" ",Enabled" line.long 0x08 "RUNCKSELR,Run Clock Selection Register" bitfld.long 0x08 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG PLL0,,Clock fixed at L" rgroup.long 0x8C++0x03 line.long 0x00 "RUNCKER,RUN Clock Enable Register" bitfld.long 0x00 1. " ENCLKMCUCP ,MCU config APB clock oscillation enable bit" ",Enabled" bitfld.long 0x00 0. " ENCLKMCUCH ,MCU config AHB clock oscillation enable bit" ",Enabled" group.long 0x90++0x03 line.long 0x00 "RUNCKDIVR,RUN Clock Divider Register" bitfld.long 0x00 8.--11. " MCUCPDIV ,MCU config APB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " MCUCHDIV ,MCU config AHB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x94++0x03 line.long 0x00 "RUNPLL0CNTR,Run PLL0 Control Register" bitfld.long 0x00 31. " PLL0ISEL ,PLL0 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL0DIVN ,PLL0 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL0DIVM ,PLL0 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL0DIVL ,PLL0 input clock divider setting bits" "No division,/2,/4,/6" group.long 0xA4++0x07 line.long 0x00 "RUNSSCG0CNTR0,RUN SSCG0 Control Register 0" bitfld.long 0x00 31. " SSCG0ISEL ,SSCG PLL0 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG0DIVN ,SSCG PLL0 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG0DIVM ,SSCG PLL0 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG0DIVL ,SSCG PLL0 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "RUNSSCG0CNTR1,RUN SSCG0 Control Register 1" bitfld.long 0x04 24. " SSCG0SSEN ,SSCG PLL0 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG0FREQ ,SSCG PLL0 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG0MODE ,SSCG PLL0 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG0RATE ,SSCG PLL0 clock modulation ratio control bits" group.long 0x98++0x03 line.long 0x00 "RUNPLL1CNTR,Run PLL1 Control Register" bitfld.long 0x00 31. " PLL1ISEL ,PLL1 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL1DIVN ,PLL1 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL1DIVM ,PLL1 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL1DIVL ,PLL1 input clock divider setting bits" "No division,/2,/4,/6" group.long 0xAC++0x07 line.long 0x00 "RUNSSCG1CNTR0,RUN SSCG1 Control Register 0" bitfld.long 0x00 31. " SSCG1ISEL ,SSCG PLL1 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG1DIVN ,SSCG PLL1 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG1DIVM ,SSCG PLL1 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG1DIVL ,SSCG PLL1 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "RUNSSCG1CNTR1,RUN SSCG1 Control Register 1" bitfld.long 0x04 24. " SSCG1SSEN ,SSCG PLL1 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG1FREQ ,SSCG PLL1 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG1MODE ,SSCG PLL1 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG1RATE ,SSCG PLL1 clock modulation ratio control bits" group.long 0x9C++0x03 line.long 0x00 "RUNPLL2CNTR,Run PLL2 Control Register" bitfld.long 0x00 31. " PLL2ISEL ,PLL2 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL2DIVN ,PLL2 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL2DIVM ,PLL2 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL2DIVL ,PLL2 input clock divider setting bits" "No division,/2,/4,/6" group.long 0xB4++0x07 line.long 0x00 "RUNSSCG2CNTR0,RUN SSCG2 Control Register 0" bitfld.long 0x00 31. " SSCG2ISEL ,SSCG PLL2 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG2DIVN ,SSCG PLL2 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG2DIVM ,SSCG PLL2 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG2DIVL ,SSCG PLL2 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "RUNSSCG2CNTR1,RUN SSCG2 Control Register 1" bitfld.long 0x04 24. " SSCG2SSEN ,SSCG PLL2 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG2FREQ ,SSCG PLL2 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG2MODE ,SSCG PLL2 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG2RATE ,SSCG PLL2 clock modulation ratio control bits" group.long 0xA0++0x03 line.long 0x00 "RUNPLL3CNTR,Run PLL3 Control Register" bitfld.long 0x00 31. " PLL3ISEL ,PLL3 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL3DIVN ,PLL3 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL3DIVM ,PLL3 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL3DIVL ,PLL3 input clock divider setting bits" "No division,/2,/4,/6" group.long 0xBC++0x07 line.long 0x00 "RUNSSCG3CNTR0,RUN SSCG3 Control Register 0" bitfld.long 0x00 31. " SSCG3ISEL ,SSCG PLL3 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG3DIVN ,SSCG PLL3 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG3DIVM ,SSCG PLL3 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG3DIVL ,SSCG PLL3 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "RUNSSCG3CNTR1,RUN SSCG3 Control Register 1" bitfld.long 0x04 24. " SSCG3SSEN ,SSCG PLL3 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG3FREQ ,SSCG PLL3 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG3MODE ,SSCG PLL3 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG3RATE ,SSCG PLL3 clock modulation ratio control bits" group.long 0xC4++0x07 line.long 0x00 "RUNLVDCFGR,RUN Low-voltage Detection Setting Register" bitfld.long 0x00 30. " LVDL1S ,Internal low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x00 24. " LVDL1E ,Internal low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " LVDL2S ,Extended internal low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x00 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 9.--11. " LVDH1V ,External low-voltage detection voltage setting bits" "2.7,2.8,3.6,3.8,4.0,4.2,2.5,2.6" bitfld.long 0x00 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 1.--3. " LVDH2V ,Extended external low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled" line.long 0x04 "RUNCSVCFGR,Run Clock Supervisor Setting Register" bitfld.long 0x04 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x04 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " SCRCSVE ,Low-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " FCRCSVE ,High-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled" rgroup.long 0xCC++0x3 line.long 0x00 "RUNREGCFGR,RUN Regular Setting Register" bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,?..." wgroup.long 0xFC++0x3 line.long 0x00 "TRGRUNCNTR,RUN Update Trigger Register" hexmask.long.byte 0x00 0.--7. 1. " APPLY_RUN ,RUN profile update trigger setting bit" tree.end tree "PSS Profile Register Group" group.long 0x100++0x0B line.long 0x00 "PSSPDCFGR,PSS Power Domain Setting Register" bitfld.long 0x00 25. " PD6_1EN ,Power domain 6_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 24. " PD6_0EN ,Power domain 6_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 23. " PD5_3EN ,Power domain 5_3 power supply control bit" "No supply,Supply" bitfld.long 0x00 22. " PD5_2EN ,Power domain 5_2 power supply control bit" "No supply,Supply" bitfld.long 0x00 21. " PD5_1EN ,Power domain 5_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 20. " PD5_0EN ,Power domain 5_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 17. " PD4_1EN ,Power domain 4_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 16. " PD4_0EN ,Power domain 4_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 12. " PD3EN ,Power domain 3 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 8. " PD2EN ,Power domain 2 power supply control bit" "No supply,Supply" line.long 0x04 "PSSCKSRER,PSS Clock Source Enable Register" bitfld.long 0x04 19. " SSCG3EN ,SSCG PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2EN ,SSCG PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1EN ,SSCG PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0EN ,SSCG PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 11. " PLL3EN ,PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2EN ,PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1EN ,PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0EN ,PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 0. " CROSCEN ,High-speed CR clock oscillation enable bit" "Disabled,Enabled" line.long 0x08 "PSSCKSELR,PSS Clock Selection Register" bitfld.long 0x08 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG PLL0,,Clock fixed at L" rgroup.long 0x10C++0x03 line.long 0x00 "PSSCKER,PSS Clock Enable Register" bitfld.long 0x00 1. " ENCLKMCUCP ,MCU config APB clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " ENCLKMCUCH ,MCU config AHB clock oscillation enable bit" "Disabled,Enabled" group.long 0x110++0x03 line.long 0x00 "PSSCKDIVR,PSS Clock Divider Register" bitfld.long 0x00 8.--11. " MCUCPDIV ,MCU config APB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " MCUCHDIV ,MCU config AHB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x114++0x03 line.long 0x00 "PSSPLL0CNTR,PSS PLL0 Control Register" bitfld.long 0x00 31. " PLL0ISEL ,PLL0 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL0DIVN ,PLL0 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL0DIVM ,PLL0 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL0DIVL ,PLL0 input clock divider setting bits" "No division,/2,/4,/6" group.long 0x124++0x07 line.long 0x00 "PSSSSCG0CNTR0,PSS SSCG0 Control Register 0" bitfld.long 0x00 31. " SSCG0ISEL ,SSCG PLL0 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG0DIVN ,SSCG PLL0 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG0DIVM ,SSCG PLL0 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG0DIVL ,SSCG PLL0 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "PSSSSCG0CNTR1,PSS SSCG0 Control Register 1" bitfld.long 0x04 24. " SSCG0SSEN ,SSCG PLL0 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG0FREQ ,SSCG PLL0 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG0MODE ,SSCG PLL0 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG0RATE ,SSCG PLL0 clock modulation ratio control bits" group.long 0x118++0x03 line.long 0x00 "PSSPLL1CNTR,PSS PLL1 Control Register" bitfld.long 0x00 31. " PLL1ISEL ,PLL1 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL1DIVN ,PLL1 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL1DIVM ,PLL1 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL1DIVL ,PLL1 input clock divider setting bits" "No division,/2,/4,/6" group.long 0x12C++0x07 line.long 0x00 "PSSSSCG1CNTR0,PSS SSCG1 Control Register 0" bitfld.long 0x00 31. " SSCG1ISEL ,SSCG PLL1 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG1DIVN ,SSCG PLL1 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG1DIVM ,SSCG PLL1 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG1DIVL ,SSCG PLL1 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "PSSSSCG1CNTR1,PSS SSCG1 Control Register 1" bitfld.long 0x04 24. " SSCG1SSEN ,SSCG PLL1 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG1FREQ ,SSCG PLL1 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG1MODE ,SSCG PLL1 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG1RATE ,SSCG PLL1 clock modulation ratio control bits" group.long 0x11C++0x03 line.long 0x00 "PSSPLL2CNTR,PSS PLL2 Control Register" bitfld.long 0x00 31. " PLL2ISEL ,PLL2 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL2DIVN ,PLL2 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL2DIVM ,PLL2 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL2DIVL ,PLL2 input clock divider setting bits" "No division,/2,/4,/6" group.long 0x134++0x07 line.long 0x00 "PSSSSCG2CNTR0,PSS SSCG2 Control Register 0" bitfld.long 0x00 31. " SSCG2ISEL ,SSCG PLL2 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG2DIVN ,SSCG PLL2 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG2DIVM ,SSCG PLL2 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG2DIVL ,SSCG PLL2 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "PSSSSCG2CNTR1,PSS SSCG2 Control Register 1" bitfld.long 0x04 24. " SSCG2SSEN ,SSCG PLL2 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG2FREQ ,SSCG PLL2 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG2MODE ,SSCG PLL2 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG2RATE ,SSCG PLL2 clock modulation ratio control bits" group.long 0x120++0x03 line.long 0x00 "PSSPLL3CNTR,PSS PLL3 Control Register" bitfld.long 0x00 31. " PLL3ISEL ,PLL3 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL3DIVN ,PLL3 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL3DIVM ,PLL3 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL3DIVL ,PLL3 input clock divider setting bits" "No division,/2,/4,/6" group.long 0x13C++0x07 line.long 0x00 "PSSSSCG3CNTR0,PSS SSCG3 Control Register 0" bitfld.long 0x00 31. " SSCG3ISEL ,SSCG PLL3 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG3DIVN ,SSCG PLL3 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG3DIVM ,SSCG PLL3 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG3DIVL ,SSCG PLL3 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "PSSSSCG3CNTR1,PSS SSCG3 Control Register 1" bitfld.long 0x04 24. " SSCG3SSEN ,SSCG PLL3 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG3FREQ ,SSCG PLL3 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG3MODE ,SSCG PLL3 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG3RATE ,SSCG PLL3 clock modulation ratio control bits" group.long 0x144++0x07 line.long 0x00 "PSSLVDCFGR,PSS Low-voltage Detection Setting Register" bitfld.long 0x00 30. " LVDL1S ,Internal low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x00 24. " LVDL1E ,Internal low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " LVDL2S ,Extended internal low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x00 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 9.--11. " LVDH1V ,External low-voltage detection voltage setting bits" "2.7,2.8,3.6,3.8,4.0,4.2,2.5,2.6" bitfld.long 0x00 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 1.--3. " LVDH2V ,Extended external low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled" line.long 0x04 "PSSCSVCFGR,PSS Clock Supervisor Setting Register" bitfld.long 0x04 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x04 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " SCRCSVE ,Low-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " FCRCSVE ,High-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled" rgroup.long 0x14C++0x3 line.long 0x00 "PSSREGCFGR,PSS Regular Setting Register" bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,Standby" group.long 0x17C++0x03 line.long 0x00 "PSSENR,PSS Profile Update Enable Register" hexmask.long.byte 0x00 0.--7. 1. " PSSEN0 ,PSS profile update enable setting bits" tree.end tree "APP Profile Register Group" rgroup.long 0x180++0x13 line.long 0x00 "APPPDCFGR,APP Power Domain Setting Register" bitfld.long 0x00 25. " PD6_1EN ,Power domain 6_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 24. " PD6_0EN ,Power domain 6_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 23. " PD5_3EN ,Power domain 5_3 power supply control bit" "No supply,Supply" bitfld.long 0x00 22. " PD5_2EN ,Power domain 5_2 power supply control bit" "No supply,Supply" bitfld.long 0x00 21. " PD5_1EN ,Power domain 5_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 20. " PD5_0EN ,Power domain 5_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 17. " PD4_1EN ,Power domain 4_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 16. " PD4_0EN ,Power domain 4_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 12. " PD3EN ,Power domain 3 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 8. " PD2EN ,Power domain 2 power supply control bit" "No supply,Supply" line.long 0x04 "APPCKSRER,APP Clock Source Enable Register" bitfld.long 0x04 19. " SSCG3EN ,SSCG PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2EN ,SSCG PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1EN ,SSCG PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0EN ,SSCG PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 11. " PLL3EN ,PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2EN ,PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1EN ,PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0EN ,PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 0. " CROSCEN ,High-speed CR clock oscillation enable bit" "Disabled,Enabled" line.long 0x08 "APPCKSELR,APP Clock Selection Register" bitfld.long 0x08 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG PLL0,,Clock fixed at L" line.long 0x0C "APPCKER,APP Clock Enable Register" bitfld.long 0x0C 1. " ENCLKMCUCP ,MCU config APB clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 0. " ENCLKMCUCH ,MCU config AHB clock oscillation enable bit" "Disabled,Enabled" line.long 0x10 "APPCKDIVR,APP Clock Divider Register" bitfld.long 0x10 8.--11. " MCUCPDIV ,MCU config APB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 0.--4. " MCUCHDIV ,MCU config AHB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" rgroup.long 0x194++0x03 line.long 0x00 "APPPLL0CNTR,APP PLL0 Control Register" bitfld.long 0x00 31. " PLL0ISEL ,PLL0 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL0DIVN ,PLL0 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL0DIVM ,PLL0 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL0DIVL ,PLL0 input clock divider setting bits" "No division,/2,/4,/6" rgroup.long 0x1A4++0x07 line.long 0x00 "APPSSCG0CNTR0,APP SSCG0 Control Register 0" bitfld.long 0x00 31. " SSCG0ISEL ,SSCG PLL0 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG0DIVN ,SSCG PLL0 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG0DIVM ,SSCG PLL0 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG0DIVL ,SSCG PLL0 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "APPSSCG0CNTR1,APP SSCG0 Control Register 1" bitfld.long 0x04 24. " SSCG0SSEN ,SSCG PLL0 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG0FREQ ,SSCG PLL0 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG0MODE ,SSCG PLL0 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG0RATE ,SSCG PLL0 clock modulation ratio control bits" rgroup.long 0x198++0x03 line.long 0x00 "APPPLL1CNTR,APP PLL1 Control Register" bitfld.long 0x00 31. " PLL1ISEL ,PLL1 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL1DIVN ,PLL1 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL1DIVM ,PLL1 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL1DIVL ,PLL1 input clock divider setting bits" "No division,/2,/4,/6" rgroup.long 0x1AC++0x07 line.long 0x00 "APPSSCG1CNTR0,APP SSCG1 Control Register 0" bitfld.long 0x00 31. " SSCG1ISEL ,SSCG PLL1 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG1DIVN ,SSCG PLL1 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG1DIVM ,SSCG PLL1 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG1DIVL ,SSCG PLL1 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "APPSSCG1CNTR1,APP SSCG1 Control Register 1" bitfld.long 0x04 24. " SSCG1SSEN ,SSCG PLL1 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG1FREQ ,SSCG PLL1 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG1MODE ,SSCG PLL1 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG1RATE ,SSCG PLL1 clock modulation ratio control bits" rgroup.long 0x19C++0x03 line.long 0x00 "APPPLL2CNTR,APP PLL2 Control Register" bitfld.long 0x00 31. " PLL2ISEL ,PLL2 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL2DIVN ,PLL2 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL2DIVM ,PLL2 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL2DIVL ,PLL2 input clock divider setting bits" "No division,/2,/4,/6" rgroup.long 0x1B4++0x07 line.long 0x00 "APPSSCG2CNTR0,APP SSCG2 Control Register 0" bitfld.long 0x00 31. " SSCG2ISEL ,SSCG PLL2 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG2DIVN ,SSCG PLL2 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG2DIVM ,SSCG PLL2 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG2DIVL ,SSCG PLL2 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "APPSSCG2CNTR1,APP SSCG2 Control Register 1" bitfld.long 0x04 24. " SSCG2SSEN ,SSCG PLL2 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG2FREQ ,SSCG PLL2 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG2MODE ,SSCG PLL2 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG2RATE ,SSCG PLL2 clock modulation ratio control bits" rgroup.long 0x1A0++0x03 line.long 0x00 "APPPLL3CNTR,APP PLL3 Control Register" bitfld.long 0x00 31. " PLL3ISEL ,PLL3 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL3DIVN ,PLL3 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " PLL3DIVM ,PLL3 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL3DIVL ,PLL3 input clock divider setting bits" "No division,/2,/4,/6" rgroup.long 0x1BC++0x07 line.long 0x00 "APPSSCG3CNTR0,APP SSCG3 Control Register 0" bitfld.long 0x00 31. " SSCG3ISEL ,SSCG PLL3 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG3DIVN ,SSCG PLL3 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG3DIVM ,SSCG PLL3 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG3DIVL ,SSCG PLL3 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "APPSSCG3CNTR1,APP SSCG3 Control Register 1" bitfld.long 0x04 24. " SSCG3SSEN ,SSCG PLL3 modulation enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG3FREQ ,SSCG PLL3 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG3MODE ,SSCG PLL3 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG3RATE ,SSCG PLL3 clock modulation ratio control bits" rgroup.long 0x1C4++0x0B line.long 0x00 "APPLVDCFGR,APP Low-voltage Detection Setting Register" bitfld.long 0x00 30. " LVDL1S ,Internal low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x00 24. " LVDL1E ,Internal low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 22. " LVDL2S ,Extended internal low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x00 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 9.--11. " LVDH1V ,External low-voltage detection voltage setting bits" "2.7,2.8,3.6,3.8,4.0,4.2,2.5,2.6" bitfld.long 0x00 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 1.--3. " LVDH2V ,Extended external low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled" line.long 0x04 "APPCSVCFGR,APP Clock Supervisor Setting Register" bitfld.long 0x04 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x04 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " SCRCSVE ,Low-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " FCRCSVE ,High-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled" line.long 0x08 "APPREGCFGR,APP Regular Setting Register" bitfld.long 0x08 7. " RMSEL ,Regulator mode setting bit" "Main,Standby" tree.end tree "STS Profile Register Group" rgroup.long 0x200++0x13 line.long 0x00 "STSPDCFGR,STS Power Domain Setting Register" bitfld.long 0x00 25. " PD6_1EN ,Power domain 6_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 24. " PD6_0EN ,Power domain 6_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 23. " PD5_3EN ,Power domain 5_3 power supply control bit" "No supply,Supply" bitfld.long 0x00 22. " PD5_2EN ,Power domain 5_2 power supply control bit" "No supply,Supply" bitfld.long 0x00 21. " PD5_1EN ,Power domain 5_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 20. " PD5_0EN ,Power domain 5_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 17. " PD4_1EN ,Power domain 4_1 power supply control bit" "No supply,Supply" bitfld.long 0x00 16. " PD4_0EN ,Power domain 4_0 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 12. " PD3EN ,Power domain 3 power supply control bit" "No supply,Supply" newline bitfld.long 0x00 8. " PD2EN ,Power domain 2 power supply control bit" "No supply,Supply" line.long 0x04 "STSCKSRER,STS Clock Source Enable Register" bitfld.long 0x04 23. " SSCG3RDY ,SSCG PLL3 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x04 22. " SSCG2RDY ,SSCG PLL2 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x04 21. " SSCG1RDY ,SSCG PLL1 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x04 20. " SSCG0RDY ,SSCG PLL0 clock oscillation stabilization bit" "Not stable,Stable" newline bitfld.long 0x04 19. " SSCG3EN ,SSCG PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2EN ,SSCG PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1EN ,SSCG PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0EN ,SSCG PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 15. " PLL3RDY ,PLL3 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x04 14. " PLL2RDY ,PLL2 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x04 13. " PLL1RDY ,PLL1 clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x04 12. " PLL0RDY ,PLL0 clock oscillation stabilization bit" "Not stable,Stable" newline bitfld.long 0x04 11. " PLL3EN ,PLL3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2EN ,PLL2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1EN ,PLL1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0EN ,PLL0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x04 7. " SOSCRDY ,Sub clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x04 6. " MOSCRDY ,Main clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x04 5. " SCROSCRDY ,Low-speed CR clock oscillation stabilization bit" "Not stable,Stable" bitfld.long 0x04 4. " CROSCRDY ,High-speed CR clock oscillation stabilization bit" "Not stable,Stable" newline bitfld.long 0x04 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x04 0. " CROSCEN ,High-speed CR clock oscillation enable bit" "Disabled,Enabled" line.long 0x08 "STSCKSELR,STS Clock Selection Register" bitfld.long 0x08 4.--6. " CDMCUCCM ,Clock domain MCUC clock selection status bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG PLL0,,Clock fixed at L" bitfld.long 0x08 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG PLL0,,Clock fixed at L" line.long 0x0C "STSCKER,STS Clock Enable Register" bitfld.long 0x0C 1. " ENCLKMCUCP ,MCU config APB clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 0. " ENCLKMCUCH ,MCU config AHB clock oscillation enable bit" "Disabled,Enabled" line.long 0x10 "STSCKDIVR,STS Clock Divider Register" bitfld.long 0x10 8.--11. " MCUCPDIV ,MCU config APB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x10 0.--4. " MCUCHDIV ,MCU config AHB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" rgroup.long 0x214++0x03 line.long 0x00 "STSPLL0CNTR,STS PLL0 Control Register" bitfld.long 0x00 31. " PLL0ISEL ,PLL0 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL0DIVN ,PLL0 clock N-multiplication rate setting bits" bitfld.long 0x00 8.--11. " PLL0DIVM ,PLL0 output clock M-division ratio setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL0DIVL ,PLL0 clock L-division ratio setting bits" "No division,/2,/4,/6" rgroup.long 0x224++0x07 line.long 0x00 "STSSSCG0CNTR0,STS SSCG0 Control Register 0" bitfld.long 0x00 31. " SSCG0ISEL ,SSCG PLL0 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG0DIVN ,SSCG PLL0 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG0DIVM ,SSCG PLL0 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG0DIVL ,SSCG PLL0 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "STSSSCG0CNTR1,STS SSCG0 Control Register 1" bitfld.long 0x04 24. " SSCG0SSEN ,SSCG PLL0 enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG0FREQ ,SSCG PLL0 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG0MODE ,SSCG PLL0 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG0RATE ,SSCG PLL0 clock modulation ratio control bits" rgroup.long 0x218++0x03 line.long 0x00 "STSPLL1CNTR,STS PLL1 Control Register" bitfld.long 0x00 31. " PLL1ISEL ,PLL1 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL1DIVN ,PLL1 clock N-multiplication rate setting bits" bitfld.long 0x00 8.--11. " PLL1DIVM ,PLL1 output clock M-division ratio setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL1DIVL ,PLL1 clock L-division ratio setting bits" "No division,/2,/4,/6" rgroup.long 0x22C++0x07 line.long 0x00 "STSSSCG1CNTR0,STS SSCG1 Control Register 0" bitfld.long 0x00 31. " SSCG1ISEL ,SSCG PLL1 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG1DIVN ,SSCG PLL1 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG1DIVM ,SSCG PLL1 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG1DIVL ,SSCG PLL1 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "STSSSCG1CNTR1,STS SSCG1 Control Register 1" bitfld.long 0x04 24. " SSCG1SSEN ,SSCG PLL1 enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG1FREQ ,SSCG PLL1 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG1MODE ,SSCG PLL1 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG1RATE ,SSCG PLL1 clock modulation ratio control bits" rgroup.long 0x21C++0x03 line.long 0x00 "STSPLL2CNTR,STS PLL2 Control Register" bitfld.long 0x00 31. " PLL2ISEL ,PLL2 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL2DIVN ,PLL2 clock N-multiplication rate setting bits" bitfld.long 0x00 8.--11. " PLL2DIVM ,PLL2 output clock M-division ratio setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL2DIVL ,PLL2 clock L-division ratio setting bits" "No division,/2,/4,/6" rgroup.long 0x234++0x07 line.long 0x00 "STSSSCG2CNTR0,STS SSCG2 Control Register 0" bitfld.long 0x00 31. " SSCG2ISEL ,SSCG PLL2 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG2DIVN ,SSCG PLL2 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG2DIVM ,SSCG PLL2 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG2DIVL ,SSCG PLL2 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "STSSSCG2CNTR1,STS SSCG2 Control Register 1" bitfld.long 0x04 24. " SSCG2SSEN ,SSCG PLL2 enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG2FREQ ,SSCG PLL2 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG2MODE ,SSCG PLL2 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG2RATE ,SSCG PLL2 clock modulation ratio control bits" rgroup.long 0x220++0x03 line.long 0x00 "STSPLL3CNTR,STS PLL3 Control Register" bitfld.long 0x00 31. " PLL3ISEL ,PLL3 input clock selection bit" "Main clock,High-speed" hexmask.long.byte 0x00 16.--23. 1. " PLL3DIVN ,PLL3 clock N-multiplication rate setting bits" bitfld.long 0x00 8.--11. " PLL3DIVM ,PLL3 output clock M-division ratio setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " PLL3DIVL ,PLL3 clock L-division ratio setting bits" "No division,/2,/4,/6" rgroup.long 0x23C++0x07 line.long 0x00 "STSSSCG3CNTR0,STS SSCG3 Control Register 0" bitfld.long 0x00 31. " SSCG3ISEL ,SSCG PLL3 input clock selection bit" "Main clock,High-speed CR" hexmask.long.byte 0x00 16.--23. 1. " SSCG3DIVN ,SSCG PLL3 clock N-multiplier setting bits" bitfld.long 0x00 8.--11. " SSCG3DIVM ,SSCG PLL3 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30" bitfld.long 0x00 0.--1. " SSCG3DIVL ,SSCG PLL3 input clock divider setting bits" "No division,/2,/4,/6" line.long 0x04 "STSSSCG3CNTR1,STS SSCG3 Control Register 1" bitfld.long 0x04 24. " SSCG3SSEN ,SSCG PLL3 enable setting bit" "Disabled,Enabled" bitfld.long 0x04 17.--18. " SSCG3FREQ ,SSCG PLL3 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096" bitfld.long 0x04 16. " SSCG3MODE ,SSCG PLL3 modulation mode setting bit" "Down,Center" hexmask.long.word 0x04 0.--9. 1. " SSCG3RATE ,SSCG PLL3 clock modulation ratio control bits" newline rgroup.long 0x244++0x0B line.long 0x00 "STSLVDCFGR,STS Low-voltage Detection Setting Register" bitfld.long 0x00 31. " LVDL1R ,Internal low-voltage detection operation status bit" "Stabilization wait/Monitoring stop,Monitoring" bitfld.long 0x00 30. " LVDL1S ,Internal low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x00 24. " LVDL1E ,Internal low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 23. " LVDL2R ,Extended low-voltage detection operation status bit" "Stabilization wait/Monitoring stop,Monitoring" bitfld.long 0x00 22. " LVDL2S ,Extended internal low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" "0,1,2,3" bitfld.long 0x00 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 15. " LVDH1R ,External low-voltage detection operation status bit" "Stabilization wait/Monitoring stop,Monitoring" bitfld.long 0x00 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 9.--11. " LVDH1V ,External low-voltage detection voltage setting bits" "2.7,2.8,3.6,3.8,4.0,4.2,2.5,2.6" bitfld.long 0x00 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " LVDH2R ,Extended external low-voltage detection operation status bit" "Stabilization wait/Monitoring stop,Monitoring" bitfld.long 0x00 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt" bitfld.long 0x00 1.--3. " LVDH2V ,Extended external low-voltage detection voltage setting bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled" newline line.long 0x04 "STSCSVCFGR,STS Clock Supervisor Setting Register" bitfld.long 0x04 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x04 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled" newline bitfld.long 0x04 3. " SCRCSVE ,Low-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 2. " FCRCSVE ,High-speed CR clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled" bitfld.long 0x04 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled" line.long 0x08 "STSREGCFGR,STS Regular Setting Register" bitfld.long 0x08 7. " RMSEL ,Regulator mode setting bit" "Main,Standby" tree.end tree "System Register Group" rgroup.long 0x280++0x0B line.long 0x00 "SYSIDR,System ID Register" line.long 0x04 "SYSPFIDR,Platform ID Register" line.long 0x08 "SYSSTSR,System Status Register" bitfld.long 0x08 7. " PSSSTS0 ,PSS profile update status bit" "Not updated,Updated" bitfld.long 0x08 6. " RUNSTS0 ,RUN profile update status bit" "Not updated,Updated" newline bitfld.long 0x08 5. " PSSDF0 ,PSS profile update completion flag bit" "Not completed,Completed" bitfld.long 0x08 4. " RUNDF0 ,RUN profile update completion (main status control) flag bit" "Not completed,Completed" newline bitfld.long 0x08 1. " CPUSTS0 ,CPU0 device status bit" "Operation,WFI" bitfld.long 0x08 0. " DVSTS0 ,Device status bit" "PSS,RUN" group.long 0x28C++0x07 line.long 0x00 "SYSINTER,System Status Interrupt Enable Register" bitfld.long 0x00 4. " RUNDIE0 ,RUN profile update completion interrupt enable bit" "Disabled,Enabled" line.long 0x04 "SYSICLR,System Status Flag And Interrupt Clear Register" bitfld.long 0x04 5. " PSSDFCLR0 ,PSS profile update completion flag clear bit" "No effect,Clear" bitfld.long 0x04 4. " RUNDFCLR0 ,RUN profile update completion flag clear bit" "No effect,Clear" rgroup.long 0x294++0x07 line.long 0x00 "SYSERRIR0,System Interrupt Factor Register 0" bitfld.long 0x00 29. " LVDH2IF ,Extended external low-voltage detection interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 28. " LVDH1IF ,External low-voltage detection interrupt" "No interrupt,Interrupt" bitfld.long 0x00 25. " LVDL2IF ,Extended internal low-voltage detection interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 24. " LVDL1IF ,Internal low-voltage detection interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " SSCG3IF ,SSCG PLL3 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 18. " SSCG2IF ,SSCG PLL2 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 17. " SSCG1IF ,SSCG PLL1 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 16. " SSCG0IF ,SSCG PLL0 abnormality detection error interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " PLL3IF ,PLL3 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 10. " PLL2IF ,PLL2 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 9. " PLL1IF ,PLL1 abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 8. " PLL0IF ,PLL0 abnormality detection error interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " SOSCIF ,Sub oscillation abnormality detection error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x00 0. " MOSCIF ,Main oscillation abnormality detection error interrupt request bit" "No interrupt,Interrupt" line.long 0x04 "SYSERRIR1,System Error Interrupt Factor Register 1" bitfld.long 0x04 6. " PSSERRIF0 ,PSS profile error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x04 5. " RUNWKERRIF0 ,RUN profile (PSS recovery time) error interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x04 4. " RUNERRIF0 ,RUN profile error interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x04 3. " PSSENERRIF0 ,PSS profile update enable write error interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x04 2. " PSSTRGCIF0 ,PSS trigger cancel interrupt request bit" "No interrupt,Interrupt" bitfld.long 0x04 1. " RUNTRGERRIF ,RUN profile update enable write error interrupt request bit" "No interrupt,Interrupt" newline bitfld.long 0x04 0. " TRGERRIF ,Trigger error interrupt request bit" "No interrupt,Interrupt" group.long 0x29C++0x07 line.long 0x00 "SYSERRICLR0,System Error Interrupt Factor Clear Register 0" bitfld.long 0x00 29. " LVDH2ICLR ,Extended external low-voltage detection interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 28. " LVDH1ICLR ,External external low-voltage detection interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 25. " LVDL2ICLR ,Extended internal low-voltage detection interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 24. " LVDL1ICLR ,Internal low-voltage detection interrupt factor clear bit" "No effect,Clear" newline bitfld.long 0x00 19. " SSCG3ICLR ,SSCG PLL3 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 18. " SSCG2ICLR ,SSCG PLL2 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 17. " SSCG1ICLR ,SSCG PLL1 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 16. " SSCG0ICLR ,SSCG PLL0 abnormality detection error interrupt factor clear bit" "No effect,Clear" newline bitfld.long 0x00 11. " PLL3ICLR ,PLL3 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 10. " PLL2ICLR ,PLL2 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 9. " PLL1ICLR ,PLL1 abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 8. " PLL0ICLR ,PLL0 abnormality detection error interrupt factor clear bit" "No effect,Clear" newline bitfld.long 0x00 1. " SOSCICLR ,Sub oscillation abnormality detection error interrupt factor clear bit" "No effect,Clear" bitfld.long 0x00 0. " MOSCICLR ,Main oscillation abnormality detection error interrupt detection error interrupt factor clear bit" "No effect,Clear" line.long 0x04 "SYSERRICLR1,System Error Interrupt Factor Clear Register 1" bitfld.long 0x04 6. " PSSERRICLR0 ,PSS profile error interrupt request bit" "No effect,Clear" bitfld.long 0x04 5. " RUNWKERRICLR0 ,RUN profile (PSS recovery time) error interrupt request bit" "No effect,Clear" newline bitfld.long 0x04 4. " RUNERRICLR0 ,Run profile error interrupt request bit" "No effect,Clear" bitfld.long 0x04 3. " PSSENERRICLR0 ,PSS profile update enable write error interrupt request bit" "No effect,Clear" newline bitfld.long 0x04 2. " PSSTRGCICLR0 ,PSS trigger cancel interrupt request bit" "No effect,Clear" bitfld.long 0x04 1. " RUNTRGERRICLR ,RUN profile update enable write error interrupt request bit" "No effect,Clear" newline bitfld.long 0x04 0. " TRGERRICLR ,Trigger error interrupt request bit" "No effect,Clear" rgroup.long 0x2A4++0x0B line.long 0x00 "SYSPROSTSR,Profile Status Register" bitfld.long 0x00 2. " PSSPSTS ,PSS profile setting status bit" "No error,Error" bitfld.long 0x00 1. " RUNWKPSTS ,RUN profile (PSS recovery time) setting status bit" "No error,Error" bitfld.long 0x00 0. " RUNPSTS ,RUN profile setting status bit" "No error,Error" line.long 0x04 "SYSRUNPEFR,RUN Profile Error Flag Register" bitfld.long 0x04 6. " PEF6 ,Profile error flag bit" "No error,Error" bitfld.long 0x04 5. " PEF5 ,Profile error flag bit" "No error,Error" bitfld.long 0x04 4. " PEF4 ,Profile error flag bit" "No error,Error" bitfld.long 0x04 3. " PEF3 ,Profile error flag bit" "No error,Error" newline bitfld.long 0x04 2. " PEF2 ,Profile error flag bit" "No error,Error" bitfld.long 0x04 1. " PEF1 ,Profile error flag bit" "No error,Error" bitfld.long 0x04 0. " PEF0 ,Profile error flag bit" "No error,Error" line.long 0x08 "SYSPSSPEFR,PSS Profile Error Flag Register" bitfld.long 0x08 10. " PEF10 ,Profile error flag bit" "No error,Error" bitfld.long 0x08 9. " PEF9 ,Profile error flag bit" "No error,Error" bitfld.long 0x08 8. " PEF8 ,Profile error flag bit" "No error,Error" bitfld.long 0x08 7. " PEF7 ,Profile error flag bit" "No error,Error" newline bitfld.long 0x08 6. " PEF6 ,Profile error flag bit" "No error,Error" bitfld.long 0x08 5. " PEF5 ,Profile error flag bit" "No error,Error" bitfld.long 0x08 4. " PEF4 ,Profile error flag bit" "No error,Error" bitfld.long 0x08 3. " PEF3 ,Profile error flag bit" "No error,Error" newline bitfld.long 0x08 1. " PEF1 ,Profile error flag bit" "No error,Error" bitfld.long 0x08 0. " PEF0 ,Profile error flag bit" "No error,Error" tree.end tree "Special Setting Register Group" group.long 0x680++0x03 line.long 0x00 "SPECFGR,System Special Setting Register" bitfld.long 0x00 31. " HOLDIO_PD6_1 ,Setting bit for power domain 6_1 HOLD data latch" "No retain,Retain" bitfld.long 0x00 30. " HOLDIO_PD6_0 ,Setting bit for power domain 6_0 HOLD data latch" "No retain,Retain" newline bitfld.long 0x00 29. " HOLDIO_PD5_3 ,Setting bit for power domain 5_3 HOLD data latch" "No retain,Retain" bitfld.long 0x00 28. " HOLDIO_PD5_2 ,Setting bit for power domain 5_2 HOLD data latch" "No retain,Retain" bitfld.long 0x00 27. " HOLDIO_PD5_1 ,Setting bit for power domain 5_1 HOLD data latch" "No retain,Retain" bitfld.long 0x00 26. " HOLDIO_PD5_0 ,Setting bit for power domain 5_0 HOLD data latch" "No retain,Retain" newline bitfld.long 0x00 24. " HOLDIO_PD2 ,Power domain 2 HOLD data latch setting bit" "No retain,Retain" newline bitfld.long 0x00 23. " PSSPADCTRL ,PPS-time port configuring bit" "Not performed,Performed" bitfld.long 0x00 22. " IO3RSTC ,I/O 3V reset configuring bit" "No reset,Reset" bitfld.long 0x00 21. " IO35RSTC ,I/O 5/3V reset configuring bit" "No reset,Reset" bitfld.long 0x00 9. " EXVRSTCNT ,Reset level configuring bit for external power supply control" "Reset,No reset" newline bitfld.long 0x00 8. " BRAMSC ,Backup RAM standby setting bit" "Disabled,Enabled" bitfld.long 0x00 4.--7. " EX5VRSTCNT ,5/3.3V external power supply stabilization time setting bits 4MHz/8MHz" "1.0/0.5,2.0/1.0,3.0/1.5,4.0/2.0,5.0/2.5,6.0/3.0,7.0/3.5,8.0/4.0,9.0/4.5,10.0/5.0,12.0/6.0,14.0/7.0,16.0/8.0,18.0/9.0,20.0/10.0,30.0/15.0" bitfld.long 0x00 0.--3. " EX12VRSTCNT ,1.2V external power supply stabilization time setting bits" "1.0/0.5,2.0/1.0,3.0/1.5,4.0/2.0,5.0/2.5,6.0/3.0,7.0/3.5,8.0/4.0,9.0/4.5,10.0/5.0,12.0/6.0,14.0/7.0,16.0/8.0,18.0/9.0,20.0/10.0,30.0/15.0" tree.end tree "Debug Register Group" rgroup.long 0x80++0x03 line.long 0x00 "JTAGDETECT,JTAG Detection Register" bitfld.long 0x00 0. " DBGCON ,Debugger connection status bit" "Not connected,Connected" group.long 0x84++0x07 line.long 0x00 "JTAGCNFG,JTAG Setting Register" bitfld.long 0x00 0. " DBGDONE ,Debugger status bit" "Connected,Not connected" line.long 0x04 "JTAGWAKEUP,JTAG Recovery Register" bitfld.long 0x04 0. " DBGWKEN ,Debugger wakeup enable bit" "Disabled,Enabled" tree.end width 0x0B tree.end tree "MCG (MCU Config Group)" base ad:0xB0688800 width 7. rgroup.long 0x00++0x13 line.long 0x00 "IRSR0,MCU Config Interrupt Request Status Register 0" bitfld.long 0x00 24. " IRQ_PW ,Partial wakeup interrupt" "No interrupt,Interrupt" bitfld.long 0x00 19. " IRQ_SCT_SUB ,Sub source clock timer interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQ_SCT_MAIN ,Main source clock timer interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQ_SCT_SCR ,Low-speed source clock timer interrupt detection status" "No interrupt,Interrupt" newline bitfld.long 0x00 16. " IRQ_SCT_CR ,High-speed source clock timer interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQ_RTC ,RTC 0.5 seconds interrupt detection status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQ_SCU ,RUN profile update complete interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQ_HWDG ,Hardware watchdog timer advance warning interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " NMI_EXTINT ,NMI detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 2. " NMI_HWDG ,Hardware watchdog timer detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 1. " NMI_SCU ,Profile error detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 0. " NMI_LVD ,Low power detection interrupt status" "No interrupt,Interrupt" line.long 0x04 "IRSR1,MCU Config Interrupt Request Status Register 1" bitfld.long 0x04 31. " IRQ_EXTINT[31] ,External interrupt channel 31 detection status" "No interrupt,Interrupt" bitfld.long 0x04 30. " [30] ,External interrupt channel 30 detection status" "No interrupt,Interrupt" bitfld.long 0x04 29. " [29] ,External interrupt channel 29 detection status" "No interrupt,Interrupt" bitfld.long 0x04 28. " [28] ,External interrupt channel 28 detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 27. " [27] ,External interrupt channel 27 detection status" "No interrupt,Interrupt" bitfld.long 0x04 26. " [26] ,External interrupt channel 26 detection status" "No interrupt,Interrupt" bitfld.long 0x04 25. " [25] ,External interrupt channel 25 detection status" "No interrupt,Interrupt" bitfld.long 0x04 24. " [24] ,External interrupt channel 24 detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 23. " [23] ,External interrupt channel 23 detection status" "No interrupt,Interrupt" bitfld.long 0x04 22. " [22] ,External interrupt channel 22 detection status" "No interrupt,Interrupt" bitfld.long 0x04 21. " [21] ,External interrupt channel 21 detection status" "No interrupt,Interrupt" bitfld.long 0x04 20. " [20] ,External interrupt channel 20 detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 19. " [19] ,External interrupt channel 19 detection status" "No interrupt,Interrupt" bitfld.long 0x04 18. " [18] ,External interrupt channel 18 detection status" "No interrupt,Interrupt" bitfld.long 0x04 17. " [17] ,External interrupt channel 17 detection status" "No interrupt,Interrupt" bitfld.long 0x04 16. " [16] ,External interrupt channel 16 detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 15. " [15] ,External interrupt channel 15 detection status" "No interrupt,Interrupt" bitfld.long 0x04 14. " [14] ,External interrupt channel 14 detection status" "No interrupt,Interrupt" bitfld.long 0x04 13. " [13] ,External interrupt channel 13 detection status" "No interrupt,Interrupt" bitfld.long 0x04 12. " [12] ,External interrupt channel 12 detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 11. " [11] ,External interrupt channel 11 detection status" "No interrupt,Interrupt" bitfld.long 0x04 10. " [10] ,External interrupt channel 10 detection status" "No interrupt,Interrupt" bitfld.long 0x04 9. " [9] ,External interrupt channel 9 detection status" "No interrupt,Interrupt" bitfld.long 0x04 8. " [8] ,External interrupt channel 8 detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 7. " [7] ,External interrupt channel 7 detection status" "No interrupt,Interrupt" bitfld.long 0x04 6. " [6] ,External interrupt channel 6 detection status" "No interrupt,Interrupt" bitfld.long 0x04 5. " [5] ,External interrupt channel 5 detection status" "No interrupt,Interrupt" bitfld.long 0x04 4. " [4] ,External interrupt channel 4 detection status" "No interrupt,Interrupt" newline bitfld.long 0x04 3. " [3] ,External interrupt channel 3 detection status" "No interrupt,Interrupt" bitfld.long 0x04 2. " [2] ,External interrupt channel 2 detection status" "No interrupt,Interrupt" bitfld.long 0x04 1. " [1] ,External interrupt channel 1 detection status" "No interrupt,Interrupt" bitfld.long 0x04 0. " [0] ,External interrupt channel 0 detection status" "No interrupt,Interrupt" line.long 0x08 "IRSR2,MCU Config Interrupt Request Register 2" bitfld.long 0x08 18. " IRQ_RLT2 ,Reload timer channel 2 interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 17. " IRQ_RLT1 ,Reload timer channel 1 interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 16. " IRQ_RLT0 ,Reload timer channel 0 interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 9. " IRQ_CRCAL ,CR calibration complete interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x08 8. " IRQ_EICU ,EICU complete interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 4. " IRQ_RAMIC ,BackUP-RAM initialization end interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 3. " IRQ_RAMTE ,BackUP-RAM diagnosis error interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 2. " IRQ_RAMTC ,BackUP-RAM diagnosis end interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x08 1. " IRQ_RAMSE ,BackUP-RAM single-bit error interrupt status" "No interrupt,Interrupt" bitfld.long 0x08 0. " NMI_RAMDE ,BackUP-RAM double-bit error interrupt status" "No interrupt,Interrupt" line.long 0x0C "IRSR3,MCU Config Interrupt Request Status Register 3" bitfld.long 0x0C 30. " IRQ_MCAN2_INT1 ,CAN-FD channel 2 interrupt 1 status" "No interrupt,Interrupt" bitfld.long 0x0C 29. " IRQ_MCAN1_INT1 ,CAN-FD channel 1 interrupt 1 status" "No interrupt,Interrupt" bitfld.long 0x0C 28. " IRQ_MCAN0_INT1 ,CAN-FD channel 0 interrupt 1 status" "No interrupt,Interrupt" bitfld.long 0x0C 26. " IRQ_MCAN2_INT0 ,CAN-FD channel 2 interrupt 0 status" "No interrupt,Interrupt" newline bitfld.long 0x0C 25. " IRQ_MCAN1_INT0 ,CAN-FD channel 1 interrupt 0 status" "No interrupt,Interrupt" bitfld.long 0x0C 24. " IRQ_MCAN0_INT0 ,CAN-FD channel 0 interrupt 0 status" "No interrupt,Interrupt" bitfld.long 0x0C 22. " IRQ_MCAN2_SE ,CAN-FB channel 2 RAM ECC single-bit error detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 21. " IRQ_MCAN1_SE ,CAN-FB channel 1 RAM ECC single-bit error detection interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x0C 20. " IRQ_MCAN0_SE ,CAN-FD channel 0 RAM ECC single-bit error detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 18. " NMI_MCAN2_DE ,CAN-FD channel 2 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 17. " NMI_MCAN1_DE ,CAN-FD channel 1 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 16. " NMI_MCAN0_DE ,CAN-FD channel 0 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x0C 10. " IRQ_MFS2_SIRQ ,MFS channel 2 sync field detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 9. " IRQ_MFS1_SIRQ ,MFS channel 1 sync field detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 8. " IRQ_MFS0_SIRQ ,MFS channel 0 sync field detection interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 6. " IRQ_MFS2_RIRQ ,MFS channel 2 reception interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x0C 5. " IRQ_MFS1_RIRQ ,MFS channel 1 reception interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 4. " IRQ_MFS0_RIRQ ,MFS channel 0 reception interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 2. " IRQ_MFS2_TIRQ ,MFS channel 2 transmission interrupt status" "No interrupt,Interrupt" bitfld.long 0x0C 1. " IRQ_MFS1_TIRQ ,MFS channel 1 transmission interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x0C 0. " IRQ_MFS0_TIRQ ,MFS channel 0 transmission interrupt status" "No interrupt,Interrupt" line.long 0x10 "IRSR4,MCU Config Interrupt Request Status Register 4" bitfld.long 0x10 6. " IRQ_MFS2_REIRQ ,MFS channel 2 reception interrupt status" "No interrupt,Interrupt" bitfld.long 0x10 5. " IRQ_MFS1_REIRQ ,MFS channel 1 reception interrupt status" "No interrupt,Interrupt" bitfld.long 0x10 4. " IRQ_MFS0_REIRQ ,MFS channel 0 reception interrupt status" "No interrupt,Interrupt" bitfld.long 0x10 2. " IRQ_MFS2_TEIRQ ,MFS channel 2 transmission interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x10 1. " IRQ_MFS1_TEIRQ ,MFS channel 1 transmission interrupt status" "No interrupt,Interrupt" bitfld.long 0x10 0. " IRQ_MFS0_TEIRQ ,MFS channel 0 transmission interrupt status" "No interrupt,Interrupt" width 0x0B tree.end tree "SYSC1 (System Controller 1)" base ad:0xB0300000 width 13. tree "Protection Register Group" group.long 0x00++0x03 line.long 0x00 "PROTKEYR,Protection Key Setting Register" tree.end tree "RUN Profile Register Group" group.long 0x80++0x2B line.long 0x00 "RUNCKSELR0,RUN Clock Selection Register 0" bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PPL0" bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PPL0" newline bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PPL0" bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PPL0" bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG0,,Clock fixed at L" line.long 0x04 "RUNCKSELR1,RUN Clock Selection Register 1" bitfld.long 0x04 24.--27. " CD4CSL ,Clock domain 4 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 16.--19. " CD3CSL ,Clock domain 3 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 8.--11. " CD2CSL ,Clock domain 2 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 0.--3. " CD1CSL ,Clock domain 1 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" line.long 0x08 "RUNCKSELR2,RUN Clock Selection Register 2" bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG0,PLL1,Clock fixed at L" bitfld.long 0x08 0.--3. " CD5CSL ,Clock domain 5 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" newline line.long 0x0C "RUNCKER0,RUN Clock Source Enable Register 0" rbitfld.long 0x0C 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x0C 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x0C 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x0C 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x0C 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x0C 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled" rbitfld.long 0x0C 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled" line.long 0x10 "RUNCKER1,RUN Clock Source Enable Register 1" bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled" line.long 0x14 "RUNCKER2,RUN Source Enable Register 2" bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled" line.long 0x18 "RUNCKDIVR0,RUN Clock Divider Register 0" bitfld.long 0x18 24.--26. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x18 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8" newline bitfld.long 0x18 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8" bitfld.long 0x18 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x1C "RUNCKDIVR1,RUN Clock Divider Register 1" bitfld.long 0x1C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x1C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 0.--2. " EXTBUSDIV ,EXTBUT clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128" line.long 0x20 "RUNCKDIVR2,RUN Clock Divider Register 2" bitfld.long 0x20 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x20 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8" line.long 0x24 "RUNCKDIVR3,RUN Clock Divider Register 3" bitfld.long 0x24 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x28 "RUNCKDIVR4,RUN Clock Divider Register 4" bitfld.long 0x28 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0xAC++0x03 line.long 0x00 "RUNCKDIVR5,RUN Clock Divider Register 5" bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD1B0DIV ,CD1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0xB0++0x03 line.long 0x00 "RUNCKDIVR6,RUN Clock Divider Register 6" bitfld.long 0x00 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0xB4++0x03 line.long 0x00 "RUNCKDIVR7,RUN Clock Divider Register 7" bitfld.long 0x00 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0xB8++0x03 line.long 0x00 "RUNCKDIVR8,RUN Clock Divider Register 8" bitfld.long 0x00 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0xBC++0x03 line.long 0x00 "RUNCKDIVR9,RUN Clock Divider Register 9" bitfld.long 0x00 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0xFC++0x03 line.long 0x00 "RUNENR,RUN Profile Update Enable Register" hexmask.long.byte 0x00 0.--7. 1. " RUNEN1 ,RUN profile update enable" tree.end tree "PSS Profile Register Group" group.long 0x100++0x2B line.long 0x00 "PSSCKSELR0,PSS Clock Selection Register 0" bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PPL0" bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PPL0" newline bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PPL0" bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PPL0" bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG0,,Clock fixed at L" line.long 0x04 "PSSCKSELR1,PSS Clock Selection Register 1" bitfld.long 0x04 24.--27. " CD4CSL ,Clock domain 4 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 16.--19. " CD3CSL ,Clock domain 3 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 8.--11. " CD2CSL ,Clock domain 2 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 0.--3. " CD1CSL ,Clock domain 1 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" line.long 0x08 "PSSCKSELR2,PSS Clock Selection Register 2" bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG0,PLL1,Clock fixed at L" bitfld.long 0x08 0.--3. " CD5CSL ,Clock domain 5 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" newline line.long 0x0C "PSSCKER0,PSS Clock Source Enable Register 0" bitfld.long 0x0C 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled" newline rbitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled" line.long 0x10 "PSSCKER1,PSS Clock Source Enable Register 1" bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled" line.long 0x14 "PSSCKER2,PSS Source Enable Register 2" bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled" line.long 0x18 "PSSCKDIVR0,PSS Clock Divider Register 0" bitfld.long 0x18 24.--26. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x18 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8" newline bitfld.long 0x18 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8" bitfld.long 0x18 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x1C "PSSCKDIVR1,PSS Clock Divider Register 1" bitfld.long 0x1C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x1C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 0.--2. " EXTBUSDIV ,EXTBUT clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128" line.long 0x20 "PSSCKDIVR2,PSS Clock Divider Register 2" bitfld.long 0x20 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x20 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8" line.long 0x24 "PSSCKDIVR3,PSS Clock Divider Register 3" bitfld.long 0x24 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x28 "PSSCKDIVR4,PSS Clock Divider Register 4" bitfld.long 0x28 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x12C++0x03 line.long 0x00 "PSSCKDIVR5,PSS Clock Divider Register 5" bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD1B0DIV ,CD1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x130++0x03 line.long 0x00 "PSSCKDIVR6,PSS Clock Divider Register 6" bitfld.long 0x00 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x134++0x03 line.long 0x00 "PSSCKDIVR7,PSS Clock Divider Register 7" bitfld.long 0x00 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x138++0x03 line.long 0x00 "PSSCKDIVR8,PSS Clock Divider Register 8" bitfld.long 0x00 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x13C++0x03 line.long 0x00 "PSSCKDIVR9,PSS Clock Divider Register 9" bitfld.long 0x00 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x17C++0x03 line.long 0x00 "PSSENR,PSS Profile Update Enable Register" hexmask.long.byte 0x00 0.--7. 1. " PSSEN1 ,PSS profile update enable" tree.end tree "APP Profile Register Group" rgroup.long 0x180++0x2B line.long 0x00 "APPCKSELR0,APP Clock Selection Register 0" bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PPL0" bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PPL0" newline bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PPL0" bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PPL0" bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG0,,Clock fixed at L" line.long 0x04 "APPCKSELR1,APP Clock Selection Register 1" bitfld.long 0x04 24.--27. " CD4CSL ,Clock domain 4 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 16.--19. " CD3CSL ,Clock domain 3 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 8.--11. " CD2CSL ,Clock domain 2 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 0.--3. " CD1CSL ,Clock domain 1 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" line.long 0x08 "APPCKSELR2,APP Clock Selection Register 2" bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG0,PLL1,Clock fixed at L" bitfld.long 0x08 0.--3. " CD5CSL ,Clock domain 5 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" newline line.long 0x0C "APPCKER0,APP Clock Source Enable Register 0" bitfld.long 0x0C 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled" line.long 0x10 "APPCKER1,APP Clock Source Enable Register 1" bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled" line.long 0x14 "APPCKER2,APP Source Enable Register 2" bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled" line.long 0x18 "APPCKDIVR0,APP Clock Divider Register 0" bitfld.long 0x18 24.--26. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x18 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8" newline bitfld.long 0x18 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8" bitfld.long 0x18 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x1C "APPCKDIVR1,APP Clock Divider Register 1" bitfld.long 0x1C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x1C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 0.--2. " EXTBUSDIV ,EXTBUT clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128" line.long 0x20 "APPCKDIVR2,APP Clock Divider Register 2" bitfld.long 0x20 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x20 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8" line.long 0x24 "APPCKDIVR3,APP Clock Divider Register 3" bitfld.long 0x24 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x28 "APPCKDIVR4,APP Clock Divider Register 4" bitfld.long 0x28 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x1AC++0x03 line.long 0x00 "APPCKDIVR5,APP Clock Divider Register 5" bitfld.long 0x00 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x1B0++0x03 line.long 0x00 "APPCKDIVR6,APP Clock Divider Register 6" bitfld.long 0x00 20.--23. " CD6B1DIV ,CD6B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD6B0DIV ,CD6B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD6A1DIV ,CD6A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD6A0DIV ,CD6A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD6DIV ,CD6 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x1B4++0x03 line.long 0x00 "APPCKDIVR7,APP Clock Divider Register 7" bitfld.long 0x00 20.--23. " CD7B1DIV ,CD7B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD7B0DIV ,CD7B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD7A1DIV ,CD7A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD7A0DIV ,CD7A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD7DIV ,CD7 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x1B8++0x03 line.long 0x00 "APPCKDIVR8,APP Clock Divider Register 8" bitfld.long 0x00 20.--23. " CD8B1DIV ,CD8B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD8B0DIV ,CD8B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD8A1DIV ,CD8A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD8A0DIV ,CD8A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD8DIV ,CD8 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x1BC++0x03 line.long 0x00 "APPCKDIVR9,APP Clock Divider Register 9" bitfld.long 0x00 20.--23. " CD9B1DIV ,CD9B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD9B0DIV ,CD9B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD9A1DIV ,CD9A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD9A0DIV ,CD9A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD9DIV ,CD9 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" tree.end tree "STS Profile Register Group" rgroup.long 0x200++0x2B line.long 0x00 "STSCKSELR0,STS Clock Selection Register 0" bitfld.long 0x00 28.--31. " HSSPICM ,HSSPI clock selection status bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x00 21. " LAPP1ACM ,LAPP1A clock selection status bit" "CD0,PPL0" bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PPL0" newline bitfld.long 0x00 17. " LAPP0ACM ,LAPP0ACM clock selection status bit" "CD0,PPL0" bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PPL0" bitfld.long 0x00 13. " LCP1ACM ,LCP1A clock selection status bit" "CD0,PPL0" bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PPL0" newline bitfld.long 0x00 9. " LCP0ACM ,LCP0A clock selection status bit" "CD0,PPL0" bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PPL0" bitfld.long 0x00 4.--6. " CD0CM ,Clock domain 0 clock selection status bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG0,,Clock fixed at L" bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG0,,Clock fixed at L" line.long 0x04 "STSCKSELR1,STS Clock Selection Register 1" bitfld.long 0x04 28.--31. " CD4CM ,Clock domain 4 clock selection status bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 24.--27. " CD4CSL ,Clock domain 4 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 20.--23. " CD3CM ,Clock domain 3 clock selection status bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 16.--19. " CD3CSL ,Clock domain 3 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" newline bitfld.long 0x04 12.--15. " CD2CM ,Clock domain 2 clock selection status bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 8.--11. " CD2CSL ,Clock domain 2 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 4.--7. " CD1CM ,Clock domain 1 clock selection status bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x04 0.--3. " CD1CSL ,Clock domain 1 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" line.long 0x08 "STSCKSELR2,STS Clock Selection Register 2" bitfld.long 0x08 12.--14. " TRCCM ,TRC clock selection status bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG0,PLL1,Clock fixed at L" bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG0,PLL1,Clock fixed at L" bitfld.long 0x08 4.--7. " CD5CM ,Clock domain 5 clock selection status bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" bitfld.long 0x08 0.--3. " CD5CSL ,Clock domain 5 clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Clock fixed at L" newline line.long 0x0C "STSCKER0,STS Clock Source Enable Register 0" bitfld.long 0x0C 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x0C 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled" line.long 0x10 "STSCKER1,STS Clock Source Enable Register 1" bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x10 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled" line.long 0x14 "STSCKER2,STS Source Enable Register 2" bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled" newline bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled" bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled" line.long 0x18 "STSCKDIVR0,STS Clock Divider Register 0" bitfld.long 0x18 24.--26. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x18 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8" newline bitfld.long 0x18 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8" bitfld.long 0x18 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x1C "STSCKDIVR1,STS Clock Divider Register 1" bitfld.long 0x1C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x1C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x1C 0.--2. " EXTBUSDIV ,EXTBUT clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128" line.long 0x20 "STSCKDIVR2,STS Clock Divider Register 2" bitfld.long 0x20 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x20 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x20 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8" line.long 0x24 "STSCKDIVR3,STS Clock Divider Register 3" bitfld.long 0x24 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x24 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" line.long 0x28 "STSCKDIVR4,STS Clock Divider Register 4" bitfld.long 0x28 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x22C++0x03 line.long 0x00 "STSCKDIVR5,STS Clock Divider Register 5" bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD1B0DIV ,CD1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x230++0x03 line.long 0x00 "STSCKDIVR6,STS Clock Divider Register 6" bitfld.long 0x00 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x234++0x03 line.long 0x00 "STSCKDIVR7,STS Clock Divider Register 7" bitfld.long 0x00 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x238++0x03 line.long 0x00 "STSCKDIVR8,STS Clock Divider Register 8" bitfld.long 0x00 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x23C++0x03 line.long 0x00 "STSCKDIVR9,STS Clock Divider Register 9" bitfld.long 0x00 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" newline bitfld.long 0x00 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" tree.end width 0x0B tree.end tree.end tree "CSV (Clock Supervisor)" base ad:0xB0600300 width 14. group.long 0x00++0x07 line.long 0x00 "CSVMOCFGR0,Main Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVMOCFGR1,Main Clock Supervisor Setting Register 1" bitfld.long 0x04 24. " REFCLKSEL ,Reference lock selection bits" "Slow,Fast" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain/Software,Domain" newline hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x08++0x07 line.long 0x00 "CSVSOCFGR0,Sub Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVSOCFGR1,Sub clock supervisor setting register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain/Software,Domain" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x10++0x07 line.long 0x00 "CSVPLL0CFGR0,PLL0 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVPLL0CFGR1,PLL0 clock supervisor setting register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Interrupt,Reset" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x18++0x07 line.long 0x00 "CSVPLL1CFGR0,PLL1 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVPLL1CFGR1,PLL1 clock supervisor setting register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Interrupt,Reset" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x20++0x07 line.long 0x00 "CSVPLL2CFGR0,PLL2 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVPLL2CFGR1,PLL2 clock supervisor setting register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Interrupt,Reset" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x28++0x07 line.long 0x00 "CSVPLL3CFGR0,PLL3 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVPLL3CFGR1,PLL3 clock supervisor setting register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Interrupt,Reset" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x30++0x07 line.long 0x00 "CSVSP0CFGR0,SSCG PLL0 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVSP0CFGR1,SSCG PLL0 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Interrupt,Reset" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x38++0x07 line.long 0x00 "CSVSP1CFGR0,SSCG PLL1 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVSP1CFGR1,SSCG PLL1 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Interrupt,Reset" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x40++0x07 line.long 0x00 "CSVSP2CFGR0,SSCG PLL2 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVSP2CFGR1,SSCG PLL2 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Interrupt,Reset" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x48++0x07 line.long 0x00 "CSVSP3CFGR0,SSCG PLL3 Clock Supervisor Setting Register 0" hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits" hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits" line.long 0x04 "CSVSP3CFGR1,SSCG PLL3 Clock Supervisor Setting Register 1" bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Interrupt,Reset" hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits" group.long 0x50++0x07 line.long 0x00 "CSVFCRCFGR,Fast CR Clock Supervisor Setting Register" bitfld.long 0x00 0.--2. " REFCLKDIV ,Reference clock division setting bits" "/4,/8,/16,/32,/64,/128,/128,/128" line.long 0x04 "CSVSCRCFGR,Slow CR Clock Supervisor Setting Register" bitfld.long 0x04 0.--2. " REFCLKDIV ,Reference clock division setting bits" "/4,/8,/16,/32,/64,/128,/128,/128" group.long 0x60++0x07 line.long 0x00 "CSVOUTER,Clock Supervisor Output Enable Register" bitfld.long 0x00 0. " OUTEN ,Clock supervisor output enable bit" "Disabled,Enabled" line.long 0x04 "CSVTESTR,Clock Supervisor Test Register" bitfld.long 0x04 25. " SCRCLKGATE ,SCR CR clock supervisor test bit" "Normal,Gating" bitfld.long 0x04 24. " FCRCLKGATE ,FCR CR clock supervisor test bit" "Normal,Gating" bitfld.long 0x04 19. " SP3CLKGATE ,SSCG PLL3 clock supervisor test bit" "Normal,Gating" newline bitfld.long 0x04 18. " SP2CLKGATE ,SSCG PLL2 clock supervisor test bit" "Normal,Gating" bitfld.long 0x04 17. " SP1CLKGATE ,SSCG PLL1 clock supervisor test bit" "Normal,Gating" bitfld.long 0x04 16. " SP0CLKGATE ,SSCG PLL0 clock supervisor test bit" "Normal,Gating" newline bitfld.long 0x04 11. " PLL3CLKGATE ,PLL3 clock supervisor test bit" "Normal,Gating" bitfld.long 0x04 10. " PLL2CLKGATE ,PLL2 clock supervisor test bit" "Normal,Gating" bitfld.long 0x04 9. " PLL1CLKGATE ,PLL1 clock supervisor test bit" "Normal,Gating" newline bitfld.long 0x04 8. " PLL0CLKGATE ,PLL0 clock supervisor test bit" "Normal,Gating" bitfld.long 0x04 3. " SO1CLKGATE ,Sub clock 1 supervisor test bit" "Normal,Gating" bitfld.long 0x04 2. " MO1CLKGATE ,Main clock 1 supervisor test bit" "Normal,Gating" newline bitfld.long 0x04 1. " SO0CLKGATE ,Sub clock 0 supervisor test bit" "Normal,Gating" bitfld.long 0x04 0. " MO0CLKGATE ,Main clock 0 supervisor test bit" "Normal,Gating" width 0x0B tree.end tree "SCT (Source Clock Timer)" base ad:0xB0600400 width 12. group.long 0x00++0x0B "High-speed CR Clock Timer Registers" line.long 0x00 "FCRCTTRGR,High-speed CR Clock Timer Trigger Register" bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stopped" bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change/Start" line.long 0x04 "FCRCTCNTR,High-speed CR Clock Timer Control Register" bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continued,Stopped" bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shot,Continuous" line.long 0x08 "FCRCTCPR,High-speed CR Clock Timer Compare Prescaler Register" bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits" rgroup.long 0x0C++0x03 line.long 0x00 "FCRCTSTR,High-speed CR Clock Timer Status Register" bitfld.long 0x00 2. " BUSY ,Setting update status bit" "Completed,In progress" bitfld.long 0x00 1. " TST ,Timer status bit" "Stopped,Operating" bitfld.long 0x00 0. " INTF ,Interrupt flag bit" "No interrupt,Interrupt" group.long 0x10++0x07 line.long 0x00 "FCRCTINTER,High-speed CR Clock Timer Interrupt Enable Register" bitfld.long 0x00 0. " INTE ,Interrupt enable bit" "Disabled,Enabled" line.long 0x04 "FCRCTICLR,High-speed CR Clock Timer Interrupt Clear Register" bitfld.long 0x04 0. " INTC ,Interrupt clear bit" "No effect,Cleared" base ad:0xB0600480 width 12. group.long 0x00++0x0B "Low-speed CR Clock Timer Register" line.long 0x00 "SCRCTTRGR,Low-speed CR Clock Timer Trigger Register" bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stopped" bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change/Start" line.long 0x04 "SCRCTCNTR,Low-Speed CR Clock Timer Control Register" bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continued,Stopped" bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shoot,Continuous" line.long 0x08 "SCRCTCPR,Low-speed CR Clock Timer Compare Prescaler Register" bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits" rgroup.long 0x0C++0x03 line.long 0x00 "SCRCTSTR,Low-speed CR Clock Timer Status Register" bitfld.long 0x00 2. " BUSY ,Setting update status bit" "Completed,In progress" bitfld.long 0x00 1. " TST ,Timer status bit" "Stopped,Operated" bitfld.long 0x00 0. " INTF ,Interrupt flag bit" "No interrupt,Interrupt" group.long 0x10++0x07 line.long 0x00 "SCRCTINTER,Low-Speed CR Clock Timer Interrupt" bitfld.long 0x00 0. " INTE ,Interrupt enable bit" "Disabled,Enabled" line.long 0x04 "SCRCTICLR,Low-Speed CR Clock Timer Interrupt Clear Register" bitfld.long 0x04 0. " INTC ,Interrupt clear bit" "No effect,Cleared" base ad:0xB0600500 width 11. group.long 0x00++0x0B "Main Clock Timer Register" line.long 0x00 "MOCTTRGR,Main Clock Timer Register" bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stopped" bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change/Start" line.long 0x04 "MOCTCNTR,Main Clock Timer Control Register" bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continued,Stopped" bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shoot,Continuous" line.long 0x08 "MOCTCPR,Main Clock Timer Compare Prescaler Register" bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits" rgroup.long 0x0C++0x03 line.long 0x00 "MOCTSTR,Main Clock Timer Status Register" bitfld.long 0x00 2. " BUSY ,Setting update status bit" "Completed,In progress" bitfld.long 0x00 1. " TST ,Timer status bit" "Stopped,Operating" bitfld.long 0x00 0. " INTF ,Interrupt flag bit" "No interrupt,Interrupt" group.long 0x10++0x07 line.long 0x00 "MOCTINTER,Main Clock Timer Interrupt Enable Register" bitfld.long 0x00 0. " INTE ,Interrupt enable bit" "Disabled,Enabled" line.long 0x04 "MOCTICLR,Main Clock Timer Interrupt Clear Register" bitfld.long 0x04 0. " INTC ,Interrupt clear bit" "No effect,Cleared" sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA") base ad:0xB0600580 width 11. group.long 0x00++0x0B "Sub Clock Timer Registers" line.long 0x00 "SOCTTRGR,Sub Clock Timer Trigger Register" bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Cleared" bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stopped" bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change/Start" line.long 0x04 "SOCTCNTR,Sub Clock Timer Control Register" bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continued,Stopped" bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shoot,Continuous" line.long 0x08 "SOCTCPR,Sub Clock Timer Compare Prescaler Register" bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits" rgroup.long 0x0C++0x03 line.long 0x00 "SOCTSTR,Sub Clock Timer Status Register" bitfld.long 0x00 2. " BUSY ,Setting update status bit" "Completed,In progress" bitfld.long 0x00 1. " TST ,Timer status bit" "Stopped,Operating" bitfld.long 0x00 0. " INTF ,Interrupt flag bit" "No interrupt,Interrupt" group.long 0x10++0x07 line.long 0x00 "SOCTINTER,Sub Clock Timer Interrupt Enable Register" bitfld.long 0x00 0. " INTE ,Interrupt enable bit" "Disabled,Enabled" line.long 0x04 "SOCTICLR,Sub Clock Timer Interrupt Clear Register" bitfld.long 0x04 0. " INTC ,Interrupt clear bit" "No effect,Cleared" endif width 0x0B tree.end tree "RTC (Real Time Clock)" base ad:0xB0618000 width 14. if ((per.l(ad:0xB0618000)&0x100)==0x00) group.long 0x00++0x03 line.long 0x00 "WTCR,Timer Control Register" bitfld.long 0x00 15. " UPCAL ,Update calibration period counter" "Completed,Update" bitfld.long 0x00 12.--14. " SCAL ,Scale calibrated value" "No change,*2,*4,*8,*16,?..." bitfld.long 0x00 11. " CCKSEL ,Clock select for calibration" "Sub,Slow CR" bitfld.long 0x00 10. " ENUP ,Enable/Disable calibration value update" "Disabled,Enabled" newline bitfld.long 0x00 9. " MTRG ,Manual trigger for calibration" "No,Yes" bitfld.long 0x00 8. " ACAL ,Automatic calibration" "Disabled,Enabled" bitfld.long 0x00 4.--5. " RCKSEL ,Clock select for RTC" "Main,Sub,Slow CR,?..." bitfld.long 0x00 3. " CSM ,Clock switching mode" "Precise,Immediate" newline bitfld.long 0x00 2. " UPDT ,Update" "Completed,Update" bitfld.long 0x00 1. " OE ,Output enable" "General purpose,Sub-Second counter" bitfld.long 0x00 0. " ST ,Start" "Stopped,Started" else group.long 0x00++0x03 line.long 0x00 "WTCR,Timer Control Register" bitfld.long 0x00 15. " UPCAL ,Update calibration period counter" "Completed,Update" bitfld.long 0x00 12.--14. " SCAL ,Scale calibrated value" "No change,*2,*4,*8,*16,?..." bitfld.long 0x00 11. " CCKSEL ,Clock select for calibration" "Sub,Slow CR" newline textfld " " bitfld.long 0x00 8. " ACAL ,Automatic calibration" "Disabled,Enabled" bitfld.long 0x00 4.--5. " RCKSEL ,Clock select for RTC" "Main,Sub,Slow CR,?..." bitfld.long 0x00 3. " CSM ,Clock switching mode" "Precise,Immediate" newline bitfld.long 0x00 2. " UPDT ,Update" "Completed,Update" bitfld.long 0x00 1. " OE ,Output enable" "General purpose,Sub-Second counter" bitfld.long 0x00 0. " ST ,Start" "Stopped,Started" endif group.long 0x04++0x03 line.long 0x00 "WTSR,Timer Status Register" rbitfld.long 0x00 8. " RUNC ,Run calibration" "Inactive,In progress" rbitfld.long 0x00 7. " CLK_STS ,Clock switching status" "Inactive,In progress" bitfld.long 0x00 1. " CSF ,Clock switched flag" "Not switched,Switched" rbitfld.long 0x00 0. " RUN ,RUN" "Inactive,Active" group.long 0x08++0x03 line.long 0x00 "WINS_SET/CLR,Interrupt Status Register Set/Clear" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CALD_SET/CLR ,Calibration done" "In Progress,Done" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CFD_SET/CLR ,Calibration failure detection" "No Failure,Failure" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DAY_SET/CLR ,Day flag" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " HOUR_SET/CLR ,Hour flag" "No interrupt,Interrupt" newline setclrfld.long 0x00 2. 0x04 2. 0x08 2. " MIN_SET/CLR ,Minute flag" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SEC_SET/CLR ,Second flag" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SUBSEC_SET/CLR ,Sub-second flag" "No interrupt,Interrupt" group.long 0x14++0x0B line.long 0x00 "WTBR,Sub-second Register" hexmask.long.tbyte 0x00 0.--23. 1. " WTBR ,Sub-second value" line.long 0x04 "WRT,Real Time Register" bitfld.long 0x04 16.--20. " WTHR ,Hour register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." bitfld.long 0x04 8.--13. " WTMR ,Minute register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..." bitfld.long 0x04 0.--5. " WTSR ,Second register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..." line.long 0x08 "RTR1,Real Time Clock Real Time Register 1" hexmask.long.word 0x08 0.--15. 1. " WTDR ,Date bits" rgroup.long 0x20++0x03 line.long 0x00 "CNTCAL,Calibration Clock Counter Register" hexmask.long.tbyte 0x00 0.--23. 1. " CNTCAL ,Calibration clock counter value" group.long 0x24++0x13 line.long 0x00 "CNTPCAL,Calibration Clock Period Counter Register" hexmask.long.word 0x00 0.--10. 1. " CNTPCAL ,Calibration clock period register" line.long 0x04 "DURMW,Calibration Duration Register" hexmask.long.tbyte 0x04 0.--23. 1. " DURMW ,Calibration duration value" line.long 0x08 "CALTRG,Calibration Trigger Register" hexmask.long.word 0x08 0.--11. 1. " CALTRG ,Calibration trigger counter value" line.long 0x0C "DEBUG,Debug Register" bitfld.long 0x0C 0. " DBGEN ,Debug enable" "Disabled,Enabled" line.long 0x10 "PWUTRGCR,Partial Wake Up Trigger Control Register" hexmask.long.tbyte 0x10 8.--25. 1. " C8MRL ,Reload value setting bit of 8ms counter" bitfld.long 0x10 4. " MD ,Reload value setting bit to 8ms counter" "Manual operation,Sub-second" bitfld.long 0x10 0.--2. " SEL ,Reload value setting bit to trigger counter" "8ms,16ms,24ms,32ms,40ms,48ms,56ms,64ms" rgroup.long 0x38++0x03 line.long 0x00 "PWUTRGSR,Partial Wake Up Trigger Status Register" bitfld.long 0x00 0. " BUSY ,Busy status" "Not busy,Busy" width 0x0B tree.end tree "CRC (CR Calibration)" base ad:0xB0688400 width 8. group.word 0x00++0x03 line.word 0x00 "CUCR1,Correction Unit Control Register 1" bitfld.word 0x00 4. " STRT ,Calibration start" "Aborted,Started" bitfld.word 0x00 1. " INT ,Calibration interrupt" "No interrupt,Interrupt" bitfld.word 0x00 0. " INTEN ,Calibration interrupt enable" "Disabled,Enabled" line.word 0x02 "CUTD1,CR Clock Timer Data Register 1" rgroup.long 0x04++0x03 line.long 0x00 "CUTR1,Main Oscillation Timer Data Register 1" hexmask.long.tbyte 0x00 0.--23. 1. " TDR ,Timer data" group.long 0x08++0x03 line.long 0x0 "CUCRC1,Correction Unit Control Clear Register 1" bitfld.long 0x00 1. " INTC ,Interrupt clear" "No effect,Clear" width 0x0B tree.end tree "BURIF (Backup Ram Interface)" base ad:0x0E800000 width 10. group.long 0x00++0x03 line.long 0x00 "UNLOCK,Unlock Register" rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked" bitfld.long 0x00 2. " TM_ESKPG ,ECC generation function disable status bit" "Not allowed,Allowed" bitfld.long 0x00 1. " TM_ESKPC ,ECC test function disable status bit" "Not allowed,Allowed" newline bitfld.long 0x00 0. " TM_EEACC ,ECC area access enable status bit" "Not allowed,Allowed" rgroup.word 0x08++0x01 line.word 0x00 "DEEAR,Double-bit ECC Error Address Register" hexmask.word 0x00 0.--14. 0x01 " ERR_ADDR ,Double-bit error occurrence address bits" rgroup.word 0x0A++0x01 line.word 0x00 "SEEAR,Single-bit ECC Error Address Register" hexmask.word 0x00 0.--14. 0x01 " ERR_ADDR ,Single-bit error occurrence address bits" if (((per.l(ad:0x0E800000+0x04))&0x100)==0x00) group.word 0x0C++0x01 line.word 0x00 "EFEAR,ECC Pseudo-error Generation Address Register" hexmask.word 0x00 0.--14. 0x01 " ERR_ADDR ,Single-bit error occurrence address bits" group.byte 0x0F++0x00 line.byte 0x00 "EECSR,ECC Error Control Register" bitfld.byte 0x00 3. " DEIE ,Double-bit-error-caused interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " DEI ,Double-bit error occurrence bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " SEIE ,Single-bit-error-caused interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not occurred,Occurred" group.tbyte 0x10++0x02 line.tbyte 0x00 "EFECR,ECC Pseudo-error Generation Control Register" bitfld.tbyte 0x00 16. " FERR ,Pseudo-error generation enable bit" "Disabled,Enabled" newline bitfld.tbyte 0x00 15. " EY[7] ,Pseudo-error generation byte [7:0] setting bit" "0,1" bitfld.tbyte 0x00 14. " [6] ,Pseudo-error generation byte [15:8] setting bit" "0,1" bitfld.tbyte 0x00 13. " [5] ,Pseudo-error generation byte [23:16] setting bit" "0,1" bitfld.tbyte 0x00 12. " [4] ,Pseudo-error generation byte [31:24] setting bit" "0,1" newline bitfld.tbyte 0x00 11. " [3] ,Pseudo-error generation byte [36:32] setting bit" "0,1" bitfld.tbyte 0x00 10. " [2] ,Pseudo-error generation byte [41:37] setting bit" "0,1" bitfld.tbyte 0x00 9. " [1] ,Pseudo-error generation byte [46:42] setting bit" "0,1" bitfld.tbyte 0x00 8. " [0] ,Pseudo-error generation byte [51:47] setting bit" "0,1" newline bitfld.tbyte 0x00 7. " EI[7] ,Pseudo-error generation bit setting bit 7" "0,1" bitfld.tbyte 0x00 6. " [6] ,Pseudo-error generation bit setting bit 6" "0,1" bitfld.tbyte 0x00 5. " [5] ,Pseudo-error generation bit setting bit 5" "0,1" bitfld.tbyte 0x00 4. " [4] ,Pseudo-error generation bit setting bit 4" "0,1" newline bitfld.tbyte 0x00 3. " [3] ,Pseudo-error generation bit setting bit 3" "0,1" bitfld.tbyte 0x00 2. " [2] ,Pseudo-error generation bit setting bit 2" "0,1" bitfld.tbyte 0x00 1. " [1] ,Pseudo-error generation bit setting bit 1" "0,1" bitfld.tbyte 0x00 0. " [0] ,Pseudo-error generation bit setting bit 0" "0,1" group.byte 0x13++0x01 line.byte 0x00 "EDPCR,ECC Data Path Control Register" bitfld.byte 0x00 2. " SKPG ,ECC generation function disable bit" "No,Yes" bitfld.byte 0x00 1. " SKPC ,ECC test function disable bit" "No,Yes" bitfld.byte 0x00 0. " EACC ,ECC area access enable bit" "Disabled,Enabled" line.byte 0x01 "ECCTKCCR,ECC Test Mode Key Code Control Register" bitfld.byte 0x01 6.--7. " KEY ,Key code control" "00,01,10,11" bitfld.byte 0x01 2. " TM_ESKPG ,ECC generation function skip enable bit" "Disabled,Enabled" bitfld.byte 0x01 1. " TM_ESKPC ,ECC test function skip enable bit" "Disabled,Enabled" newline bitfld.byte 0x01 0. " TM_EEACC ,ECC area access enable bit" "Data Area,ECC Area" else rgroup.word 0x0C++0x01 line.word 0x00 "EFEAR,ECC Pseudo-error Generation Address Register" hexmask.word 0x00 0.--14. 0x01 " ERR_ADDR ,Single-bit error occurrence address bits" rgroup.byte 0x0F++0x00 line.byte 0x00 "EECSR,ECC Error Control Register" bitfld.byte 0x00 3. " DEIE ,Double-bit-error-caused interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " DEI ,Double-bit error occurrence bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " SEIE ,Single-bit-error-caused interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not occurred,Occurred" rgroup.tbyte 0x10++0x02 line.tbyte 0x00 "EFECR,ECC Pseudo-error Generation Control Register" bitfld.tbyte 0x00 16. " FERR ,Pseudo-error generation enable bit" "Disabled,Enabled" newline bitfld.tbyte 0x00 15. " EY[7] ,Pseudo-error generation byte [7:0] setting bit" "0,1" bitfld.tbyte 0x00 14. " [6] ,Pseudo-error generation byte [15:8] setting bit" "0,1" bitfld.tbyte 0x00 13. " [5] ,Pseudo-error generation byte [23:16] setting bit" "0,1" bitfld.tbyte 0x00 12. " [4] ,Pseudo-error generation byte [31:24] setting bit" "0,1" newline bitfld.tbyte 0x00 11. " [3] ,Pseudo-error generation byte [36:32] setting bit" "0,1" bitfld.tbyte 0x00 10. " [2] ,Pseudo-error generation byte [41:37] setting bit" "0,1" bitfld.tbyte 0x00 9. " [1] ,Pseudo-error generation byte [46:42] setting bit" "0,1" bitfld.tbyte 0x00 8. " [0] ,Pseudo-error generation byte [51:47] setting bit" "0,1" newline bitfld.tbyte 0x00 7. " EI[7] ,Pseudo-error generation bit setting bit 7" "0,1" bitfld.tbyte 0x00 6. " [6] ,Pseudo-error generation bit setting bit 6" "0,1" bitfld.tbyte 0x00 5. " [5] ,Pseudo-error generation bit setting bit 5" "0,1" bitfld.tbyte 0x00 4. " [4] ,Pseudo-error generation bit setting bit 4" "0,1" newline bitfld.tbyte 0x00 3. " [3] ,Pseudo-error generation bit setting bit 3" "0,1" bitfld.tbyte 0x00 2. " [2] ,Pseudo-error generation bit setting bit 2" "0,1" bitfld.tbyte 0x00 1. " [1] ,Pseudo-error generation bit setting bit 1" "0,1" bitfld.tbyte 0x00 0. " [0] ,Pseudo-error generation bit setting bit 0" "0,1" rgroup.byte 0x13++0x01 line.byte 0x00 "EDPCR,ECC Data Path Control Register" bitfld.byte 0x00 2. " SKPG ,ECC generation function disable bit" "No,Yes" bitfld.byte 0x00 1. " SKPC ,ECC test function disable bit" "No,Yes" bitfld.byte 0x00 0. " EACC ,ECC area access enable bit" "Disabled,Enabled" line.byte 0x01 "ECCTKCCR,ECC Test Mode Key Code Control Register" bitfld.byte 0x01 6.--7. " KEY ,Key code control" "00,01,10,11" bitfld.byte 0x01 2. " TM_ESKPG ,ECC generation function skip enable bit" "Disabled,Enabled" bitfld.byte 0x01 1. " TM_ESKPC ,ECC test function skip enable bit" "Disabled,Enabled" newline bitfld.byte 0x01 0. " TM_EEACC ,ECC area access enable bit" "Data Area,ECC Area" endif if (((per.l(ad:0x0E800000+0x18))&0xE0000000)!=0x00) rgroup.long 0x18++0x03 line.long 0x00 "TEAR0,Test Error Address Register 0" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " [1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " [0] ,March diagnosis error" "No error,Error" newline hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address" else rgroup.long 0x18++0x03 line.long 0x00 "TEAR0,Test Error Address Register 0" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " [1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " [0] ,March diagnosis error" "No error,Error" endif if (((per.l(ad:0x0E800000+0x1C))&0xE0000000)!=0x00) rgroup.long 0x1C++0x03 line.long 0x00 "TEAR1,Test Error Address Register 1" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " [1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " [0] ,March diagnosis error" "No error,Error" newline hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address" else rgroup.long 0x1C++0x03 line.long 0x00 "TEAR1,Test Error Address Register 1" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " [1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " [0] ,March diagnosis error" "No error,Error" endif if (((per.l(ad:0x0E800000+0x20))&0xE0000000)!=0x00) rgroup.long 0x20++0x03 line.long 0x00 "TEAR2,Test Error Address Register 2" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " [1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " [0] ,March diagnosis error" "No error,Error" newline hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address" else rgroup.long 0x20++0x03 line.long 0x00 "TEAR2,Test Error Address Register 2" bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error" bitfld.long 0x00 30. " [1] ,Checker diagnosis error" "No error,Error" bitfld.long 0x00 29. " [0] ,March diagnosis error" "No error,Error" endif if (((per.l(ad:0x0E800000+0x04))&0x100)==0x00) group.word 0x24++0x05 line.word 0x00 "TASAR,Test Start Address Register" hexmask.word 0x00 0.--14. 0x01 " SADDR ,RAM diagnosis start address" line.word 0x02 "TAEAR,Test End Address Register" hexmask.word 0x02 0.--14. 0x01 " EADDR ,RAM diagnosis end address" line.word 0x04 "TTCR,Test Diagnosis Function Register" rbitfld.word 0x04 9. " TSTAT ,RAM diagnosis error detection" "No error,Error" rbitfld.word 0x04 8. " OVFLW ,RAM diagnosis error overflow" "3 Or Fewer,4 Or More" bitfld.word 0x04 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled" newline bitfld.word 0x04 6. " TEI ,Error occurrence during diagnosis" "No error,Error" bitfld.word 0x04 5. " TCIE ,Diagnosis end factor interrupt enable" "Disabled,Enabled" bitfld.word 0x04 4. " TCI ,Diagnosis end" "Not Completed,Completed" newline bitfld.word 0x04 3. " TTYP[2] ,Unique diagnosis not performed/performed" "Not performed,Performed" bitfld.word 0x04 2. " [1] ,Checker diagnosis not performed/performed" "Not Performed,Performed" bitfld.word 0x04 1. " [0] ,March diagnosis not performed/performed" "Not Performed,Performed" newline rbitfld.word 0x04 0. " TRUN ,RAM diagnosis operation status" "Not In Progress,In progress" group.byte 0x2A++0x00 line.byte 0x00 "TICR,Test Initialization Function Register" bitfld.byte 0x00 3. " ICIE ,RAM initialization end factor interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ICI ,RAM initialization end" "Not completed,Completed" bitfld.byte 0x00 1. " ITYP ,RAM initialization contents specification" "0's,1's" newline rbitfld.byte 0x00 0. " IRUN ,RAM initialization operation status" "Not In Progress,In Progress" group.byte 0x2F++0x00 line.byte 0x00 "TSRCR,Test Software Reset Generation Control Register" bitfld.byte 0x00 7. " SRST ,Software reset" "No reset,Reset" group.byte 0x2B++0x01 line.byte 0x00 "TFECR,Test Pseudo-error Control Register" bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ETYP[2] ,Pseudo-error generation processing specification (unique)" "No error,Error" bitfld.byte 0x00 1. " [1] ,Pseudo-error generation processing specification (checker)" "No error,Error" newline bitfld.byte 0x00 0. " [0] ,Pseudo-error generation processing specification (march)" "No error,Error" line.byte 0x01 "TKCCR,Test Key Code Control Register" bitfld.byte 0x01 6.--7. " KEY ,Key code control" "0,1,2,3" bitfld.byte 0x01 0.--1. " CODE ,Operation specification" "Termination,Initialization,Diagnosis,?..." group.long 0x30++0x03 line.long 0x00 "EVENTCLR,Event Clear Register" bitfld.long 0x00 26. " DEICLR ,Double-bit error occurrence clear bit" "No effect,Clear" bitfld.long 0x00 24. " SEICLR ,Single-bit error occurrence clear bit" "No effect,Clear" bitfld.long 0x00 18. " ICICLR ,RAM initialization end clear bit" "No effect,Clear" newline bitfld.long 0x00 6. " TEICLR ,Error occurrence during diagnosis" "No effect,Clear" bitfld.long 0x00 4. " TCICLR ,Diagnosis end" "No effect,Clear" else rgroup.word 0x24++0x05 line.word 0x00 "TASAR,Test Start Address Register" hexmask.word 0x00 0.--14. 0x01 " SADDR ,RAM diagnosis start address" line.word 0x02 "TAEAR,Test End Address Register" hexmask.word 0x02 0.--14. 0x01 " EADDR ,RAM diagnosis end address" line.word 0x04 "TTCR,Test Diagnosis Function Register" rbitfld.word 0x04 9. " TSTAT ,RAM diagnosis error detection" "No error,Error" rbitfld.word 0x04 8. " OVFLW ,RAM diagnosis error overflow" "3 Or Fewer,4 Or More" bitfld.word 0x04 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled" newline bitfld.word 0x04 6. " TEI ,Error occurrence during diagnosis" "No error,Error" bitfld.word 0x04 5. " TCIE ,Diagnosis end factor interrupt enable" "Disabled,Enabled" bitfld.word 0x04 4. " TCI ,Diagnosis end" "Not Completed,Completed" newline bitfld.word 0x04 3. " TTYP[2] ,Unique diagnosis not performed/performed" "Not performed,Performed" bitfld.word 0x04 2. " [1] ,Checker diagnosis not performed/performed" "Not Performed,Performed" bitfld.word 0x04 1. " [0] ,March diagnosis not performed/performed" "Not Performed,Performed" newline rbitfld.word 0x04 0. " TRUN ,RAM diagnosis operation status" "Not In Progress,In progress" rgroup.byte 0x2A++0x00 line.byte 0x00 "TICR,Test Initialization Function Register" bitfld.byte 0x00 3. " ICIE ,RAM initialization end factor interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ICI ,RAM initialization end" "Not completed,Completed" bitfld.byte 0x00 1. " ITYP ,RAM initialization contents specification" "0's,1's" newline rbitfld.byte 0x00 0. " IRUN ,RAM initialization operation status" "Not In Progress,In Progress" rgroup.byte 0x2F++0x00 line.byte 0x00 "TSRCR,Test Software Reset Generation Control Register" bitfld.byte 0x00 7. " SRST ,Software reset" "No reset,Reset" rgroup.byte 0x2B++0x01 line.byte 0x00 "TFECR,Test Pseudo-error Control Register" bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ETYP[2] ,Pseudo-error generation processing specification (unique)" "No error,Error" bitfld.byte 0x00 1. " [1] ,Pseudo-error generation processing specification (checker)" "No error,Error" newline bitfld.byte 0x00 0. " [0] ,Pseudo-error generation processing specification (march)" "No error,Error" line.byte 0x01 "TKCCR,Test Key Code Control Register" bitfld.byte 0x01 6.--7. " KEY ,Key code control" "0,1,2,3" bitfld.byte 0x01 0.--1. " CODE ,Operation specification" "Termination,Initialization,Diagnosis,?..." rgroup.long 0x30++0x03 line.long 0x00 "EVENTCLR,Event Clear Register" bitfld.long 0x00 26. " DEICLR ,Double-bit error occurrence clear bit" "No effect,Clear" bitfld.long 0x00 24. " SEICLR ,Single-bit error occurrence clear bit" "No effect,Clear" bitfld.long 0x00 18. " ICICLR ,RAM initialization end clear bit" "No effect,Clear" newline bitfld.long 0x00 6. " TEICLR ,Error occurrence during diagnosis" "No effect,Clear" bitfld.long 0x00 4. " TCICLR ,Diagnosis end" "No effect,Clear" endif width 0x0B tree.end tree "EXTINT (External Interrupt)" base ad:0xB0620000 width 14. group.long 0x00++0x03 line.long 0x00 "ENIR_SET/CLR,External Interrupt Enable Register" sif cpuis("S6J342*")||cpuis("S6J351*") setclrfld.long 0x00 31. 0x04 31. 0x08 31. " EN_[31] ,External interrupt enable bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,External interrupt enable bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,External interrupt enable bit 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,External interrupt enable bit 28" "Disabled,Enabled" newline setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,External interrupt enable bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,External interrupt enable bit 26" "Disabled,Enabled" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,External interrupt enable bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,External interrupt enable bit 24" "Disabled,Enabled" newline setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,External interrupt enable bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,External interrupt enable bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,External interrupt enable bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,External interrupt enable bit 20" "Disabled,Enabled" newline else setclrfld.long 0x00 23. 0x04 23. 0x08 23. " EN_[23] ,External interrupt enable bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,External interrupt enable bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,External interrupt enable bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,External interrupt enable bit 20" "Disabled,Enabled" newline endif setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,External interrupt enable bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,External interrupt enable bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,External interrupt enable bit 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,External interrupt enable bit 16" "Disabled,Enabled" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,External interrupt enable bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,External interrupt enable bit 14" "Disabled,Enabled" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,External interrupt enable bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,External interrupt enable bit 12" "Disabled,Enabled" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,External interrupt enable bit 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,External interrupt enable bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,External interrupt enable bit 09" "Disabled,Enabled" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,External interrupt enable bit 08" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,External interrupt enable bit 07" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,External interrupt enable bit 06" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,External interrupt enable bit 05" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,External interrupt enable bit 04" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,External interrupt enable bit 03" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,External interrupt enable bit 02" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,External interrupt enable bit 01" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,External interrupt enable bit 00" "Disabled,Enabled" rgroup.long 0x0C++0x03 line.long 0x00 "EIRR,External Factor Register" sif cpuis("S6J342*")||cpuis("S6J351*") bitfld.long 0x00 31. " ER_[31] ,External interrupt factor detection bit 31" "Not detected,Detected" bitfld.long 0x00 30. " [30] ,External interrupt factor detection bit 30" "Not detected,Detected" bitfld.long 0x00 29. " [29] ,External interrupt factor detection bit 29" "Not detected,Detected" bitfld.long 0x00 28. " [28] ,External interrupt factor detection bit 28" "Not detected,Detected" newline bitfld.long 0x00 27. " [27] ,External interrupt factor detection bit 27" "Not detected,Detected" bitfld.long 0x00 26. " [26] ,External interrupt factor detection bit 26" "Not detected,Detected" bitfld.long 0x00 25. " [25] ,External interrupt factor detection bit 25" "Not detected,Detected" bitfld.long 0x00 24. " [24] ,External interrupt factor detection bit 24" "Not detected,Detected" newline bitfld.long 0x00 23. " [23] ,External interrupt factor detection bit 23" "Not detected,Detected" bitfld.long 0x00 22. " [22] ,External interrupt factor detection bit 22" "Not detected,Detected" bitfld.long 0x00 21. " [21] ,External interrupt factor detection bit 21" "Not detected,Detected" bitfld.long 0x00 20. " [20] ,External interrupt factor detection bit 20" "Not detected,Detected" newline else bitfld.long 0x00 23. " ER_[23] ,External interrupt factor detection bit 23" "Not detected,Detected" bitfld.long 0x00 22. " [22] ,External interrupt factor detection bit 22" "Not detected,Detected" bitfld.long 0x00 21. " [21] ,External interrupt factor detection bit 21" "Not detected,Detected" bitfld.long 0x00 20. " [20] ,External interrupt factor detection bit 20" "Not detected,Detected" newline endif bitfld.long 0x00 19. " [19] ,External interrupt factor detection bit 19" "Not detected,Detected" bitfld.long 0x00 18. " [18] ,External interrupt factor detection bit 18" "Not detected,Detected" bitfld.long 0x00 17. " [17] ,External interrupt factor detection bit 17" "Not detected,Detected" bitfld.long 0x00 16. " [16] ,External interrupt factor detection bit 16" "Not detected,Detected" newline bitfld.long 0x00 15. " [15] ,External interrupt factor detection bit 15" "Not detected,Detected" bitfld.long 0x00 14. " [14] ,External interrupt factor detection bit 14" "Not detected,Detected" bitfld.long 0x00 13. " [13] ,External interrupt factor detection bit 13" "Not detected,Detected" bitfld.long 0x00 12. " [12] ,External interrupt factor detection bit 12" "Not detected,Detected" newline bitfld.long 0x00 11. " [11] ,External interrupt factor detection bit 11" "Not detected,Detected" bitfld.long 0x00 10. " [10] ,External interrupt factor detection bit 10" "Not detected,Detected" bitfld.long 0x00 9. " [9] ,External interrupt factor detection bit 09" "Not detected,Detected" bitfld.long 0x00 8. " [8] ,External interrupt factor detection bit 08" "Not detected,Detected" newline bitfld.long 0x00 7. " [7] ,External interrupt factor detection bit 07" "Not detected,Detected" bitfld.long 0x00 6. " [6] ,External interrupt factor detection bit 06" "Not detected,Detected" bitfld.long 0x00 5. " [5] ,External interrupt factor detection bit 05" "Not detected,Detected" bitfld.long 0x00 4. " [4] ,External interrupt factor detection bit 04" "Not detected,Detected" newline bitfld.long 0x00 3. " [3] ,External interrupt factor detection bit 03" "Not detected,Detected" bitfld.long 0x00 2. " [2] ,External interrupt factor detection bit 02" "Not detected,Detected" bitfld.long 0x00 1. " [1] ,External interrupt factor detection bit 01" "Not detected,Detected" bitfld.long 0x00 0. " [0] ,External interrupt factor detection bit 00" "Not detected,Detected" group.long 0x10++0x07 line.long 0x00 "EIRCR,External Interrupt Factor Clear Register" sif cpuis("S6J342*")||cpuis("S6J351*") bitfld.long 0x00 31. " ERC_[31] ,External interrupt factor clear bit 31" "Not detected,Detected" bitfld.long 0x00 30. " [30] ,External interrupt factor clear bit 30" "Not detected,Detected" bitfld.long 0x00 29. " [29] ,External interrupt factor clear bit 29" "Not detected,Detected" bitfld.long 0x00 28. " [28] ,External interrupt factor clear bit 28" "Not detected,Detected" newline bitfld.long 0x00 27. " [27] ,External interrupt factor clear bit 27" "Not detected,Detected" bitfld.long 0x00 26. " [26] ,External interrupt factor clear bit 26" "Not detected,Detected" bitfld.long 0x00 25. " [25] ,External interrupt factor clear bit 25" "Not detected,Detected" bitfld.long 0x00 24. " [24] ,External interrupt factor clear bit 24" "Not detected,Detected" newline bitfld.long 0x00 23. " [23] ,External interrupt factor clear bit 23" "Not detected,Detected" bitfld.long 0x00 22. " [22] ,External interrupt factor clear bit 22" "Not detected,Detected" bitfld.long 0x00 21. " [21] ,External interrupt factor clear bit 21" "Not detected,Detected" bitfld.long 0x00 20. " [20] ,External interrupt factor clear bit 20" "Not detected,Detected" newline else bitfld.long 0x00 23. " ERC_[23] ,External interrupt factor clear bit 23" "No effect,Clear" bitfld.long 0x00 22. " [22] ,External interrupt factor clear bit 22" "No effect,Clear" bitfld.long 0x00 21. " [21] ,External interrupt factor clear bit 21" "No effect,Clear" bitfld.long 0x00 20. " [20] ,External interrupt factor clear bit 20" "No effect,Clear" newline endif bitfld.long 0x00 19. " [19] ,External interrupt factor clear bit 19" "No effect,Clear" bitfld.long 0x00 18. " [18] ,External interrupt factor clear bit 18" "No effect,Clear" bitfld.long 0x00 17. " [17] ,External interrupt factor clear bit 17" "No effect,Clear" bitfld.long 0x00 16. " [16] ,External interrupt factor clear bit 16" "No effect,Clear" newline bitfld.long 0x00 15. " [15] ,External interrupt factor clear bit 15" "No effect,Clear" bitfld.long 0x00 14. " [14] ,External interrupt factor clear bit 14" "No effect,Clear" bitfld.long 0x00 13. " [13] ,External interrupt factor clear bit 13" "No effect,Clear" bitfld.long 0x00 12. " [12] ,External interrupt factor clear bit 12" "No effect,Clear" newline bitfld.long 0x00 11. " [11] ,External interrupt factor clear bit 11" "No effect,Clear" bitfld.long 0x00 10. " [10] ,External interrupt factor clear bit 10" "No effect,Clear" bitfld.long 0x00 9. " [9] ,External interrupt factor clear bit 09" "No effect,Clear" bitfld.long 0x00 8. " [8] ,External interrupt factor clear bit 08" "No effect,Clear" newline bitfld.long 0x00 7. " [7] ,External interrupt factor clear bit 07" "No effect,Clear" bitfld.long 0x00 6. " [6] ,External interrupt factor clear bit 06" "No effect,Clear" bitfld.long 0x00 5. " [5] ,External interrupt factor clear bit 05" "No effect,Clear" bitfld.long 0x00 4. " [4] ,External interrupt factor clear bit 04" "No effect,Clear" newline bitfld.long 0x00 3. " [3] ,External interrupt factor clear bit 03" "No effect,Clear" bitfld.long 0x00 2. " [2] ,External interrupt factor clear bit 02" "No effect,Clear" bitfld.long 0x00 1. " [1] ,External interrupt factor clear bit 01" "No effect,Clear" bitfld.long 0x00 0. " [0] ,External interrupt factor clear bit 00" "No effect,Clear" line.long 0x04 "NFER_SET/CLR,Noise Filter Enable Register" sif cpuis("S6J342*")||cpuis("S6J351*") setclrfld.long 0x04 31. 0x08 31. 0x0C 31. " NFE_[31] ,Noise filter enable bit 31" "Disabled,Enabled" setclrfld.long 0x04 30. 0x08 30. 0x0C 30. " [30] ,Noise filter enable bit 30" "Disabled,Enabled" setclrfld.long 0x04 29. 0x08 29. 0x0C 29. " [29] ,Noise filter enable bit 29" "Disabled,Enabled" setclrfld.long 0x04 28. 0x08 28. 0x0C 28. " [28] ,Noise filter enable bit 28" "Disabled,Enabled" newline setclrfld.long 0x04 27. 0x08 27. 0x0C 27. " [27] ,Noise filter enable bit 27" "Disabled,Enabled" setclrfld.long 0x04 26. 0x08 26. 0x0C 26. " [26] ,Noise filter enable bit 26" "Disabled,Enabled" setclrfld.long 0x04 25. 0x08 25. 0x0C 25. " [25] ,Noise filter enable bit 25" "Disabled,Enabled" setclrfld.long 0x04 24. 0x08 24. 0x0C 24. " [24] ,Noise filter enable bit 24" "Disabled,Enabled" newline setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " [23] ,Noise filter enable bit 23" "Disabled,Enabled" setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,Noise filter enable bit 22" "Disabled,Enabled" setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,Noise filter enable bit 21" "Disabled,Enabled" setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,Noise filter enable bit 20" "Disabled,Enabled" newline else setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " NFE_[23] ,Noise filter enable bit 23" "Disabled,Enabled" setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,Noise filter enable bit 22" "Disabled,Enabled" setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,Noise filter enable bit 21" "Disabled,Enabled" setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,Noise filter enable bit 20" "Disabled,Enabled" newline endif setclrfld.long 0x04 19. 0x08 19. 0x0C 19. " [19] ,Noise filter enable bit 19" "Disabled,Enabled" setclrfld.long 0x04 18. 0x08 18. 0x0C 18. " [18] ,Noise filter enable bit 18" "Disabled,Enabled" setclrfld.long 0x04 17. 0x08 17. 0x0C 17. " [17] ,Noise filter enable bit 17" "Disabled,Enabled" setclrfld.long 0x04 16. 0x08 16. 0x0C 16. " [16] ,Noise filter enable bit 16" "Disabled,Enabled" newline setclrfld.long 0x04 15. 0x08 15. 0x0C 15. " [15] ,Noise filter enable bit 15" "Disabled,Enabled" setclrfld.long 0x04 14. 0x08 14. 0x0C 14. " [14] ,Noise filter enable bit 14" "Disabled,Enabled" setclrfld.long 0x04 13. 0x08 13. 0x0C 13. " [13] ,Noise filter enable bit 13" "Disabled,Enabled" setclrfld.long 0x04 12. 0x08 12. 0x0C 12. " [12] ,Noise filter enable bit 12" "Disabled,Enabled" newline setclrfld.long 0x04 11. 0x08 11. 0x0C 11. " [11] ,Noise filter enable bit 11" "Disabled,Enabled" setclrfld.long 0x04 10. 0x08 10. 0x0C 10. " [10] ,Noise filter enable bit 10" "Disabled,Enabled" setclrfld.long 0x04 9. 0x08 09. 0x0C 09. " [9] ,Noise filter enable bit 09" "Disabled,Enabled" setclrfld.long 0x04 8. 0x08 08. 0x0C 08. " [8] ,Noise filter enable bit 08" "Disabled,Enabled" newline setclrfld.long 0x04 7. 0x08 07. 0x0C 07. " [7] ,Noise filter enable bit 07" "Disabled,Enabled" setclrfld.long 0x04 6. 0x08 06. 0x0C 06. " [6] ,Noise filter enable bit 06" "Disabled,Enabled" setclrfld.long 0x04 5. 0x08 05. 0x0C 05. " [5] ,Noise filter enable bit 05" "Disabled,Enabled" setclrfld.long 0x04 4. 0x08 04. 0x0C 04. " [4] ,Noise filter enable bit 04" "Disabled,Enabled" newline setclrfld.long 0x04 3. 0x08 03. 0x0C 03. " [3] ,Noise filter enable bit 03" "Disabled,Enabled" setclrfld.long 0x04 2. 0x08 02. 0x0C 02. " [2] ,Noise filter enable bit 02" "Disabled,Enabled" setclrfld.long 0x04 1. 0x08 01. 0x0C 01. " [1] ,Noise filter enable bit 01" "Disabled,Enabled" setclrfld.long 0x04 0. 0x08 00. 0x0C 00. " [0] ,Noise filter enable bit 00" "Disabled,Enabled" group.long 0x20++0x0B line.long 0x00 "ELVR0,External Interrupt Level Register" bitfld.long 0x00 28.--30. " LCBA[7] ,INT7 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 24.--26. " [6] ,INT6 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 20.--22. " [5] ,INT5 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 16.--18. " [4] ,INT4 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" newline bitfld.long 0x00 12.--14. " [3] ,INT3 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 8.--10. " [2] ,INT2 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 4.--6. " [1] ,INT1 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 0.--2. " [0] ,INT0 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" line.long 0x04 "ELVR1,External Interrupt Level Register" bitfld.long 0x04 28.--30. " LCBA[7] ,INT15 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 24.--26. " [6] ,INT14 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 20.--22. " [5] ,INT13 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 16.--18. " [4] ,INT12 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" newline bitfld.long 0x04 12.--14. " [3] ,INT11 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 8.--10. " [2] ,INT10 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 4.--6. " [1] ,INT9 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x04 0.--2. " [0] ,INT8 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" line.long 0x08 "ELVR2,External Interrupt Level Register" bitfld.long 0x08 28.--30. " LCBA[7] ,INT23 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 24.--26. " [6] ,INT22 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 20.--22. " [5] ,INT21 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 16.--18. " [4] ,INT20 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" newline bitfld.long 0x08 12.--14. " [3] ,INT19 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 8.--10. " [2] ,INT18 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 4.--6. " [1] ,INT17 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x08 0.--2. " [0] ,INT16 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" sif cpuis("S6J342*")||cpuis("S6J351*") group.long 0x2C++0x3 line.long 0x00 "ELVR3,External Interrupt Level Register" bitfld.long 0x00 28.--30. " LCBA[7] ,INT31 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 24.--26. " [6] ,INT30 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 20.--22. " [5] ,INT29 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 16.--18. " [4] ,INT28 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" newline bitfld.long 0x00 12.--14. " [3] ,INT27 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 8.--10. " [2] ,INT26 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 4.--6. " [1] ,INT25 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" bitfld.long 0x00 0.--2. " [0] ,INT24 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both" endif group.long 0x30++0x07 line.long 0x00 "NMIR,Non Maskable Interrupt Register" bitfld.long 0x00 8. " NMICLR ,Non maskable interrupt clear bit" ",Clear" rbitfld.long 0x00 0. " NMIINT ,Non maskable interrupt request detection bit" "Not detected,Detected" line.long 0x04 "DRER_SET/CLR,DMA Request Enable Register" sif cpuis("S6J342*")||cpuis("S6J351*") setclrfld.long 0x04 31. 0x08 31. 0x0C 31. " DRE_[31] ,DMA request enable bit 31" "Disabled,Enabled" setclrfld.long 0x04 30. 0x08 30. 0x0C 30. " [30] ,DMA request enable bit 30" "Disabled,Enabled" setclrfld.long 0x04 29. 0x08 29. 0x0C 29. " [29] ,DMA request enable bit 29" "Disabled,Enabled" setclrfld.long 0x04 28. 0x08 28. 0x0C 28. " [28] ,DMA request enable bit 28" "Disabled,Enabled" newline setclrfld.long 0x04 27. 0x08 27. 0x0C 27. " [27] ,DMA request enable bit 27" "Disabled,Enabled" setclrfld.long 0x04 26. 0x08 26. 0x0C 26. " [26] ,DMA request enable bit 26" "Disabled,Enabled" setclrfld.long 0x04 25. 0x08 25. 0x0C 25. " [25] ,DMA request enable bit 25" "Disabled,Enabled" setclrfld.long 0x04 24. 0x08 24. 0x0C 24. " [24] ,DMA request enable bit 24" "Disabled,Enabled" newline setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " [23] ,DMA request enable bit 23" "Disabled,Enabled" setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,DMA request enable bit 22" "Disabled,Enabled" setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,DMA request enable bit 21" "Disabled,Enabled" setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,DMA request enable bit 20" "Disabled,Enabled" newline else setclrfld.long 0x04 23. 0x08 23. 0x0C 23. " DRE_[23] ,DMA request enable bit 23" "Disabled,Enabled" setclrfld.long 0x04 22. 0x08 22. 0x0C 22. " [22] ,DMA request enable bit 22" "Disabled,Enabled" setclrfld.long 0x04 21. 0x08 21. 0x0C 21. " [21] ,DMA request enable bit 21" "Disabled,Enabled" setclrfld.long 0x04 20. 0x08 20. 0x0C 20. " [20] ,DMA request enable bit 20" "Disabled,Enabled" newline endif setclrfld.long 0x04 19. 0x08 19. 0x0C 19. " [19] ,DMA request enable bit 19" "Disabled,Enabled" setclrfld.long 0x04 18. 0x08 18. 0x0C 18. " [18] ,DMA request enable bit 18" "Disabled,Enabled" setclrfld.long 0x04 17. 0x08 17. 0x0C 17. " [17] ,DMA request enable bit 17" "Disabled,Enabled" setclrfld.long 0x04 16. 0x08 16. 0x0C 16. " [16] ,DMA request enable bit 16" "Disabled,Enabled" newline setclrfld.long 0x04 15. 0x08 15. 0x0C 15. " [15] ,DMA request enable bit 15" "Disabled,Enabled" setclrfld.long 0x04 14. 0x08 14. 0x0C 14. " [14] ,DMA request enable bit 14" "Disabled,Enabled" setclrfld.long 0x04 13. 0x08 13. 0x0C 13. " [13] ,DMA request enable bit 13" "Disabled,Enabled" setclrfld.long 0x04 12. 0x08 12. 0x0C 12. " [12] ,DMA request enable bit 12" "Disabled,Enabled" newline setclrfld.long 0x04 11. 0x08 11. 0x0C 11. " [11] ,DMA request enable bit 11" "Disabled,Enabled" setclrfld.long 0x04 10. 0x08 10. 0x0C 10. " [10] ,DMA request enable bit 10" "Disabled,Enabled" setclrfld.long 0x04 9. 0x08 09. 0x0C 09. " [9] ,DMA request enable bit 9" "Disabled,Enabled" setclrfld.long 0x04 8. 0x08 08. 0x0C 08. " [8] ,DMA request enable bit 8" "Disabled,Enabled" newline setclrfld.long 0x04 7. 0x08 07. 0x0C 07. " [7] ,DMA request enable bit 7" "Disabled,Enabled" setclrfld.long 0x04 6. 0x08 06. 0x0C 06. " [6] ,DMA request enable bit 6" "Disabled,Enabled" setclrfld.long 0x04 5. 0x08 05. 0x0C 05. " [5] ,DMA request enable bit 5" "Disabled,Enabled" setclrfld.long 0x04 4. 0x08 04. 0x0C 04. " [4] ,DMA request enable bit 4" "Disabled,Enabled" newline setclrfld.long 0x04 3. 0x08 03. 0x0C 03. " [3] ,DMA request enable bit 3" "Disabled,Enabled" setclrfld.long 0x04 2. 0x08 02. 0x0C 02. " [2] ,DMA request enable bit 2" "Disabled,Enabled" setclrfld.long 0x04 1. 0x08 01. 0x0C 01. " [1] ,DMA request enable bit 1" "Disabled,Enabled" setclrfld.long 0x04 0. 0x08 00. 0x0C 00. " [0] ,DMA request enable bit 0" "Disabled,Enabled" rgroup.long 0x40++0x03 line.long 0x00 "DRFR,DMA Request Flag Register" sif cpuis("S6J342*")||cpuis("S6J351*") bitfld.long 0x00 31. " DRF_[31] ,DMA request detection bit 31" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,DMA request detection bit 30" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,DMA request detection bit 29" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,DMA request detection bit 28" "Not requested,Requested" newline bitfld.long 0x00 27. " [27] ,DMA request detection bit 27" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,DMA request detection bit 26" "Not requested,Requested" bitfld.long 0x00 25. " [25] ,DMA request detection bit 25" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,DMA request detection bit 24" "Not requested,Requested" newline bitfld.long 0x00 23. " [23] ,DMA request detection bit 23" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,DMA request detection bit 22" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,DMA request detection bit 21" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,DMA request detection bit 20" "Not requested,Requested" newline else bitfld.long 0x00 23. " DRF_[23] ,DMA request detection bit 23" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,DMA request detection bit 22" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,DMA request detection bit 21" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,DMA request detection bit 20" "Not requested,Requested" newline endif bitfld.long 0x00 19. " [19] ,DMA request detection bit 19" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,DMA request detection bit 18" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,DMA request detection bit 17" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,DMA request detection bit 16" "Not requested,Requested" newline bitfld.long 0x00 15. " [15] ,DMA request detection bit 15" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,DMA request detection bit 14" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,DMA request detection bit 13" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,DMA request detection bit 12" "Not requested,Requested" newline bitfld.long 0x00 11. " [11] ,DMA request detection bit 11" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,DMA request detection bit 10" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,DMA request detection bit 09" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,DMA request detection bit 08" "Not requested,Requested" newline bitfld.long 0x00 7. " [7] ,DMA request detection bit 07" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,DMA request detection bit 06" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,DMA request detection bit 05" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,DMA request detection bit 04" "Not requested,Requested" newline bitfld.long 0x00 3. " [3] ,DMA request detection bit 03" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,DMA request detection bit 02" "Not requested,Requested" bitfld.long 0x00 1. " [1] ,DMA request detection bit 01" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,DMA request detection bit 00" "Not requested,Requested" width 0x0B tree.end tree "HWDT (Hardware Watchdog Timer)" base ad:0xB060C000 width 10. group.long 0x00++0x03 line.long 0x00 "PROT,Hardware Watchdog Protection Register" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Hardware Watchdog Counter Register" if ((per.l(ad:0xB060C000)&0xFFFFFFFF)==0xFFFFFFFF) group.long 0x0C++0x03 line.long 0x00 "RSTCAUSE,Hardware Watchdog Reset Factor Register" bitfld.long 0x00 4. " RSTCAUSE4 ,Reset factor bit 4" "No reset,Reset" bitfld.long 0x00 3. " RSTCAUSE3 ,Reset factor bit 3" "No reset,Reset" bitfld.long 0x00 2. " RSTCAUSE2 ,Reset factor bit 2" "No reset,Reset" newline bitfld.long 0x00 1. " RSTCAUSE1 ,Reset factor bit 1" "No reset,Reset" bitfld.long 0x00 0. " RSTCAUSE0 ,Reset factor bit 0" "No reset,Reset" else rgroup.long 0x0C++0x03 line.long 0x00 "RSTCAUSE,Hardware Watchdog Reset Factor Register" bitfld.long 0x00 4. " RSTCAUSE4 ,Reset factor bit 4" "No reset,Reset" bitfld.long 0x00 3. " RSTCAUSE3 ,Reset factor bit 3" "No reset,Reset" bitfld.long 0x00 2. " RSTCAUSE2 ,Reset factor bit 2" "No reset,Reset" newline bitfld.long 0x00 1. " RSTCAUSE1 ,Reset factor bit 1" "No reset,Reset" bitfld.long 0x00 0. " RSTCAUSE0 ,Reset factor bit 0" "No reset,Reset" endif sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*") wgroup.long 0x10++0x03 line.long 0x00 "TRG0,Hardware Watchdog Trigger 0" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0" wgroup.long 0x18++0x03 line.long 0x00 "TRG1,Hardware Watchdog Trigger 1" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1" else group.long 0x10++0x03 line.long 0x00 "TRG0,Hardware Watchdog Trigger 0" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0" group.long 0x18++0x03 line.long 0x00 "TRG1,Hardware Watchdog Trigger 1" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1" endif if ((per.l(ad:0xB060C000)&0xFFFFFFFF)==0xFFFFFFFF) group.long 0x20++0x03 line.long 0x00 "INT,Hardware Watchdog Interrupt" bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Generated" bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable bit" "Not generated,Generated" rbitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected" newline rbitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected" sif cpuis("S6J342*")||cpuis("S6J351C*") group.long 0x24++0x03 line.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register" bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Clear" bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear" else wgroup.long 0x24++0x03 line.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register" bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Clear" bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear" endif group.long 0x2C++0x17 line.long 0x00 "TRG0CFG,Hardware Watchdog Trigger 0 Configuration Register" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration bits" line.long 0x04 "TRG1CFG,Hardware watchdog trigger 1 configuration register" hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration bits" line.long 0x08 "RUNLLS,Hardware Watchdog Lower Limit RUN Setting Register" line.long 0x0C "RUNULS,Hardware Watchdog Upper Limit RUN Setting Register" line.long 0x10 "PSSLLS,Hardware Watchdog Lower Limit PSS Setting Register" line.long 0x14 "PSSULS,Hardware Watchdog Upper Limit PSS Setting Register" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*") wgroup.long 0x44++0x03 line.long 0x00 "RSTDLY,Hardware Watchdog Reset Delay Counter Register" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits" else group.long 0x44++0x03 line.long 0x00 "RSTDLY,Hardware Watchdog Reset Delay Counter Register" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits" endif sif (cpuis("S6J33*"))||cpuis("S6J342*")||cpuis("S6J351C*") if ((per.l(ad:0xB060C000+0x48)&0x02)==0x02) group.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,High-Speed,Low-Speed" newline rbitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" ",Enabled" rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" else group.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,High-Speed,Low-Speed" newline rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" endif else if ((per.l(ad:0xB060C000+0x48)&0x02)==0x02) group.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,Sub clock,Main clock" newline rbitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" "Disabled,Enabled" rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" else group.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,Sub Clock,Main Clock" newline rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" endif endif else rgroup.long 0x20++0x03 line.long 0x00 "INT,Hardware Watchdog Interrupt" bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Interrupt" bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable bit" "Not generated,Generated" bitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected" newline bitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") hgroup.long 0x24++0x03 hide.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register" else sif (cpuis("S6J33*")) wgroup.long 0x24++0x03 line.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register" bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Cleared" bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear" else rgroup.long 0x24++0x03 line.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register" bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Cleared" bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Cleared" endif endif rgroup.long 0x2C++0x17 line.long 0x00 "TRG0CFG,Hardware Watchdog Trigger 0 Configuration Register" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration bits" line.long 0x04 "TRG1CFG,Hardware Watchdog Trigger 1 Configuration Register" hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration bits" line.long 0x08 "RUNLLS,Hardware Watchdog Lower Limit RUN Setting Register" line.long 0x0C "RUNULS,Hardware Watchdog Upper Limit RUN Setting Register" line.long 0x10 "PSSLLS,Hardware Watchdog Lower Limit PSS Setting Register" line.long 0x14 "PSSULS,Hardware Watchdog Upper Limit PSS Setting Register" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") hgroup.long 0x44++0x03 hide.long 0x00 "RSTDLY,Hardware Watchdog Reset Delay Counter Register" else rgroup.long 0x44++0x03 line.long 0x00 "RSTDLY,Hardware Watchdog Reset Delay Counter Register" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits" endif sif (cpuis("S6J33*"))||cpuis("S6J342*")||cpuis("S6J351C*") if ((per.l(ad:0xB060C000+0x48)&0x02)==0x02) rgroup.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,High-Speed,Low-Speed" newline bitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" ",Enabled" bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" else rgroup.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,Sub clock,Main clock" newline bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" endif else if ((per.l(ad:0xB060C000+0x48)&0x02)==0x02) rgroup.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,Sub clock,Main clock" newline bitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" "Disabled,Enabled" bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" else rgroup.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,Sub clock,Main clock" newline bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" endif endif endif rgroup.long 0x4C++0x0F line.long 0x00 "RUNLLC,Hardware Watchdog Lower Limit RUN Current Register" line.long 0x04 "RUNULC,Hardware Watchdog Upper Limit RUN Current Register" line.long 0x08 "PSSLLC,Hardware Watchdog Lower Limit PSS Current Register" line.long 0x0C "PSSULC,Hardware Watchdog Upper Limit PSS Current Register" width 0x0B tree.end tree "SWDT (Software Watchdog Timer)" base ad:0xB0308000 width 10. group.long 0x00++0x03 line.long 0x00 "PROT,Software Watchdog Protection Register" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Software Watchdog Counter Register" if ((per.l(ad:0xB0308000)&0xFFFFFFFF)==0xFFFFFFFF) group.long 0x0C++0x03 line.long 0x00 "RSTCAUSE,Software Watchdog Reset Factor Register" bitfld.long 0x00 4. " RSTCAUSE_[4] ,Reset factor bit 4" "No reset,Reset" bitfld.long 0x00 3. " [3] ,Reset factor bit 3" "No reset,Reset" bitfld.long 0x00 2. " [2] ,Reset factor bit 2" "No reset,Reset" newline bitfld.long 0x00 1. " [1] ,Reset factor bit 1" "No reset,Reset" bitfld.long 0x00 0. " [0] ,Reset factor bit 0" "No reset,Reset" else rgroup.long 0x0C++0x03 line.long 0x00 "RSTCAUSE,Software Watchdog Reset Factor Register" bitfld.long 0x00 4. " RSTCAUSE_[4] ,Reset factor bit 4" "No reset,Reset" bitfld.long 0x00 3. " [3] ,Reset factor bit 3" "No reset,Reset" bitfld.long 0x00 2. " [2] ,Reset factor bit 2" "No reset,Reset" newline bitfld.long 0x00 1. " [1] ,Reset factor bit 1" "No reset,Reset" bitfld.long 0x00 0. " [0] ,Reset factor bit 0" "No reset,Reset" endif group.long 0x10++0x03 line.long 0x00 "TRG0,Software Watchdog Trigger 0" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0" group.long 0x18++0x03 line.long 0x00 "TRG1,Software Watchdog Trigger 1" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1" if ((per.l(ad:0xB0308000)&0xFFFFFFFF)==0xFFFFFFFF) group.long 0x20++0x03 line.long 0x00 "INT,Software Watchdog Interrupt" bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Generated" bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable bit" "Not generated,Generated" rbitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected" newline rbitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected" sif cpuis("S6J342*")||cpuis("S6J351C*") group.long 0x24++0x03 line.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register" bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Clear" bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear" else wgroup.long 0x24++0x03 line.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register" bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Clear" bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear" endif group.long 0x2C++0x17 line.long 0x00 "TRG0CFG,Software Watchdog Trigger 0 Configuration Register" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration bits" line.long 0x04 "TRG1CFG,Software watchdog trigger 1 Configuration Register" hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration bits" line.long 0x08 "RUNLLS,Software Watchdog Lower Limit RUN Setting Register" line.long 0x0C "RUNULS,Software watchdog Upper Limit RUN Setting Register" line.long 0x10 "PSSLLS,Software watchdog Lower Limit PSS Setting Register" line.long 0x14 "PSSULS,Software watchdog Upper Limit PSS Setting Register" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*") wgroup.long 0x44++0x03 line.long 0x00 "RSTDLY,Software Watchdog Reset Delay Counter Register" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits" else group.long 0x44++0x03 line.long 0x00 "RSTDLY,Software Watchdog Reset Delay Counter Register" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits" endif if ((per.l(ad:0xB0308000+0x48)&0x02)==0x02) group.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" sif cpuis("S6J312?HAA") bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,?..." newline else bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,Sub clock,Main clock" newline endif bitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" "Disabled,Enabled" bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" else group.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" sif cpuis("S6J312?HAA") bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,?..." newline else bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,Sub clock,Main clock" newline endif bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" endif else rgroup.long 0x20++0x03 line.long 0x00 "INT,Software Watchdog Interrupt" bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Interrupt" bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable bit" "Not generated,Generated" bitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected" newline bitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") hgroup.long 0x24++0x03 hide.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register" else sif (cpuis("S6J33*")) wgroup.long 0x24++0x03 line.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register" bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Cleared" bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear" else rgroup.long 0x24++0x03 line.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register" bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Cleared" bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Cleared" endif endif rgroup.long 0x2C++0x17 line.long 0x00 "TRG0CFG,Software Watchdog Trigger 0 Configuration Register" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration bits" line.long 0x04 "TRG1CFG,Software Watchdog Trigger 1 Configuration Register" hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration bits" line.long 0x08 "RUNLLS,Software Watchdog Lower Limit RUN Setting Register" line.long 0x0C "RUNULS,Software Watchdog Upper Limit RUN Setting Register" line.long 0x10 "PSSLLS,Software Watchdog Lower Limit PSS Setting Register" line.long 0x14 "PSSULS,Software Watchdog Upper Limit PSS Setting Register" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") hgroup.long 0x44++0x03 hide.long 0x00 "RSTDLY,Software watchdog reset delay counter register" else rgroup.long 0x44++0x03 line.long 0x00 "RSTDLY,Software watchdog reset delay counter register" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits" endif if ((per.l(ad:0xB0308000+0x48)&0x02)==0x02) rgroup.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" sif cpuis("S6J312?HAA") bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,?..." newline else bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,Sub clock,Main clock" newline endif bitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" "Disabled,Enabled" bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" else rgroup.long 0x48++0x03 line.long 0x00 "CFG,Hardware Watchdog Configuration Register" sif cpuis("S6J312?HAA") bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,?..." newline else bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked" bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,Sub clock,Main clock" newline endif bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled" endif endif rgroup.long 0x4C++0x0F line.long 0x00 "RUNLLC,Software Watchdog Lower Limit RUN Current Register" line.long 0x04 "RUNULC,Software Watchdog Upper Limit RUN Current Register" line.long 0x08 "PSSLLC,Software Watchdog Lower Limit PSS Current Register" line.long 0x0C "PSSULC,Software Watchdog Upper Limit PSS Current Register" width 0x0B tree.end tree "TCRAM" base ad:0x00000000 width 14. if ((per.l(ad:0x00000000)&0x100)==0x00) group.long 0x00++0x07 line.long 0x00 "TCMCFG0,Configuration Register 0" bitfld.long 0x00 24.--25. " DWAIT ,Number of data wait bits" "0,1,2,3" rbitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked" hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC data error insertion bits" line.long 0x04 "TCMCFG1,Configuration Register 1" else rgroup.long 0x00++0x07 line.long 0x00 "TCMCFG0,Configuration Register 0" bitfld.long 0x00 24.--25. " DWAIT ,Number of data wait bits" "0,1,2,3" bitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked" hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC data error insertion bits" line.long 0x04 "TCMCFG1,Configuration Register 1" endif group.long 0x08++0x03 line.long 0x00 "TCMUNLOCK,Unlock register" if ((per.l(ad:0x00000000)&0x100)==0x00) group.long 0x10++0x03 line.long 0x00 "ECCDEN,ECC Direct Access Enable Register" bitfld.long 0x00 23. " DEN ,Direct access enable" "Disabled,Enabled" newline hexmask.long.byte 0x00 16.--22. 1. " DENUNLOCK ,Direct access enable unlock" else rgroup.long 0x10++0x03 line.long 0x00 "ECCDEN,ECC Direct Access Enable Register" bitfld.long 0x00 23. " DEN ,Direct access enable" "Disabled,Enabled" newline hexmask.long.byte 0x00 16.--22. 1. " DENUNLOCK ,Direct access enable unlock" endif rgroup.long 0x14++0x0B line.long 0x00 "ECCDR_PARITY,ECC Direct Read Parity Register" hexmask.long.word 0x00 0.--13. 1. " ECCDR_PARITY ,Direct read parity data" line.long 0x04 "ECCDR_DATA0,ECC Direct Read Data Register 0" line.long 0x08 "ECCDR_DATA1,ECC Direct Read Data Register 1" if ((per.l(ad:0x00000000)&0x100)==0x00) group.long 0x24++0x03 line.long 0x00 "ECCDW,ECC Direct Write Register" bitfld.long 0x00 31. " DWEN ,Direct access enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " DWENUNLOCK ,Direct write access enable unlock" hexmask.long.word 0x00 0.--13. 1. " ECCDW_PARITY ,Direct write parity data" else rgroup.long 0x24++0x03 line.long 0x00 "ECCDW,ECC Direct Write Register" bitfld.long 0x00 31. " DWEN ,Direct access enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " DWENUNLOCK ,Direct write access enable unlock" hexmask.long.word 0x00 0.--13. 1. " ECCDW_PARITY ,Direct write parity data" endif if ((per.l(ad:0x00000000+0x30)&0xE0000000)!=0x00) rgroup.long 0x30++0x03 line.long 0x00 "TEAR0,Error Address Register 0" bitfld.long 0x00 29.--31. " TER ,Unique diagnosis error" "No error,March error,Checker error,,Unique error,?..." newline hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address" else rgroup.long 0x30++0x03 line.long 0x00 "TEAR0,Error Address Register 0" bitfld.long 0x00 29.--31. " TER ,Unique diagnosis error" "No error,March error,Checker error,,Unique error,?..." endif if ((per.l(ad:0x00000000+0x34)&0xE0000000)!=0x00) rgroup.long 0x34++0x03 line.long 0x00 "TEAR1,Error Address Register 1" bitfld.long 0x00 29.--31. " TER ,Unique diagnosis error" "No error,March error,Checker error,,Unique error,?..." newline hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address" else rgroup.long 0x34++0x03 line.long 0x00 "TEAR1,Error Address Register 1" bitfld.long 0x00 29.--31. " TER ,Unique diagnosis error" "No error,March error,Checker error,,Unique error,?..." endif if ((per.l(ad:0x00000000+0x38)&0xE0000000)!=0x00) rgroup.long 0x38++0x03 line.long 0x00 "TEAR2,Error Address Register 2" bitfld.long 0x00 29.--31. " TER ,Unique diagnosis error" "No error,March error,Checker error,,Unique error,?..." newline hexmask.long.word 0x00 0.--14. 0x01 " ERR_ADDR ,Error occurrence address" else rgroup.long 0x38++0x03 line.long 0x00 "TEAR2,Error Address Register 2" bitfld.long 0x00 29.--31. " TER ,Unique diagnosis error" "No error,March error,Checker error,,Unique error,?..." endif if ((per.l(ad:0x00000000)&0x100)==0x00) group.word 0x3C++0x03 line.word 0x00 "TAEAR,End Address Register" hexmask.word 0x00 0.--14. 0x01 " EADDR ,RAM diagnosis end address" line.word 0x02 "TASAR,Start Address Register" hexmask.word 0x02 0.--14. 0x01 " SADDR ,RAM diagnosis start address" group.byte 0x40++0x01 line.byte 0x00 "TFECR,Pseudo Error Generation Control Register" bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ETYP[2] ,Unique pseudo-error generation" "Not generated,Generated" bitfld.byte 0x00 1. " [1] ,Checker pseudo-error generation" "Not generated,Generated" newline bitfld.byte 0x00 0. " [0] ,March pseudo-error generation" "Not generated,Generated" line.byte 0x01 "TICR,Initialization Function Register" bitfld.byte 0x01 3. " ICIE ,RAM initialization end source interrupt enable" "Disabled,Enabled" rbitfld.byte 0x01 2. " ICI ,RAM initialization completion" "Not completed,Completed" bitfld.byte 0x01 1. " ITYP ,RAM initialization contents specification" "0,1" newline rbitfld.byte 0x01 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress" group.word 0x42++0x01 line.word 0x00 "TTCR,Diagnosis Function Register" rbitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error" rbitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or less,4 or more" bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled" newline rbitfld.word 0x00 6. " TEI ,Diagnosis-time error generation" "0,1" bitfld.word 0x00 5. " TCIE ,Diagnosis end source interrupt enable" "Disabled,Enabled" rbitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed" newline bitfld.word 0x00 3. " TTYP[2] ,Perform unique diagnosis" "Not performed,Performed" bitfld.word 0x00 2. " [1] ,Perform checked diagnosis" "Not performed,Performed" bitfld.word 0x00 1. " [0] ,Perform march diagnosis" "Not performed,Performed" newline rbitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress" group.byte 0x44++0x00 line.byte 0x00 "TSRCR,Soft Reset Generation Control Register" bitfld.byte 0x00 7. " SRST ,Software reset" "Not reset,Reset" group.byte 0x47++0x00 line.byte 0x00 "TKCCR,Key Code Control Register" bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11" bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forcibly terminate,Activate initialization,Activate diagnosis,?..." group.byte 0x45++0x00 line.byte 0x00 "TSCR,Status Clear Register" bitfld.byte 0x00 6. " TEIC ,Diagnosis-time error generation clear" "No effect,Clear" bitfld.byte 0x00 4. " TCIC ,Diagnosis end clear" "No effect,Clear" bitfld.byte 0x00 2. " ICIC ,Ram initialization end clear" "No effect,Clear" else rgroup.word 0x3C++0x03 line.word 0x00 "TAEAR,End Address Register" hexmask.word 0x00 0.--14. 0x01 " EADDR ,RAM diagnosis end address" line.word 0x02 "TASAR,Start Address Register" hexmask.word 0x02 0.--14. 0x01 " SADDR ,RAM diagnosis start address" rgroup.byte 0x40++0x01 line.byte 0x00 "TFECR,Pseudo Error Generation Control Register" bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled" bitfld.byte 0x00 2. " ETYP[2] ,March pseudo-error generation processing specification" "Not generated,Generated" bitfld.byte 0x00 1. " [1] ,Checker pseudo-error generation processing specification" "Not generated,Generated" newline bitfld.byte 0x00 0. " [0] ,Unique pseudo-error generation processing specification" "Not generated,Generated" line.byte 0x01 "TICR,Initialization Function Register" bitfld.byte 0x01 3. " ICIE ,RAM initialization end source interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " ICI ,RAM initialization completion" "Not completed,Completed" bitfld.byte 0x01 1. " ITYP ,RAM initialization contents specification" "0,1" newline bitfld.byte 0x01 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress" rgroup.word 0x42++0x01 line.word 0x00 "TTCR,Diagnosis Function Register" bitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error" bitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or less,4 or more" bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled" newline bitfld.word 0x00 6. " TEI ,Diagnosis-time error generation" "0,1" bitfld.word 0x00 5. " TCIE ,Diagnosis end source interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed" newline bitfld.word 0x00 3. " TTYP[2] ,Perform march diagnosis" "Not performed,Performed" bitfld.word 0x00 2. " [1] ,Perform checked diagnosis" "Not performed,Performed" bitfld.word 0x00 1. " [0] ,Perform unique diagnosis" "Not performed,Performed" newline bitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress" rgroup.byte 0x44++0x00 line.byte 0x00 "TSRCR,Soft Reset Generation Control Register" bitfld.byte 0x00 7. " SRST ,Software reset" "No reset,Reset" rgroup.byte 0x47++0x00 line.byte 0x00 "TKCCR,Key Code Control Register" bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11" bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forcibly terminate,Activate initialization,Activate diagnosis,?..." rgroup.byte 0x45++0x00 line.byte 0x00 "TSCR,Status Clear Register" bitfld.byte 0x00 6. " TEIC ,Diagnosis-time error generation clear" "No effect,Clear" bitfld.byte 0x00 4. " TCIC ,Diagnosis end clear" "No effect,Clear" bitfld.byte 0x00 2. " ICIC ,Ram initialization end clear" "No effect,Clear" endif width 0x0B tree.end tree "TCFLASH" base ad:0xB0411000 width 11. group.long 0x00++0x03 line.long 0x00 "FCPROTKEY,Configuration Protection Key Register" group.long 0x08++0x03 line.long 0x00 "FCFGR,Configuration Register" bitfld.long 0x00 6. " SWFRST ,Software reset" "No reset,Reset" bitfld.long 0x00 5. " TCMPR ,TCM priority enable" "AXI and TCM,TCM" bitfld.long 0x00 4. " WE ,Program enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " TCMSPEC ,TCM speculative access enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2 cycles,3 cycles" group.long 0x10++0x03 line.long 0x00 "FECCCTRL,ECC Control Register" bitfld.long 0x00 0. " ECCOFF ,ECC off" "Performed,Not performed" newline group.long 0x28++0x07 line.long 0x00 "FDATEIR_L,Data Bit Error Injection Register" bitfld.long 0x00 31. " FDATEIR[63] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 30. " [62] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 29. " [61] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 28. " [60] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 27. " [59] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 26. " [58] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 25. " [57] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 24. " [56] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 23. " [55] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 22. " [54] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 21. " [53] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 20. " [52] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 19. " [51] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 18. " [50] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 17. " [49] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 16. " [48] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 15. " [47] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 14. " [46] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 13. " [45] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 12. " [44] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 11. " [43] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 10. " [42] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 9. " [41] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 8. " [40] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 7. " [39] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 6. " [38] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 5. " [37] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 4. " [36] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x00 3. " [35] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 2. " [34] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 1. " [33] ,Data bit error injection point" "No error,Error" bitfld.long 0x00 0. " [32] ,Data bit error injection point" "No error,Error" line.long 0x04 "FDATEIR_H,Data Bit Error Injection Register" bitfld.long 0x04 31. " FDATEIR[31] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 30. " [30] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 29. " [29] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 28. " [28] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 27. " [27] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 26. " [26] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 25. " [25] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 24. " [24] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 23. " [23] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 22. " [22] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 21. " [21] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 20. " [20] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 19. " [19] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 18. " [18] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 17. " [17] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 16. " [16] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 15. " [15] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 14. " [14] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 13. " [13] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 12. " [12] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 11. " [11] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 10. " [10] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 9. " [9] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 8. " [8] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 7. " [7] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 6. " [6] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 5. " [5] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 4. " [4] ,Data bit error injection point" "No error,Error" newline bitfld.long 0x04 3. " [3] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 2. " [2] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 1. " [1] ,Data bit error injection point" "No error,Error" bitfld.long 0x04 0. " [0] ,Data bit error injection point" "No error,Error" group.long 0x1C++0x03 line.long 0x00 "FECCEIR,Bit Error Injection Register" bitfld.long 0x00 27. " LMASK[3] ,Error injection lane mask (0x18 to 0x1F)" "Error,No error" bitfld.long 0x00 26. " [2] ,Error injection lane mask (0x10 to 0x17)" "Error,No error" bitfld.long 0x00 25. " [1] ,Error injection lane mask (0x08 to 0x0F)" "Error,No error" bitfld.long 0x00 24. " [0] ,Error injection lane mask (0x00 to 0x07)" "Error,No error" newline bitfld.long 0x00 7. " FECCEIR[7] ,ECC bit injection point" "0,1" bitfld.long 0x00 6. " [6] ,ECC bit injection point" "0,1" bitfld.long 0x00 5. " [5] ,ECC bit injection point" "0,1" bitfld.long 0x00 4. " [4] ,ECC bit injection point" "0,1" newline bitfld.long 0x00 3. " [3] ,ECC bit injection point" "0,1" bitfld.long 0x00 2. " [2] ,ECC bit injection point" "0,1" bitfld.long 0x00 1. " [1] ,ECC bit injection point" "0,1" bitfld.long 0x00 0. " [0] ,ECC bit injection point" "0,1" group.long 0x20++0x03 line.long 0x00 "FICTRL,Interrupt Control Register" bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" "No effect,Clear" bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" "No effect,Clear" bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled" rgroup.long 0x38++0x03 line.long 0x00 "FSTAT,Status Register" bitfld.long 0x00 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt" bitfld.long 0x00 7. " CERS ,Chip erase status" "Not performed,Performed" newline bitfld.long 0x00 6. " PGMS ,Program status" "No programming,Programming" bitfld.long 0x00 5. " ESPS ,Erase suspend status" "Not suspended,Suspended" bitfld.long 0x00 4. " ERSEC ,Erase suspend sector status" "Not suspended,Suspended" newline bitfld.long 0x00 3. " SERS ,Sector erase status" "Not performed,Performed" bitfld.long 0x00 2. " READ ,Reading ready" "Not ready,Ready" bitfld.long 0x00 1. " HANG ,Hangup" "No,Yes" newline bitfld.long 0x00 0. " RDY ,Programming/erasing ready" "Performing,Completed" group.long 0x50++0x03 line.long 0x00 "FSECIR,Interrupt Register" rbitfld.long 0x00 16. " SECINT ,1-bit error correction interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " SECIC ,1-bit error correction interrupt clear" "No effect,Clear" newline bitfld.long 0x00 0. " SECIE ,1-bit error correction interrupt enable" "Disabled,Enabled" rgroup.long 0x54++0x03 line.long 0x00 "FECCEAR,ECC Error Address Register" hexmask.long 0x00 5.--31. 0x20 " FECCEAR_BASE ,Base error address" newline bitfld.long 0x00 3. " SELF[3] ,Single error lane flag bit 3 [255:192]" "No error,Error" bitfld.long 0x00 2. " [2] ,Single error lane flag bit 2 [191:128]" "No error,Error" bitfld.long 0x00 1. " [1] ,Single error lane flag bit 1 [127:64]" "No error,Error" newline bitfld.long 0x00 0. " [0] ,Single error lane flag bit 0 [63:0]" "No error,Error" rgroup.long 0x60++0x07 line.long 0x00 "FUIDR0,TCFLASH Unique ID ROM Register 0" line.long 0x04 "FUIDR1,TCFLASH Unique ID ROM Register 1" group.long 0x80++0x03 line.long 0x00 "FUCEDIR,Uncorrectable Error Detection Interrupt Register" rbitfld.long 0x00 16. " UCEDINT ,Uncorrectable error detection interrupt" "No error,Error" bitfld.long 0x00 8. " UCEDIC ,Uncorrectable error detection interrupt clear" "No effect,Clear" rgroup.long 0x84++0x03 line.long 0x00 "FUCEAR,Uncorrectable Error Address Register" hexmask.long 0x00 5.--31. 0x20 " UCEA_BASE ,Uncorrectable error address" newline bitfld.long 0x00 3. " UCELF[3] ,Uncorrectable error lane flag bit 3 [255:192]" "No error,Error" bitfld.long 0x00 2. " [2] ,Uncorrectable error lane flag bit 2 [191:128]" "No error,Error" bitfld.long 0x00 1. " [1] ,Uncorrectable error lane flag bit 1 [127:64]" "No error,Error" newline bitfld.long 0x00 0. " [0] ,Uncorrectable error lane flag bit 0 [63:0]" "No error,Error" rgroup.long 0x88++0x03 line.long 0x00 "SYNR,Syndrome Register" hexmask.long.byte 0x00 24.--31. 1. " SYN[3] ,Syndrome of FWORD256 [255:192]" hexmask.long.byte 0x00 17.--23. 1. " [2] ,Syndrome of FWORD256 [191:128]" hexmask.long.word 0x00 8.--16. 1. " [1] ,Syndrome of FWORD256 [127:64]" newline hexmask.long.byte 0x00 0.--7. 1. " [1] ,Syndrome of FWORD256 [127:64]" group.long 0x90++0x03 line.long 0x00 "BRCFG,Buffer Region Configuration Register" hexmask.long.word 0x00 16.--31. 1. " REGION_END_BUF ,TCM buffer word number of region end" hexmask.long.byte 0x00 8.--15. 1. " SSEC ,Starting bufferable sector number" hexmask.long.byte 0x00 0.--7. 1. " ESEC ,Ending bufferable sector number" group.long 0x98++0x03 line.long 0x00 "BRAT,Buffer Region Attribute Register" bitfld.long 0x00 16. " VCLR ,TCM buffer region international clear" "No effect,Clear" bitfld.long 0x00 8.--9. " AM ,Buffer policy for TCM buffer region" "Wait state,2 pieces,Locked,?..." bitfld.long 0x00 0. " RGEN ,TCM Buffer region enable" "Disabled,Enabled" newline width 26. if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x400+0x00)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register" group.long (0x400+0x04)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register" group.long (0x400+0x08)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register" group.long (0x400+0x0C)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register" group.long (0x400+0x10)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[128:159],TCM Buffer Register" group.long (0x400+0x14)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[160:191],TCM Buffer Register" group.long (0x400+0x18)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[192:223],TCM Buffer Register" group.long (0x400+0x1C)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[224:255],TCM Buffer Register" group.long (0x400+0x20)++0x03 line.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x400+0x24)++0x03 line.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x400+0x28)++0x03 line.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x400+0x00)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x400+0x04)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x400+0x08)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x400+0x0C)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x400+0x10)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x400+0x14)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x400+0x18)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x400+0x1C)++0x03 line.long 0x00 "TCMBUF0_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x400+0x20)++0x03 line.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x400+0x24)++0x03 line.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x400+0x28)++0x03 line.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x400+0x00)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x400+0x04)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x400+0x08)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x400+0x0C)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x400+0x10)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x400+0x14)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x400+0x18)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x400+0x1C)++0x03 hide.long 0x00 "TCMBUF0_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x400+0x20)++0x03 hide.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register" hgroup.long (0x400+0x24)++0x03 hide.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register" hgroup.long (0x400+0x28)++0x03 hide.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x440+0x00)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register" group.long (0x440+0x04)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register" group.long (0x440+0x08)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register" group.long (0x440+0x0C)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register" group.long (0x440+0x10)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[128:159],TCM Buffer Register" group.long (0x440+0x14)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[160:191],TCM Buffer Register" group.long (0x440+0x18)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[192:223],TCM Buffer Register" group.long (0x440+0x1C)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[224:255],TCM Buffer Register" group.long (0x440+0x20)++0x03 line.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x440+0x24)++0x03 line.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x440+0x28)++0x03 line.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x440+0x00)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x440+0x04)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x440+0x08)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x440+0x0C)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x440+0x10)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x440+0x14)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x440+0x18)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x440+0x1C)++0x03 line.long 0x00 "TCMBUF1_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x440+0x20)++0x03 line.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x440+0x24)++0x03 line.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x440+0x28)++0x03 line.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x440+0x00)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x440+0x04)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x440+0x08)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x440+0x0C)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x440+0x10)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x440+0x14)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x440+0x18)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x440+0x1C)++0x03 hide.long 0x00 "TCMBUF1_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x440+0x20)++0x03 hide.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register" hgroup.long (0x440+0x24)++0x03 hide.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register" hgroup.long (0x440+0x28)++0x03 hide.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x480+0x00)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register" group.long (0x480+0x04)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register" group.long (0x480+0x08)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register" group.long (0x480+0x0C)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register" group.long (0x480+0x10)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[128:159],TCM Buffer Register" group.long (0x480+0x14)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[160:191],TCM Buffer Register" group.long (0x480+0x18)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[192:223],TCM Buffer Register" group.long (0x480+0x1C)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[224:255],TCM Buffer Register" group.long (0x480+0x20)++0x03 line.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x480+0x24)++0x03 line.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x480+0x28)++0x03 line.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x480+0x00)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x480+0x04)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x480+0x08)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x480+0x0C)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x480+0x10)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x480+0x14)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x480+0x18)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x480+0x1C)++0x03 line.long 0x00 "TCMBUF2_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x480+0x20)++0x03 line.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x480+0x24)++0x03 line.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x480+0x28)++0x03 line.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x480+0x00)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x480+0x04)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x480+0x08)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x480+0x0C)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x480+0x10)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x480+0x14)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x480+0x18)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x480+0x1C)++0x03 hide.long 0x00 "TCMBUF2_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x480+0x20)++0x03 hide.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register" hgroup.long (0x480+0x24)++0x03 hide.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register" hgroup.long (0x480+0x28)++0x03 hide.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x4C0+0x00)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register" group.long (0x4C0+0x04)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register" group.long (0x4C0+0x08)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register" group.long (0x4C0+0x0C)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register" group.long (0x4C0+0x10)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[128:159],TCM Buffer Register" group.long (0x4C0+0x14)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[160:191],TCM Buffer Register" group.long (0x4C0+0x18)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[192:223],TCM Buffer Register" group.long (0x4C0+0x1C)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[224:255],TCM Buffer Register" group.long (0x4C0+0x20)++0x03 line.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x4C0+0x24)++0x03 line.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x4C0+0x28)++0x03 line.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x4C0+0x00)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x4C0+0x04)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x4C0+0x08)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x4C0+0x0C)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x4C0+0x10)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x4C0+0x14)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x4C0+0x18)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x4C0+0x1C)++0x03 line.long 0x00 "TCMBUF3_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x4C0+0x20)++0x03 line.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x4C0+0x24)++0x03 line.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x4C0+0x28)++0x03 line.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x4C0+0x00)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x4C0+0x04)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x4C0+0x08)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x4C0+0x0C)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x4C0+0x10)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x4C0+0x14)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x4C0+0x18)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x4C0+0x1C)++0x03 hide.long 0x00 "TCMBUF3_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x4C0+0x20)++0x03 hide.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register" hgroup.long (0x4C0+0x24)++0x03 hide.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register" hgroup.long (0x4C0+0x28)++0x03 hide.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x500+0x00)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register" group.long (0x500+0x04)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register" group.long (0x500+0x08)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register" group.long (0x500+0x0C)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register" group.long (0x500+0x10)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[128:159],TCM Buffer Register" group.long (0x500+0x14)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[160:191],TCM Buffer Register" group.long (0x500+0x18)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[192:223],TCM Buffer Register" group.long (0x500+0x1C)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[224:255],TCM Buffer Register" group.long (0x500+0x20)++0x03 line.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x500+0x24)++0x03 line.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x500+0x28)++0x03 line.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x500+0x00)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x500+0x04)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x500+0x08)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x500+0x0C)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x500+0x10)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x500+0x14)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x500+0x18)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x500+0x1C)++0x03 line.long 0x00 "TCMBUF4_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x500+0x20)++0x03 line.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x500+0x24)++0x03 line.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x500+0x28)++0x03 line.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x500+0x00)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x500+0x04)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x500+0x08)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x500+0x0C)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x500+0x10)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x500+0x14)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x500+0x18)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x500+0x1C)++0x03 hide.long 0x00 "TCMBUF4_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x500+0x20)++0x03 hide.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register" hgroup.long (0x500+0x24)++0x03 hide.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register" hgroup.long (0x500+0x28)++0x03 hide.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x540+0x00)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register" group.long (0x540+0x04)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register" group.long (0x540+0x08)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register" group.long (0x540+0x0C)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register" group.long (0x540+0x10)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[128:159],TCM Buffer Register" group.long (0x540+0x14)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[160:191],TCM Buffer Register" group.long (0x540+0x18)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[192:223],TCM Buffer Register" group.long (0x540+0x1C)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[224:255],TCM Buffer Register" group.long (0x540+0x20)++0x03 line.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x540+0x24)++0x03 line.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x540+0x28)++0x03 line.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x540+0x00)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x540+0x04)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x540+0x08)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x540+0x0C)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x540+0x10)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x540+0x14)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x540+0x18)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x540+0x1C)++0x03 line.long 0x00 "TCMBUF5_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x540+0x20)++0x03 line.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x540+0x24)++0x03 line.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x540+0x28)++0x03 line.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x540+0x00)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x540+0x04)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x540+0x08)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x540+0x0C)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x540+0x10)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x540+0x14)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x540+0x18)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x540+0x1C)++0x03 hide.long 0x00 "TCMBUF5_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x540+0x20)++0x03 hide.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register" hgroup.long (0x540+0x24)++0x03 hide.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register" hgroup.long (0x540+0x28)++0x03 hide.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x580+0x00)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register" group.long (0x580+0x04)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register" group.long (0x580+0x08)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register" group.long (0x580+0x0C)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register" group.long (0x580+0x10)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[128:159],TCM Buffer Register" group.long (0x580+0x14)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[160:191],TCM Buffer Register" group.long (0x580+0x18)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[192:223],TCM Buffer Register" group.long (0x580+0x1C)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[224:255],TCM Buffer Register" group.long (0x580+0x20)++0x03 line.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x580+0x24)++0x03 line.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x580+0x28)++0x03 line.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x580+0x00)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x580+0x04)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x580+0x08)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x580+0x0C)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x580+0x10)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x580+0x14)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x580+0x18)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x580+0x1C)++0x03 line.long 0x00 "TCMBUF6_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x580+0x20)++0x03 line.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x580+0x24)++0x03 line.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x580+0x28)++0x03 line.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x580+0x00)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x580+0x04)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x580+0x08)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x580+0x0C)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x580+0x10)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x580+0x14)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x580+0x18)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x580+0x1C)++0x03 hide.long 0x00 "TCMBUF6_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x580+0x20)++0x03 hide.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register" hgroup.long (0x580+0x24)++0x03 hide.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register" hgroup.long (0x580+0x28)++0x03 hide.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x5C0+0x00)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register" group.long (0x5C0+0x04)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register" group.long (0x5C0+0x08)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register" group.long (0x5C0+0x0C)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register" group.long (0x5C0+0x10)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[128:159],TCM Buffer Register" group.long (0x5C0+0x14)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[160:191],TCM Buffer Register" group.long (0x5C0+0x18)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[192:223],TCM Buffer Register" group.long (0x5C0+0x1C)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[224:255],TCM Buffer Register" group.long (0x5C0+0x20)++0x03 line.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x5C0+0x24)++0x03 line.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x5C0+0x28)++0x03 line.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x5C0+0x00)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x5C0+0x04)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x5C0+0x08)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x5C0+0x0C)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x5C0+0x10)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x5C0+0x14)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x5C0+0x18)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x5C0+0x1C)++0x03 line.long 0x00 "TCMBUF7_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x5C0+0x20)++0x03 line.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x5C0+0x24)++0x03 line.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x5C0+0x28)++0x03 line.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x5C0+0x00)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x5C0+0x04)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x5C0+0x08)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x5C0+0x0C)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x5C0+0x10)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x5C0+0x14)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x5C0+0x18)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x5C0+0x1C)++0x03 hide.long 0x00 "TCMBUF7_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x5C0+0x20)++0x03 hide.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register" hgroup.long (0x5C0+0x24)++0x03 hide.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register" hgroup.long (0x5C0+0x28)++0x03 hide.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x600+0x00)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register" group.long (0x600+0x04)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register" group.long (0x600+0x08)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register" group.long (0x600+0x0C)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register" group.long (0x600+0x10)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[128:159],TCM Buffer Register" group.long (0x600+0x14)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[160:191],TCM Buffer Register" group.long (0x600+0x18)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[192:223],TCM Buffer Register" group.long (0x600+0x1C)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[224:255],TCM Buffer Register" group.long (0x600+0x20)++0x03 line.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x600+0x24)++0x03 line.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x600+0x28)++0x03 line.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x600+0x00)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x600+0x04)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x600+0x08)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x600+0x0C)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x600+0x10)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x600+0x14)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x600+0x18)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x600+0x1C)++0x03 line.long 0x00 "TCMBUF8_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x600+0x20)++0x03 line.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x600+0x24)++0x03 line.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x600+0x28)++0x03 line.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x600+0x00)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x600+0x04)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x600+0x08)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x600+0x0C)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x600+0x10)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x600+0x14)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x600+0x18)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x600+0x1C)++0x03 hide.long 0x00 "TCMBUF8_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x600+0x20)++0x03 hide.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register" hgroup.long (0x600+0x24)++0x03 hide.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register" hgroup.long (0x600+0x28)++0x03 hide.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x640+0x00)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register" group.long (0x640+0x04)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register" group.long (0x640+0x08)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register" group.long (0x640+0x0C)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register" group.long (0x640+0x10)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[128:159],TCM Buffer Register" group.long (0x640+0x14)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[160:191],TCM Buffer Register" group.long (0x640+0x18)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[192:223],TCM Buffer Register" group.long (0x640+0x1C)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[224:255],TCM Buffer Register" group.long (0x640+0x20)++0x03 line.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x640+0x24)++0x03 line.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x640+0x28)++0x03 line.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x640+0x00)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x640+0x04)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x640+0x08)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x640+0x0C)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x640+0x10)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x640+0x14)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x640+0x18)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x640+0x1C)++0x03 line.long 0x00 "TCMBUF9_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x640+0x20)++0x03 line.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x640+0x24)++0x03 line.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x640+0x28)++0x03 line.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x640+0x00)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x640+0x04)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x640+0x08)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x640+0x0C)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x640+0x10)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x640+0x14)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x640+0x18)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x640+0x1C)++0x03 hide.long 0x00 "TCMBUF9_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x640+0x20)++0x03 hide.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register" hgroup.long (0x640+0x24)++0x03 hide.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register" hgroup.long (0x640+0x28)++0x03 hide.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x680+0x00)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register" group.long (0x680+0x04)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register" group.long (0x680+0x08)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register" group.long (0x680+0x0C)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register" group.long (0x680+0x10)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[128:159],TCM Buffer Register" group.long (0x680+0x14)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[160:191],TCM Buffer Register" group.long (0x680+0x18)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[192:223],TCM Buffer Register" group.long (0x680+0x1C)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[224:255],TCM Buffer Register" group.long (0x680+0x20)++0x03 line.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x680+0x24)++0x03 line.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x680+0x28)++0x03 line.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x680+0x00)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x680+0x04)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x680+0x08)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x680+0x0C)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x680+0x10)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x680+0x14)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x680+0x18)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x680+0x1C)++0x03 line.long 0x00 "TCMBUF10_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x680+0x20)++0x03 line.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x680+0x24)++0x03 line.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x680+0x28)++0x03 line.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x680+0x00)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x680+0x04)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x680+0x08)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x680+0x0C)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x680+0x10)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x680+0x14)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x680+0x18)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x680+0x1C)++0x03 hide.long 0x00 "TCMBUF10_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x680+0x20)++0x03 hide.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register" hgroup.long (0x680+0x24)++0x03 hide.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register" hgroup.long (0x680+0x28)++0x03 hide.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x6C0+0x00)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register" group.long (0x6C0+0x04)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register" group.long (0x6C0+0x08)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register" group.long (0x6C0+0x0C)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register" group.long (0x6C0+0x10)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[128:159],TCM Buffer Register" group.long (0x6C0+0x14)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[160:191],TCM Buffer Register" group.long (0x6C0+0x18)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[192:223],TCM Buffer Register" group.long (0x6C0+0x1C)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[224:255],TCM Buffer Register" group.long (0x6C0+0x20)++0x03 line.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x6C0+0x24)++0x03 line.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x6C0+0x28)++0x03 line.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x6C0+0x00)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x6C0+0x04)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x6C0+0x08)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x6C0+0x0C)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x6C0+0x10)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x6C0+0x14)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x6C0+0x18)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x6C0+0x1C)++0x03 line.long 0x00 "TCMBUF11_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x6C0+0x20)++0x03 line.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x6C0+0x24)++0x03 line.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x6C0+0x28)++0x03 line.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x6C0+0x00)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x6C0+0x04)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x6C0+0x08)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x6C0+0x0C)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x6C0+0x10)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x6C0+0x14)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x6C0+0x18)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x6C0+0x1C)++0x03 hide.long 0x00 "TCMBUF11_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x6C0+0x20)++0x03 hide.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register" hgroup.long (0x6C0+0x24)++0x03 hide.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register" hgroup.long (0x6C0+0x28)++0x03 hide.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x700+0x00)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register" group.long (0x700+0x04)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register" group.long (0x700+0x08)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register" group.long (0x700+0x0C)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register" group.long (0x700+0x10)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[128:159],TCM Buffer Register" group.long (0x700+0x14)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[160:191],TCM Buffer Register" group.long (0x700+0x18)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[192:223],TCM Buffer Register" group.long (0x700+0x1C)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[224:255],TCM Buffer Register" group.long (0x700+0x20)++0x03 line.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x700+0x24)++0x03 line.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x700+0x28)++0x03 line.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x700+0x00)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x700+0x04)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x700+0x08)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x700+0x0C)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x700+0x10)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x700+0x14)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x700+0x18)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x700+0x1C)++0x03 line.long 0x00 "TCMBUF12_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x700+0x20)++0x03 line.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x700+0x24)++0x03 line.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x700+0x28)++0x03 line.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x700+0x00)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x700+0x04)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x700+0x08)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x700+0x0C)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x700+0x10)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x700+0x14)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x700+0x18)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x700+0x1C)++0x03 hide.long 0x00 "TCMBUF12_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x700+0x20)++0x03 hide.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register" hgroup.long (0x700+0x24)++0x03 hide.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register" hgroup.long (0x700+0x28)++0x03 hide.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x740+0x00)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register" group.long (0x740+0x04)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register" group.long (0x740+0x08)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register" group.long (0x740+0x0C)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register" group.long (0x740+0x10)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[128:159],TCM Buffer Register" group.long (0x740+0x14)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[160:191],TCM Buffer Register" group.long (0x740+0x18)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[192:223],TCM Buffer Register" group.long (0x740+0x1C)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[224:255],TCM Buffer Register" group.long (0x740+0x20)++0x03 line.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x740+0x24)++0x03 line.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x740+0x28)++0x03 line.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x740+0x00)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x740+0x04)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x740+0x08)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x740+0x0C)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x740+0x10)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x740+0x14)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x740+0x18)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x740+0x1C)++0x03 line.long 0x00 "TCMBUF13_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x740+0x20)++0x03 line.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x740+0x24)++0x03 line.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x740+0x28)++0x03 line.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x740+0x00)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x740+0x04)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x740+0x08)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x740+0x0C)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x740+0x10)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x740+0x14)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x740+0x18)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x740+0x1C)++0x03 hide.long 0x00 "TCMBUF13_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x740+0x20)++0x03 hide.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register" hgroup.long (0x740+0x24)++0x03 hide.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register" hgroup.long (0x740+0x28)++0x03 hide.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x780+0x00)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register" group.long (0x780+0x04)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register" group.long (0x780+0x08)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register" group.long (0x780+0x0C)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register" group.long (0x780+0x10)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[128:159],TCM Buffer Register" group.long (0x780+0x14)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[160:191],TCM Buffer Register" group.long (0x780+0x18)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[192:223],TCM Buffer Register" group.long (0x780+0x1C)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[224:255],TCM Buffer Register" group.long (0x780+0x20)++0x03 line.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x780+0x24)++0x03 line.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x780+0x28)++0x03 line.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x780+0x00)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x780+0x04)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x780+0x08)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x780+0x0C)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x780+0x10)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x780+0x14)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x780+0x18)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x780+0x1C)++0x03 line.long 0x00 "TCMBUF14_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x780+0x20)++0x03 line.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x780+0x24)++0x03 line.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x780+0x28)++0x03 line.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x780+0x00)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x780+0x04)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x780+0x08)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x780+0x0C)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x780+0x10)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x780+0x14)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x780+0x18)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x780+0x1C)++0x03 hide.long 0x00 "TCMBUF14_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x780+0x20)++0x03 hide.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register" hgroup.long (0x780+0x24)++0x03 hide.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register" hgroup.long (0x780+0x28)++0x03 hide.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register" endif if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200) group.long (0x7C0+0x00)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register" group.long (0x7C0+0x04)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register" group.long (0x7C0+0x08)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register" group.long (0x7C0+0x0C)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register" group.long (0x7C0+0x10)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[128:159],TCM Buffer Register" group.long (0x7C0+0x14)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[160:191],TCM Buffer Register" group.long (0x7C0+0x18)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[192:223],TCM Buffer Register" group.long (0x7C0+0x1C)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[224:255],TCM Buffer Register" group.long (0x7C0+0x20)++0x03 line.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x01 " BUFADDL ,Buffer address lower bit" group.long (0x7C0+0x24)++0x03 line.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" group.long (0x7C0+0x28)++0x03 line.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register" elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00)) rgroup.long (0x7C0+0x00)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register" rgroup.long (0x7C0+0x04)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register" rgroup.long (0x7C0+0x08)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register" rgroup.long (0x7C0+0x0C)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register" rgroup.long (0x7C0+0x10)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[128:159],TCM Buffer Register" rgroup.long (0x7C0+0x14)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[160:191],TCM Buffer Register" rgroup.long (0x7C0+0x18)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[192:223],TCM Buffer Register" rgroup.long (0x7C0+0x1C)++0x03 line.long 0x00 "TCMBUF15_BUFDATA[224:255],TCM Buffer Register" rgroup.long (0x7C0+0x20)++0x03 line.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register" bitfld.long 0x00 23. " READ1 ,Read 1" ",1" hexmask.long.tbyte 0x00 5.--22. 0x20 " BUFADDH ,Buffer address upper bit" hexmask.long.byte 0x00 0.--4. 0x00 " BUFADDL ,Buffer address lower bit" rgroup.long (0x7C0+0x24)++0x03 line.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register" bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid" rgroup.long (0x7C0+0x28)++0x03 line.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register" else hgroup.long (0x7C0+0x00)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register" hgroup.long (0x7C0+0x04)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register" hgroup.long (0x7C0+0x08)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register" hgroup.long (0x7C0+0x0C)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register" hgroup.long (0x7C0+0x10)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[128:159],TCM Buffer Register" hgroup.long (0x7C0+0x14)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[160:191],TCM Buffer Register" hgroup.long (0x7C0+0x18)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[192:223],TCM Buffer Register" hgroup.long (0x7C0+0x1C)++0x03 hide.long 0x00 "TCMBUF15_BUFDATA[224:255],TCM Buffer Register" hgroup.long (0x7C0+0x20)++0x03 hide.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register" hgroup.long (0x7C0+0x24)++0x03 hide.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register" hgroup.long (0x7C0+0x28)++0x03 hide.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register" endif width 0x0B tree.end tree "WORKFLASH" base ad:0xB0412000 width 9. group.long 0x00++0x03 line.long 0x00 "CPR,Configuration Protection Key Register" group.long 0x08++0x03 line.long 0x00 "CR,Configuration Register" bitfld.long 0x00 16. " SWFRST ,Software reset" "No reset,Reset" bitfld.long 0x00 8. " WE ,Write enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FAWC ,Flash access wait control" "Disabled,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" group.long 0x10++0x03 line.long 0x00 "WCR,Write Command Sequencer Configuration Register" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" rgroup.long 0x14++0x03 line.long 0x00 "WSR,Write Command Sequencer Status Register" bitfld.long 0x00 0.--1. " ST ,Write command sequencer status" "Idle,Sending,Waiting,?..." group.long 0x78++0x03 line.long 0x00 "DBEIR,Data Bit Error Injection Register" bitfld.long 0x00 31. " DBEIR[31] ,Data bit error injection location bit 31" "Sent,Inverted" bitfld.long 0x00 30. " [30] ,Data bit error injection location bit 30" "Sent,Inverted" bitfld.long 0x00 29. " [29] ,Data bit error injection location bit 29" "Sent,Inverted" newline bitfld.long 0x00 28. " [28] ,Data bit error injection location bit 28" "Sent,Inverted" bitfld.long 0x00 27. " [27] ,Data bit error injection location bit 27" "Sent,Inverted" bitfld.long 0x00 26. " [26] ,Data bit error injection location bit 26" "Sent,Inverted" newline bitfld.long 0x00 25. " [25] ,Data bit error injection location bit 25" "Sent,Inverted" bitfld.long 0x00 24. " [24] ,Data bit error injection location bit 24" "Sent,Inverted" bitfld.long 0x00 23. " [23] ,Data bit error injection location bit 23" "Sent,Inverted" newline bitfld.long 0x00 22. " [22] ,Data bit error injection location bit 22" "Sent,Inverted" bitfld.long 0x00 21. " [21] ,Data bit error injection location bit 21" "Sent,Inverted" bitfld.long 0x00 20. " [20] ,Data bit error injection location bit 20" "Sent,Inverted" newline bitfld.long 0x00 19. " [19] ,Data bit error injection location bit 19" "Sent,Inverted" bitfld.long 0x00 18. " [18] ,Data bit error injection location bit 18" "Sent,Inverted" bitfld.long 0x00 17. " [17] ,Data bit error injection location bit 17" "Sent,Inverted" newline bitfld.long 0x00 16. " [16] ,Data bit error injection location bit 16" "Sent,Inverted" bitfld.long 0x00 15. " [15] ,Data bit error injection location bit 15" "Sent,Inverted" bitfld.long 0x00 14. " [14] ,Data bit error injection location bit 14" "Sent,Inverted" newline bitfld.long 0x00 13. " [13] ,Data bit error injection location bit 13" "Sent,Inverted" bitfld.long 0x00 12. " [12] ,Data bit error injection location bit 12" "Sent,Inverted" bitfld.long 0x00 11. " [11] ,Data bit error injection location bit 11" "Sent,Inverted" newline bitfld.long 0x00 10. " [10] ,Data bit error injection location bit 10" "Sent,Inverted" bitfld.long 0x00 9. " [9] ,Data bit error injection location bit 9" "Sent,Inverted" bitfld.long 0x00 8. " [8] ,Data bit error injection location bit 8" "Sent,Inverted" newline bitfld.long 0x00 7. " [7] ,Data bit error injection location bit 7" "Sent,Inverted" bitfld.long 0x00 6. " [6] ,Data bit error injection location bit 6" "Sent,Inverted" bitfld.long 0x00 5. " [5] ,Data bit error injection location bit 5" "Sent,Inverted" newline bitfld.long 0x00 4. " [4] ,Data bit error injection location bit 4" "Sent,Inverted" bitfld.long 0x00 3. " [3] ,Data bit error injection location bit 3" "Sent,Inverted" bitfld.long 0x00 2. " [2] ,Data bit error injection location bit 2" "Sent,Inverted" newline bitfld.long 0x00 1. " [1] ,Data bit error injection location bit 1" "Sent,Inverted" bitfld.long 0x00 0. " [0] ,Data bit error injection location bit 0" "Sent,Inverted" group.long 0x1C++0x03 line.long 0x00 "EEIR,ECC Bit Error Injection Register" bitfld.long 0x00 6. " EEIR[6] ,ECC bit error injection location bit 6" "Sent,Inverted" bitfld.long 0x00 5. " [5] ,ECC bit error injection location bit 5" "Sent,Inverted" bitfld.long 0x00 4. " [4] ,ECC bit error injection location bit 4" "Sent,Inverted" newline bitfld.long 0x00 3. " [3] ,ECC bit error injection location bit 3" "Sent,Inverted" bitfld.long 0x00 2. " [2] ,ECC bit error injection location bit 2" "Sent,Inverted" bitfld.long 0x00 1. " [1] ,ECC bit error injection location bit 1" "Sent,Inverted" newline bitfld.long 0x00 0. " [0] ,ECC bit error injection location bit 0" "Sent,Inverted" group.long 0x24++0x03 line.long 0x00 "ICR,Interrupt Control Register" bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" "No effect,Clear" bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" "No effect,Clear" bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " RDYIE ,Ready interrupt enable" "Disabled,Enabled" rgroup.long 0x28++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 12. " WERINT ,Write enable release interrupt" "No interrupt,Interrupt" bitfld.long 0x00 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " ESPS ,Erase suspend status" "Not suspended,Suspended" bitfld.long 0x00 3. " SERS ,Sector erase status" "Not erasing,Erasing" bitfld.long 0x00 0. " RDY ,Ready" "Not ready,Ready" group.long 0x2C++0x03 line.long 0x00 "SECIR,SEC Interrupt Register" hexmask.long.byte 0x00 24.--31. 1. " SYN ,Syndrome" rbitfld.long 0x00 16. " SECINT ,1-bit error correction interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " SECIC ,1-bit error correction interrupt clear" "No effect,Clear" newline bitfld.long 0x00 0. " SECIE ,1-bit error correction interrupt enable" "Disabled,Enabled" rgroup.long 0x30++0x03 line.long 0x00 "EEAR,ECC Error Address Register" group.long 0x38++0x03 line.long 0x00 "EMENR,Extra Mode Enable Register" bitfld.long 0x00 8. " AEE ,Read arbitration error enable" "Disabled,Enabled" bitfld.long 0x00 0. " EMEN ,Extra mode enable" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "SEQCM,Sequencer Command Register" hexmask.long.byte 0x00 16.--23. 1. " ERS ,Sector erase instruction" bitfld.long 0x00 0.--3. " OPC ,Command" "No operation,Read/Reset,Erase command,Suspend 1 command,,,,,,,,Suspend 2 command,?..." rgroup.long 0x58++0x03 line.long 0x00 "ARBERR,Arbitration Error Register" bitfld.long 0x00 0. " ARBERR ,Read arbitration error" "No error,Error" group.long 0x5C++0x03 line.long 0x00 "ARBCLR,Arbitration Error Clear Register" bitfld.long 0x00 0. " ARBCLR ,Read arbitration error clear" "No effect,Clear" rgroup.long 0x60++0x03 line.long 0x00 "BERR,Bus Error Response Status Register" bitfld.long 0x00 11. " ERSERR ,ERS writing violation" "Not detected,Detected" bitfld.long 0x00 10. " RORW ,Write access to a read-only register" "Not detected,Detected" bitfld.long 0x00 9. " NWTM ,Writing to mirror area 4" "Not detected,Detected" newline bitfld.long 0x00 8. " ACCIGN ,Command overrun" "Not detected,Detected" bitfld.long 0x00 7. " ECRWL ,Protection sequence violation" "Not detected,Detected" bitfld.long 0x00 6. " UNACC ,Unprivileged writing" "Not detected,Detected" newline bitfld.long 0x00 5. " RESA ,Reserved area access" "Not detected,Detected" bitfld.long 0x00 4. " RWE ,Write protected sector access error" "Not detected,Detected" bitfld.long 0x00 2. " SIZE ,Access size violation" "Not detected,Detected" newline bitfld.long 0x00 1. " CRWE ,Writing prohibition violation" "Not detected,Detected" bitfld.long 0x00 0. " DED ,Uncorrectable error detection" "Not detected,Detected" group.long 0x64++0x03 line.long 0x00 "BERRCLR,Bus Error Response Status Clear Register" bitfld.long 0x00 11. " ERSERRCLR ,ERSERR clear" "No effect,Clear" bitfld.long 0x00 10. " RORWCLR ,RORW clear" "No effect,Clear" bitfld.long 0x00 9. " NWTMCLR ,NWTM clear" "No effect,Clear" newline bitfld.long 0x00 8. " ACCIGNCLR ,ACCIGN clear" "No effect,Clear" bitfld.long 0x00 7. " ECRWLCLR ,ECRWL clear" "No effect,Clear" bitfld.long 0x00 6. " UNACCLR ,UNACC clear" "No effect,Clear" newline bitfld.long 0x00 5. " RESACLR ,RESA clear" "No effect,Clear" bitfld.long 0x00 4. " RWECLR ,RWE clear" "No effect,Clear" bitfld.long 0x00 2. " SIZECLR ,SIZE clear" "No effect,Clear" newline bitfld.long 0x00 1. " CRWECLR ,CRWE clear" "No effect,Clear" bitfld.long 0x00 0. " DEDCLR ,DED clear" "No effect,Clear" rgroup.long 0x6C++0x07 line.long 0x00 "UCESR,Uncorrectable Error Status Register" hexmask.long.byte 0x00 24.--30. 1. " SYN ,Syndrome" line.long 0x04 "UCEAR,Uncorrectable Error Address Register" group.long 0x68++0x03 line.long 0x00 "WARBR,Write Arbitration Register" rbitfld.long 0x00 24. " WERSTS ,Write enable release status" "Disabled,Enabled" rbitfld.long 0x00 16. " WERINT ,Write enable release interrupt" "Disabled,Enabled" bitfld.long 0x00 8. " WERINTCLR ,Write enable release interrupt clear" "No effect,Clear" newline bitfld.long 0x00 0. " WERINTE ,Write enable release interrupt" "Disabled,Enabled" width 0x0B tree.end tree "BHI (BOOTROM HARDWARE INTERFACE)" base ad:0xFFFEFC00 width 13. wgroup.long 0x358++0x03 line.long 0x00 "UNLOCK,EXCFG Lock Release Register" group.long 0x360++0x03 line.long 0x00 "CNFG,EXCFG Setting Register" bitfld.long 0x00 8. " SWAP ,Exception vector register swap" "No effect,Swap" rbitfld.long 0x00 0. " LST ,BootROM hardware interface lock status" "Unlocked,Locked" group.long 0x384++0x0F line.long 0x00 "UNDEFINACT,EXCFG Inactive Set - Undefined Instruction Vector Register" line.long 0x04 "SVCINACT,EXCFG Inactive Set - Supervisor Call Vector Register" line.long 0x08 "PABORTINACT,EXCFG Inactive Set - Prefetch Abort Vector Register" line.long 0x0C "DABORTINACT,EXCFG Inactive Set - Data Abort Vector Register" rgroup.long 0x3C4++0x0F line.long 0x00 "UNDEFACT,EXCFG Active Set - Undefined Instruction Vector Register" line.long 0x04 "SVCACT,EXCFG Active Set - Supervisor Call Vector Register" line.long 0x08 "PABORTACT,EXCFG Active Set - Prefetch Abort Vector Register" line.long 0x0C "DABORTACT,EXCFG Active Set - Data Abort Vector Register" width 0x0B tree.end tree.open "BSI (BOOTROM SOFTWARE INTERFACE)" tree "TCM" base ad:0xB0E01000 width 11. tree "SR" group.long 0x00++0x03 line.long 0x00 "MK_SER,Security Enable Marker" group.long 0x08++0x03 line.long 0x00 "MK_SSR,Security Scope Marker" group.long 0x10++0x03 line.long 0x00 "MK_CEER,Chip Erase Enable" group.long 0x18++0x03 line.long 0x00 "MK_SOER,Security Overwrite Enable Marker" group.long 0x20++0x03 line.long 0x00 "MK_SWPOER,Sector Write Permission Overwrite Enable Marker" group.long 0x28++0x03 line.long 0x00 "MK_CSWP0,Code Flash Sector Write Permissions Of The Small Sectors Marker 0" group.long 0x30++0x03 line.long 0x00 "MK_CSWP1,Code Flash Sector Write Permissions Of The Large Sectors Marker 1" group.long 0x34++0x03 line.long 0x00 "MK_CSWP2,Code Flash Sector Write Permissions Of The Large Sectors Marker 2" group.long 0x38++0x03 line.long 0x00 "MK_CSWP3,Code Flash Sector Write Permissions Of The Large Sectors Marker 3" group.long 0x3C++0x03 line.long 0x00 "MK_CSWP4,Code Flash Sector Write Permissions Of The Large Sectors Marker 4" group.long 0x40++0x03 line.long 0x00 "MK_CSWP5,Code Flash Sector Write Permissions Of The Large Sectors Marker 5" group.long 0x44++0x03 line.long 0x00 "MK_CSWP6,Code Flash Sector Write Permissions Of The Large Sectors Marker 6" group.long 0x48++0x03 line.long 0x00 "MK_CSWP7,Code Flash Sector Write Permissions Of The Large Sectors Marker 7" group.long 0x4C++0x03 line.long 0x00 "MK_CSWP8,Code Flash Sector Write Permissions Of The Large Sectors Marker 8" group.long 0x70++0x03 line.long 0x00 "MK_WSWP0,Work Flash Sector Write Permissions Marker 0" group.long 0x74++0x03 line.long 0x00 "MK_WSWP1,Work Flash Sector Write Permissions Marker 1" group.long 0x78++0x03 line.long 0x00 "MK_WSWP2,Work Flash Sector Write Permissions Marker 2" group.long 0x7C++0x03 line.long 0x00 "MK_WSWP3,Work Flash Sector Write Permissions Marker 3" tree.end width 7. tree "DDR" group.long 0x88++0x03 line.long 0x00 "DSEM,Debugger Connection Enable Marker" group.long 0x90++0x03 line.long 0x00 "DSKM0,Debugger Security Key Marker 0 (Bits 127:96)" group.long 0x98++0x03 line.long 0x00 "DSKM1,Debugger Security Key Marker 1 (Bits 95:64)" group.long 0xA0++0x03 line.long 0x00 "DSKM2,Debugger Security Key Marker 2 (Bits 63:32)" group.long 0xA8++0x03 line.long 0x00 "DSKM3,Debugger Security Key Marker 3 (Bits 31:0)" tree.end width 7. tree "BDR" group.long 0xC0++0x03 line.long 0x00 "SBMM,SHE Secure Boot Mode Marker" group.long 0xC8++0x03 line.long 0x00 "SBSM,SHE Secure Boot Size Marker" group.long 0xE0++0x03 line.long 0x00 "DWEM,Debugger Connection Wait Enable Marker" group.long 0xE8++0x03 line.long 0x00 "ABVM,Alternative Boot Vector Marker" group.long 0xF0++0x03 line.long 0x00 "ABVEM,Alternative Boot Vector Enable Marker" tree.end width 10. tree "WDR" group.long 0x100++0x03 line.long 0x00 "INTM,Hardware Watchdog Interrupt Configuration Marker" bitfld.long 0x00 17. " RSTENM ,Reset enable marker" "NMI,Reset" bitfld.long 0x00 16. " IRQENM ,Prior warning interrupt enable marker" "Disabled,Enabled" group.long 0x108++0x03 line.long 0x00 "TRG0CFGM,Hardware Watchdog Trigger 0 Configuration Marker" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFGM ,Watchdog trigger 0 configuration marker" group.long 0x110++0x03 line.long 0x00 "TRG1CFGM,Hardware Watchdog Trigger 1 Configuration Marker" hexmask.long.byte 0x00 0.--7. 1. " TRG1CFGM ,Hardware watchdog trigger 1 configuration marker" group.long 0x118++0x03 line.long 0x00 "RUNLLM,Hardware Watchdog Lower Limit RUN Setting Marker" group.long 0x120++0x03 line.long 0x00 "RUNULM,Hardware Watchdog Upper Limit RUN Setting Marker" group.long 0x128++0x03 line.long 0x00 "PSSLLM,Hardware Watchdog Lower Limit PSS Setting Marker" group.long 0x130++0x03 line.long 0x00 "PSSULM,Hardware Watchdog Upper Limit PSS Setting Marker" group.long 0x138++0x03 line.long 0x00 "RSTDLYM,Hardware Watchdog Reset Delay Counter Marker" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLYM ,Reset/NMI delay counter marker" group.long 0x140++0x03 line.long 0x00 "CFGM,Hardware Watchdog Configuration Marker" bitfld.long 0x00 16.--20. " OBSSELM ,Watchdog counter monitor bit output selection marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSELM ,Clock selection marker" "High-speed,Low-speed,High-speed,Low-speed" group.long 0x148++0x03 line.long 0x00 "CEM,Hardware Watchdog Configuration Enable Marker" tree.end width 0x0B tree.end tree "AXI" base ad:0xB1E01000 width 11. tree "SR" group.long 0x00++0x03 line.long 0x00 "MK_SER,Security Enable Marker" group.long 0x08++0x03 line.long 0x00 "MK_SSR,Security Scope Marker" group.long 0x10++0x03 line.long 0x00 "MK_CEER,Chip Erase Enable" group.long 0x18++0x03 line.long 0x00 "MK_SOER,Security Overwrite Enable Marker" group.long 0x20++0x03 line.long 0x00 "MK_SWPOER,Sector Write Permission Overwrite Enable Marker" group.long 0x28++0x03 line.long 0x00 "MK_CSWP0,Code Flash Sector Write Permissions Of The Small Sectors Marker 0" group.long 0x30++0x03 line.long 0x00 "MK_CSWP1,Code Flash Sector Write Permissions Of The Large Sectors Marker 1" group.long 0x34++0x03 line.long 0x00 "MK_CSWP2,Code Flash Sector Write Permissions Of The Large Sectors Marker 2" group.long 0x38++0x03 line.long 0x00 "MK_CSWP3,Code Flash Sector Write Permissions Of The Large Sectors Marker 3" group.long 0x3C++0x03 line.long 0x00 "MK_CSWP4,Code Flash Sector Write Permissions Of The Large Sectors Marker 4" group.long 0x40++0x03 line.long 0x00 "MK_CSWP5,Code Flash Sector Write Permissions Of The Large Sectors Marker 5" group.long 0x44++0x03 line.long 0x00 "MK_CSWP6,Code Flash Sector Write Permissions Of The Large Sectors Marker 6" group.long 0x48++0x03 line.long 0x00 "MK_CSWP7,Code Flash Sector Write Permissions Of The Large Sectors Marker 7" group.long 0x4C++0x03 line.long 0x00 "MK_CSWP8,Code Flash Sector Write Permissions Of The Large Sectors Marker 8" group.long 0x70++0x03 line.long 0x00 "MK_WSWP0,Work Flash Sector Write Permissions Marker 0" group.long 0x74++0x03 line.long 0x00 "MK_WSWP1,Work Flash Sector Write Permissions Marker 1" group.long 0x78++0x03 line.long 0x00 "MK_WSWP2,Work Flash Sector Write Permissions Marker 2" group.long 0x7C++0x03 line.long 0x00 "MK_WSWP3,Work Flash Sector Write Permissions Marker 3" tree.end width 7. tree "DDR" group.long 0x88++0x03 line.long 0x00 "DSEM,Debugger Connection Enable Marker" group.long 0x90++0x03 line.long 0x00 "DSKM0,Debugger Security Key Marker 0 (Bits 127:96)" group.long 0x98++0x03 line.long 0x00 "DSKM1,Debugger Security Key Marker 1 (Bits 95:64)" group.long 0xA0++0x03 line.long 0x00 "DSKM2,Debugger Security Key Marker 2 (Bits 63:32)" group.long 0xA8++0x03 line.long 0x00 "DSKM3,Debugger Security Key Marker 3 (Bits 31:0)" tree.end width 7. tree "BDR" group.long 0xC0++0x03 line.long 0x00 "SBMM,SHE Secure Boot Mode Marker" group.long 0xC8++0x03 line.long 0x00 "SBSM,SHE Secure Boot Size Marker" group.long 0xE0++0x03 line.long 0x00 "DWEM,Debugger Connection Wait Enable Marker" group.long 0xE8++0x03 line.long 0x00 "ABVM,Alternative Boot Vector Marker" group.long 0xF0++0x03 line.long 0x00 "ABVEM,Alternative Boot Vector Enable Marker" tree.end width 10. tree "WDR" group.long 0x100++0x03 line.long 0x00 "INTM,Hardware Watchdog Interrupt Configuration Marker" bitfld.long 0x00 17. " RSTENM ,Reset enable marker" "NMI,Reset" bitfld.long 0x00 16. " IRQENM ,Prior warning interrupt enable marker" "Disabled,Enabled" group.long 0x108++0x03 line.long 0x00 "TRG0CFGM,Hardware Watchdog Trigger 0 Configuration Marker" hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFGM ,Watchdog trigger 0 configuration marker" group.long 0x110++0x03 line.long 0x00 "TRG1CFGM,Hardware Watchdog Trigger 1 Configuration Marker" hexmask.long.byte 0x00 0.--7. 1. " TRG1CFGM ,Hardware watchdog trigger 1 configuration marker" group.long 0x118++0x03 line.long 0x00 "RUNLLM,Hardware Watchdog Lower Limit RUN Setting Marker" group.long 0x120++0x03 line.long 0x00 "RUNULM,Hardware Watchdog Upper Limit RUN Setting Marker" group.long 0x128++0x03 line.long 0x00 "PSSLLM,Hardware Watchdog Lower Limit PSS Setting Marker" group.long 0x130++0x03 line.long 0x00 "PSSULM,Hardware Watchdog Upper Limit PSS Setting Marker" group.long 0x138++0x03 line.long 0x00 "RSTDLYM,Hardware Watchdog Reset Delay Counter Marker" hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLYM ,Reset/NMI delay counter marker" group.long 0x140++0x03 line.long 0x00 "CFGM,Hardware Watchdog Configuration Marker" bitfld.long 0x00 16.--20. " OBSSELM ,Watchdog counter monitor bit output selection marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--9. " CLKSELM ,Clock selection marker" "High-speed,Low-speed,High-speed,Low-speed" group.long 0x148++0x03 line.long 0x00 "CEM,Hardware Watchdog Configuration Enable Marker" tree.end width 0x0B tree.end tree.end tree "INTC (INTERRUPT CONTROLER)" base ad:0xB0400000 width 8. rgroup.long 0x00++0x0F line.long 0x00 "NMIVAS,NMI Vector Address Status Register" line.long 0x04 "NMIST,NMI Status Register" bitfld.long 0x04 8.--11. " NMIPS ,NMI priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--5. " NMISN ,NMI channel number bits" "0,,,,4,5,6,7,8,,,,12,13,,15,,,18,,,,,,24,?..." line.long 0x08 "IRQVAS,IRQ Vector Address Status Register" line.long 0x0C "IRQST,IRQ Status Register" bitfld.long 0x0C 24. " NIRQ ,IRQ interrupt status bit" "No interrupt,Interrupt" bitfld.long 0x0C 16.--20. " IRQPS ,IRQ priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0C 0.--9. 1. " IRQSN ,IRQ channel number bits" width 9. tree "NMI Vector Address Registers" group.long 0x10++0x03 line.long 0x00 "NMIVA0,(NMIX Pin (Ext-IRC)) NMI Vector Address Bits" group.long 0x20++0x13 line.long 0x00 "NMIVA4,(LVDs IRQ) NMI Vector Address Bits" line.long 0x04 "NMIVA5,(CSV Profile) NMI Vector Address Bits" line.long 0x08 "NMIVA6,(HW-WDT) NMI Vector Address Bits" line.long 0x0C "NMIVA7,(SW-WDT) NMI Vector Address Bits" line.long 0x10 "NMIVA8,(IRC 2-bit ECC Error Detection) NMI Vector Address Bits" sif cpuis("S6J351*") group.long 0x34++0x03 line.long 0x00 "NMIVA9,(Expand PLL CSV(OR-ed Of All Factors)) NMI Vector Address Bits" endif group.long 0x40++0x07 line.long 0x00 "NMIVA12,(CAN-FD RAMs 2-bit ECC Error Detection) NMI Vector Address Bits" line.long 0x04 "NMIVA13,(DMAC MPU #0 Protection Violation) NMI Vector Address Bits" group.long 0x4C++0x03 line.long 0x00 "NMIVA15,(SHE MPU) NMI Vector Address Bits" group.long 0x58++0x03 line.long 0x00 "NMIVA18,(TPU Protection Violation) NMI Vector Address Bits" sif !cpuis("S6J351*") group.long 0x70++0x03 line.long 0x00 "NMIVA24,(Bus Diagnosis Error Detection) NMI Vector Address Bits" endif tree.end width 10. tree "IRQ Vector Address Registers" group.long 0x94++0x0B line.long 0x00 "IRQVA1,(System Control Status) IRQ Vector Address Bits" line.long 0x04 "IRQVA2,(HW-WDT Pre-warning) IRQ Vector Address Bits" line.long 0x08 "IRQVA3,(SW-WDT Pre-warning) IRQ Vector Address Bits" group.long 0xB0++0x03 line.long 0x00 "IRQVA8,(TCFLASH RDY/Hang Up/Single Bit Error) IRQ Vector Address Bits" group.long 0xB8++0x03 line.long 0x00 "IRQVA10,(Work FLASH Hang Up) IRQ Vector Address Bits" group.long 0xC8++0x0B line.long 0x00 "IRQVA14,(System SRAM Single Bit Error) IRQ Vector Address Bits" line.long 0x04 "IRQVA15,(CAN FD RAM(ch. 0 To 4/8) Single Bit Error) IRQ Vector Address Bits" line.long 0x08 "IRQVA16,(IRC Vector Address RAM Single Bit Error) IRQ Vector Address Bits" group.long 0xE0++0x03 line.long 0x00 "IRQVA20,(Work FLASH RDY/Write Enable Release/Single Bit Error) IRQ Vector Address Bits" group.long 0xF0++0x03 line.long 0x00 "IRQVA24,(External Interrupt Request ch.0/ch.16) IRQ Vector Address Bits" group.long 0xF4++0x03 line.long 0x00 "IRQVA25,(External Interrupt Request ch.1/ch.17) IRQ Vector Address Bits" group.long 0xF8++0x03 line.long 0x00 "IRQVA26,(External Interrupt Request ch.2/ch.18) IRQ Vector Address Bits" group.long 0xFC++0x03 line.long 0x00 "IRQVA27,(External Interrupt Request ch.3/ch.19) IRQ Vector Address Bits" group.long 0x100++0x03 line.long 0x00 "IRQVA28,(External Interrupt Request ch.4/ch.20) IRQ Vector Address Bits" group.long 0x104++0x03 line.long 0x00 "IRQVA29,(External Interrupt Request ch.5/ch.21) IRQ Vector Address Bits" group.long 0x108++0x03 line.long 0x00 "IRQVA30,(External Interrupt Request ch.6/ch.22) IRQ Vector Address Bits" group.long 0x10C++0x03 line.long 0x00 "IRQVA31,(External Interrupt Request ch.7/ch.23) IRQ Vector Address Bits" group.long 0x110++0x03 line.long 0x00 "IRQVA32,(External Interrupt Request ch.8/ch.24) IRQ Vector Address Bits" group.long 0x114++0x03 line.long 0x00 "IRQVA33,(External Interrupt Request ch.9/ch.25) IRQ Vector Address Bits" group.long 0x118++0x03 line.long 0x00 "IRQVA34,(External Interrupt Request ch.10/ch.26) IRQ Vector Address Bits" group.long 0x11C++0x03 line.long 0x00 "IRQVA35,(External Interrupt Request ch.11/ch.27) IRQ Vector Address Bits" group.long 0x120++0x03 line.long 0x00 "IRQVA36,(External Interrupt Request ch.12/ch.28) IRQ Vector Address Bits" group.long 0x124++0x03 line.long 0x00 "IRQVA37,(External Interrupt Request ch.13/ch.29) IRQ Vector Address Bits" group.long 0x128++0x03 line.long 0x00 "IRQVA38,(External Interrupt Request ch.14/ch.30) IRQ Vector Address Bits" group.long 0x12C++0x03 line.long 0x00 "IRQVA39,(External Interrupt Request ch.15/ch.31) IRQ Vector Address Bits" group.long 0x130++0x03 line.long 0x00 "IRQVA40,(CAN FD ch.0) IRQ Vector Address Bits" group.long 0x134++0x03 line.long 0x00 "IRQVA41,(CAN FD ch.1) IRQ Vector Address Bits" group.long 0x138++0x03 line.long 0x00 "IRQVA42,(CAN FD ch.2) IRQ Vector Address Bits" group.long 0x13C++0x03 line.long 0x00 "IRQVA43,(CAN FD ch.3) IRQ Vector Address Bits" sif !cpuis("S6J351*") group.long 0x140++0x03 line.long 0x00 "IRQVA44,(CAN FD ch.4) IRQ Vector Address Bits" endif sif !cpuis("S6J351*") group.long 0x144++0x03 line.long 0x00 "IRQVA45,(CAN FD ch.8) IRQ Vector Address Bits" endif group.long 0x148++0x03 line.long 0x00 "IRQVA46,(MFS RX ch.0) IRQ Vector Address Bits" group.long (0x148+0x04)++0x03 line.long 0x00 "IRQVA47,(MFS TX ch.0) IRQ Vector Address Bits" group.long 0x150++0x03 line.long 0x00 "IRQVA48,(MFS RX ch.1) IRQ Vector Address Bits" group.long (0x150+0x04)++0x03 line.long 0x00 "IRQVA49,(MFS TX ch.1) IRQ Vector Address Bits" group.long 0x158++0x03 line.long 0x00 "IRQVA50,(MFS RX ch.2) IRQ Vector Address Bits" group.long (0x158+0x04)++0x03 line.long 0x00 "IRQVA51,(MFS TX ch.2) IRQ Vector Address Bits" group.long 0x160++0x03 line.long 0x00 "IRQVA52,(MFS RX ch.3) IRQ Vector Address Bits" group.long (0x160+0x04)++0x03 line.long 0x00 "IRQVA53,(MFS TX ch.3) IRQ Vector Address Bits" group.long 0x168++0x03 line.long 0x00 "IRQVA54,(MFS RX ch.4) IRQ Vector Address Bits" group.long (0x168+0x04)++0x03 line.long 0x00 "IRQVA55,(MFS TX ch.4) IRQ Vector Address Bits" group.long 0x170++0x03 line.long 0x00 "IRQVA56,(MFS RX ch.5) IRQ Vector Address Bits" group.long (0x170+0x04)++0x03 line.long 0x00 "IRQVA57,(MFS TX ch.5) IRQ Vector Address Bits" group.long 0x178++0x03 line.long 0x00 "IRQVA58,(MFS RX ch.6) IRQ Vector Address Bits" group.long (0x178+0x04)++0x03 line.long 0x00 "IRQVA59,(MFS TX ch.6) IRQ Vector Address Bits" group.long 0x180++0x03 line.long 0x00 "IRQVA60,(MFS RX ch.7) IRQ Vector Address Bits" group.long (0x180+0x04)++0x03 line.long 0x00 "IRQVA61,(MFS TX ch.7) IRQ Vector Address Bits" group.long 0x188++0x03 line.long 0x00 "IRQVA62,(MFS RX ch.8) IRQ Vector Address Bits" group.long (0x188+0x04)++0x03 line.long 0x00 "IRQVA63,(MFS TX ch.8) IRQ Vector Address Bits" group.long 0x190++0x03 line.long 0x00 "IRQVA64,(MFS RX ch.9) IRQ Vector Address Bits" group.long (0x190+0x04)++0x03 line.long 0x00 "IRQVA65,(MFS TX ch.9) IRQ Vector Address Bits" group.long 0x198++0x03 line.long 0x00 "IRQVA66,(MFS RX ch.10) IRQ Vector Address Bits" group.long (0x198+0x04)++0x03 line.long 0x00 "IRQVA67,(MFS TX ch.10) IRQ Vector Address Bits" group.long 0x1A0++0x03 line.long 0x00 "IRQVA68,(MFS RX ch.11) IRQ Vector Address Bits" group.long (0x1A0+0x04)++0x03 line.long 0x00 "IRQVA69,(MFS TX ch.11) IRQ Vector Address Bits" sif !cpuis("S6J351*") group.long 0x1A8++0x03 line.long 0x00 "IRQVA70,(MFS RX ch.12) IRQ Vector Address Bits" endif sif !cpuis("S6J351*") group.long (0x1A8+0x04)++0x03 line.long 0x00 "IRQVA71,(MFS TX ch.12) IRQ Vector Address Bits" endif sif !cpuis("S6J351*") group.long 0x1B0++0x03 line.long 0x00 "IRQVA72,(MFS RX ch.13) IRQ Vector Address Bits" endif sif !cpuis("S6J351*") group.long (0x1B0+0x04)++0x03 line.long 0x00 "IRQVA73,(MFS TX ch.13) IRQ Vector Address Bits" endif group.long 0x1FC++0x07 line.long 0x00 "IRQVA91,(SHE Error) IRQ Vector Address Bits" line.long 0x04 "IRQVA92,(SHE) IRQ Vector Address Bits" sif cpuis("S6J351*") group.long 0x204++0x07 line.long 0x00 "IRQVA93,(DDR HSSPI RX) IRQ Vector Address Bits" line.long 0x04 "IRQVA94,(DDR HSSPI TX) IRQ Vector Address Bits" endif group.long 0x20C++0x03 line.long 0x00 "IRQVA95,(TCRAM Diag) IRQ Vector Address Bits" group.long 0x214++0x0F line.long 0x00 "IRQVA97,(Global Timer) IRQ Vector Address Bits" line.long 0x04 "IRQVA98,(RTC) IRQ Vector Address Bits" line.long 0x08 "IRQVA99,(CR Calibration) IRQ Vector Address Bits" line.long 0x0C "IRQVA100,(Base Timer ch.0/8/9/10/11) IRQ Vector Address Bits" group.long 0x224++0x03 line.long 0x00 "IRQVA101,(Base Timer ch.1) IRQ Vector Address Bits" group.long 0x228++0x03 line.long 0x00 "IRQVA102,(Base Timer ch.2) IRQ Vector Address Bits" group.long 0x22C++0x03 line.long 0x00 "IRQVA103,(Base Timer ch.3) IRQ Vector Address Bits" group.long 0x230++0x03 line.long 0x00 "IRQVA104,(Base Timer ch.4) IRQ Vector Address Bits" group.long 0x234++0x03 line.long 0x00 "IRQVA105,(Base Timer ch.5) IRQ Vector Address Bits" group.long 0x238++0x03 line.long 0x00 "IRQVA106,(Base Timer ch.6) IRQ Vector Address Bits" group.long 0x23C++0x03 line.long 0x00 "IRQVA107,(Base Timer ch.7) IRQ Vector Address Bits" group.long 0x240++0x03 line.long 0x00 "IRQVA108,(Base Timer ch.12/20/21/22/23) IRQ Vector Address Bits" group.long 0x244++0x03 line.long 0x00 "IRQVA109,(Base Timer ch.13) IRQ Vector Address Bits" group.long 0x248++0x03 line.long 0x00 "IRQVA110,(Base Timer ch.14) IRQ Vector Address Bits" group.long 0x24C++0x03 line.long 0x00 "IRQVA111,(Base Timer ch.15) IRQ Vector Address Bits" group.long 0x250++0x03 line.long 0x00 "IRQVA112,(Base Timer ch.16) IRQ Vector Address Bits" group.long 0x254++0x03 line.long 0x00 "IRQVA113,(Base Timer ch.17) IRQ Vector Address Bits" group.long 0x258++0x03 line.long 0x00 "IRQVA114,(Base Timer ch.18) IRQ Vector Address Bits" group.long 0x25C++0x03 line.long 0x00 "IRQVA115,(Base Timer ch.19) IRQ Vector Address Bits" group.long 0x260++0x03 line.long 0x00 "IRQVA116,(Base Timer ch.24/32/33/34/35) IRQ Vector Address Bits" group.long 0x264++0x03 line.long 0x00 "IRQVA117,(Base Timer ch.25) IRQ Vector Address Bits" group.long 0x268++0x03 line.long 0x00 "IRQVA118,(Base Timer ch.26) IRQ Vector Address Bits" group.long 0x26C++0x03 line.long 0x00 "IRQVA119,(Base Timer ch.27) IRQ Vector Address Bits" group.long 0x270++0x03 line.long 0x00 "IRQVA120,(Base Timer ch.28) IRQ Vector Address Bits" group.long 0x274++0x03 line.long 0x00 "IRQVA121,(Base Timer ch.29) IRQ Vector Address Bits" group.long 0x278++0x03 line.long 0x00 "IRQVA122,(Base Timer ch.30) IRQ Vector Address Bits" group.long 0x27C++0x03 line.long 0x00 "IRQVA123,(Base Timer ch.31) IRQ Vector Address Bits" sif !cpuis("S6J351*") group.long 0x280++0x03 line.long 0x00 "IRQVA124,(Base Timer ch.36/44/45/46/47) IRQ Vector Address Bits" group.long 0x284++0x03 line.long 0x00 "IRQVA125,(Base Timer ch.37) IRQ Vector Address Bits" group.long 0x288++0x03 line.long 0x00 "IRQVA126,(Base Timer ch.38) IRQ Vector Address Bits" group.long 0x28C++0x03 line.long 0x00 "IRQVA127,(Base Timer ch.39) IRQ Vector Address Bits" group.long 0x290++0x03 line.long 0x00 "IRQVA128,(Base Timer ch.40) IRQ Vector Address Bits" group.long 0x294++0x03 line.long 0x00 "IRQVA129,(Base Timer ch.41) IRQ Vector Address Bits" group.long 0x298++0x03 line.long 0x00 "IRQVA130,(Base Timer ch.42) IRQ Vector Address Bits" group.long 0x29C++0x03 line.long 0x00 "IRQVA131,(Base Timer ch.43) IRQ Vector Address Bits" group.long 0x2A0++0x03 line.long 0x00 "IRQVA132,(Base Timer ch.48/56/57/58/59) IRQ Vector Address Bits" group.long 0x2A4++0x03 line.long 0x00 "IRQVA133,(Base Timer ch.49) IRQ Vector Address Bits" group.long 0x2A8++0x03 line.long 0x00 "IRQVA134,(Base Timer ch.50) IRQ Vector Address Bits" group.long 0x2AC++0x03 line.long 0x00 "IRQVA135,(Base Timer ch.51) IRQ Vector Address Bits" group.long 0x2B0++0x03 line.long 0x00 "IRQVA136,(Base Timer ch.52) IRQ Vector Address Bits" group.long 0x2B4++0x03 line.long 0x00 "IRQVA137,(Base Timer ch.53) IRQ Vector Address Bits" group.long 0x2B8++0x03 line.long 0x00 "IRQVA138,(Base Timer ch.54) IRQ Vector Address Bits" group.long 0x2BC++0x03 line.long 0x00 "IRQVA139,(Base Timer ch.55) IRQ Vector Address Bits" group.long 0x2C0++0x03 line.long 0x00 "IRQVA140,(Base Timer ch.60) IRQ Vector Address Bits" group.long 0x2C4++0x03 line.long 0x00 "IRQVA141,(Base Timer ch.61) IRQ Vector Address Bits" group.long 0x2C8++0x03 line.long 0x00 "IRQVA142,(Base Timer ch.62) IRQ Vector Address Bits" group.long 0x2CC++0x03 line.long 0x00 "IRQVA143,(Base Timer ch.63) IRQ Vector Address Bits" endif group.long 0x2D0++0x03 line.long 0x00 "IRQVA144,(Reload Timer ch.0) IRQ Vector Address Bits" group.long 0x2D4++0x03 line.long 0x00 "IRQVA145,(Reload Timer ch.1) IRQ Vector Address Bits" group.long 0x2D8++0x03 line.long 0x00 "IRQVA146,(Reload Timer ch.2) IRQ Vector Address Bits" group.long 0x2DC++0x03 line.long 0x00 "IRQVA147,(Reload Timer ch.3) IRQ Vector Address Bits" group.long 0x2E0++0x03 line.long 0x00 "IRQVA148,(Reload Timer ch.16) IRQ Vector Address Bits" group.long 0x2E4++0x03 line.long 0x00 "IRQVA149,(Reload Timer ch.17) IRQ Vector Address Bits" group.long 0x2E8++0x03 line.long 0x00 "IRQVA150,(FRT ch.0) IRQ Vector Address Bits" group.long 0x2EC++0x03 line.long 0x00 "IRQVA151,(FRT ch.1) IRQ Vector Address Bits" group.long 0x2F0++0x03 line.long 0x00 "IRQVA152,(FRT ch.2) IRQ Vector Address Bits" group.long 0x2F4++0x03 line.long 0x00 "IRQVA153,(FRT ch.3) IRQ Vector Address Bits" group.long 0x2F8++0x03 line.long 0x00 "IRQVA154,(FRT ch.4) IRQ Vector Address Bits" group.long 0x300++0x0B line.long 0x00 "IRQVA156,(FRT ch.8) IRQ Vector Address Bits" line.long 0x04 "IRQVA157,(FRT ch.9) IRQ Vector Address Bits" line.long 0x08 "IRQVA158,(FRT ch.10) IRQ Vector Address Bits" group.long 0x318++0x3B line.long 0x00 "IRQVA162,IRQ0 Of Input Capture 0 (ch.0) IRQ Vector Address Bits" line.long 0x04 "IRQVA163,IRQ0 Of Input Capture 1 (ch.2) IRQ Vector Address Bits" line.long 0x08 "IRQVA164,IRQ0 Of Input Capture 2 (ch.4) IRQ Vector Address Bits" line.long 0x0C "IRQVA165,IRQ0 Of Input Capture 8 (ch.16) IRQ Vector Address Bits" line.long 0x10 "IRQVA166,IRQ0 Of Input Capture 9 (ch.18) IRQ Vector Address Bits" line.long 0x14 "IRQVA167,IRQ0 Of Input Capture 10 (ch.20) IRQ Vector Address Bits" line.long 0x18 "IRQVA168,IRQ1 Of Input Capture 0 (ch.1) IRQ Vector Address Bits" line.long 0x1C "IRQVA169,IRQ1 Of Input Capture 1 (ch.3) IRQ Vector Address Bits" line.long 0x20 "IRQVA170,IRQ1 Of Input Capture 2 (ch.5) IRQ Vector Address Bits" line.long 0x24 "IRQVA171,IRQ1 Of Input Capture 8 (ch.17) IRQ Vector Address Bits" line.long 0x28 "IRQVA172,IRQ1 Of Input Capture 9 (ch.19) IRQ Vector Address Bits" line.long 0x2C "IRQVA173,IRQ1 Of Input Capture 10 (ch.21) IRQ Vector Address Bits" line.long 0x30 "IRQVA174,IRQ0 Of Output Compare 0 (ch.0) IRQ Vector Address Bits" line.long 0x34 "IRQVA175,IRQ0 Of Output Compare 1 (ch.2) IRQ Vector Address Bits" line.long 0x38 "IRQVA176,IRQ0 Of Output Compare 2 (ch.4) IRQ Vector Address Bits" group.long 0x358++0x17 line.long 0x00 "IRQVA178,IRQ0 Of Output Compare 8 (ch.16) IRQ Vector Address Bits" line.long 0x04 "IRQVA179,IRQ0 Of Output Compare 9 (ch.18) IRQ Vector Address Bits" line.long 0x08 "IRQVA180,IRQ0 Of Output Compare 10 (ch.20) IRQ Vector Address Bits" line.long 0x0C "IRQVA181,IRQ1 Of Output Compare 0 (ch.1) IRQ Vector Address Bits" line.long 0x10 "IRQVA182,IRQ1 Of Output Compare 1 (ch.3) IRQ Vector Address Bits" line.long 0x14 "IRQVA183,IRQ1 Of Output Compare 2 (ch.5) IRQ Vector Address Bits" group.long 0x374++0x13 line.long 0x00 "IRQVA185,IRQ1 Of Output Compare 8 (ch.17) IRQ Vector Address Bits" line.long 0x04 "IRQVA186,IRQ1 Of Output Compare 9 (ch.19) IRQ Vector Address Bits" line.long 0x08 "IRQVA187,IRQ1 Of Output Compare 10 (ch.21) IRQ Vector Address Bits" line.long 0x0C "IRQVA188,(QPRC ch.8) IRQ Vector Address Bits" line.long 0x10 "IRQVA189,(QPRC ch.9) IRQ Vector Address Bits" sif !cpuis("S6J351*") group.long 0x388++0x0F line.long 0x00 "IRQVA190,(ADC12B0 Conversion Done) IRQ Vector Address Bits" line.long 0x04 "IRQVA191,(ADC12B0 Group Interrupt) IRQ Vector Address Bits" line.long 0x08 "IRQVA192,(ADC12B0 Pulse Detection Function) IRQ Vector Address Bits" line.long 0x0C "IRQVA193,(ADC12B0 RCO) IRQ Vector Address Bits" endif group.long 0x398++0x13 line.long 0x00 "IRQVA194,(ADC12B1 Conversion Done) IRQ Vector Address Bits" line.long 0x04 "IRQVA195,(ADC12B1 Group Interrupt) IRQ Vector Address Bits" line.long 0x08 "IRQVA196,(ADC12B1 Pulse Detection Function) IRQ Vector Address Bits" line.long 0x0C "IRQVA197,(ADC12B1 RCO) IRQ Vector Address Bits" line.long 0x10 "IRQVA198,(DMA Error) IRQ Vector Address Bits" group.long 0x3AC++0x03 line.long 0x00 "IRQVA199,(DMAC Completion ch.0)" group.long 0x3B0++0x03 line.long 0x00 "IRQVA200,(DMAC Completion ch.1)" group.long 0x3B4++0x03 line.long 0x00 "IRQVA201,(DMAC Completion ch.2)" group.long 0x3B8++0x03 line.long 0x00 "IRQVA202,(DMAC Completion ch.3)" group.long 0x3BC++0x03 line.long 0x00 "IRQVA203,(DMAC Completion ch.4)" group.long 0x3C0++0x03 line.long 0x00 "IRQVA204,(DMAC Completion ch.5)" group.long 0x3C4++0x03 line.long 0x00 "IRQVA205,(DMAC Completion ch.6)" group.long 0x3C8++0x03 line.long 0x00 "IRQVA206,(DMAC Completion ch.7)" group.long 0x3CC++0x03 line.long 0x00 "IRQVA207,(DMAC Completion ch.8)" group.long 0x3D0++0x03 line.long 0x00 "IRQVA208,(DMAC Completion ch.9)" group.long 0x3D4++0x03 line.long 0x00 "IRQVA209,(DMAC Completion ch.10)" group.long 0x3D8++0x03 line.long 0x00 "IRQVA210,(DMAC Completion ch.11)" group.long 0x3DC++0x03 line.long 0x00 "IRQVA211,(DMAC Completion ch.12)" group.long 0x3E0++0x03 line.long 0x00 "IRQVA212,(DMAC Completion ch.13)" group.long 0x3E4++0x03 line.long 0x00 "IRQVA213,(DMAC Completion ch.14)" group.long 0x3E8++0x03 line.long 0x00 "IRQVA214,(DMAC Completion ch.15)" group.long 0x3EC++0x1B line.long 0x00 "IRQVA215,DMAC RLT (ch.0/1/2/3 OR-ed) IRQ Vector Address Bits" line.long 0x04 "IRQVA216,(SCT RC IRQ) IRQ Vector Address Bits" line.long 0x08 "IRQVA217,(SCT SRC IRQ) IRQ Vector Address Bits" line.long 0x0C "IRQVA218,(SCT Main OSC IRQ) IRQ Vector Address Bits" line.long 0x10 "IRQVA219,(SCT Sub OSC IRQ) IRQ Vector Address Bits" line.long 0x14 "IRQVA220,(CR5 Performance Monitor Unit IRQ) IRQ Vector Address Bits" line.long 0x18 "IRQVA221,(PRGCRC) IRQ Vector Address Bits" group.long 0x408++0x03 line.long 0x00 "IRQVA222,(MFS ch.0 Error) IRQ Vector Address Bits" group.long 0x40C++0x03 line.long 0x00 "IRQVA223,(MFS ch.1 Error) IRQ Vector Address Bits" group.long 0x410++0x03 line.long 0x00 "IRQVA224,(MFS ch.2 Error) IRQ Vector Address Bits" group.long 0x414++0x03 line.long 0x00 "IRQVA225,(MFS ch.3 Error) IRQ Vector Address Bits" group.long 0x418++0x03 line.long 0x00 "IRQVA226,(MFS ch.4 Error) IRQ Vector Address Bits" group.long 0x41C++0x03 line.long 0x00 "IRQVA227,(MFS ch.5 Error) IRQ Vector Address Bits" group.long 0x420++0x03 line.long 0x00 "IRQVA228,(MFS ch.6 Error) IRQ Vector Address Bits" group.long 0x424++0x03 line.long 0x00 "IRQVA229,(MFS ch.7 Error) IRQ Vector Address Bits" group.long 0x428++0x03 line.long 0x00 "IRQVA230,(MFS ch.8 Error) IRQ Vector Address Bits" group.long 0x42C++0x03 line.long 0x00 "IRQVA231,(MFS ch.9 Error) IRQ Vector Address Bits" group.long 0x430++0x03 line.long 0x00 "IRQVA232,(MFS ch.10 Error) IRQ Vector Address Bits" group.long 0x434++0x03 line.long 0x00 "IRQVA233,(MFS ch.11 Error) IRQ Vector Address Bits" sif !cpuis("S6J351*") group.long 0x438++0x03 line.long 0x00 "IRQVA234,(MFS ch.12 Error) IRQ Vector Address Bits" endif sif !cpuis("S6J351*") group.long 0x43C++0x03 line.long 0x00 "IRQVA235,(MFS ch.13 Error) IRQ Vector Address Bits" endif tree.end width 8. tree "NMI Priority Level Registers" group.long 0x890++0x07 line.long 0x00 "NMIPL0,Priority Level Register" bitfld.long 0x00 0.--3. " NMIPL0 ,(NMIX pin(Ext-IRC) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "NMIPL1,Priority Level Register" bitfld.long 0x04 24.--27. " NMIPL7 ,(SW-WDT) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " NMIPL6 ,(HW-WDT) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " NMIPL5 ,(CSV profile) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " NMIPL4 ,(LVDs IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("S6J351*") group.long 0x898++0x03 line.long 0x00 "NMIPL2,Priority Level Register" bitfld.long 0x00 0.--3. " NMIPL8 ,(IRC 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " NMIPL9 ,(Expand PLL CSV(OR-ed of all factors)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x898++0x03 line.long 0x00 "NMIPL2,Priority Level Register" bitfld.long 0x00 0.--3. " NMIPL8 ,(IRC 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x89C++0x07 line.long 0x00 "NMIPL3,Priority Level Register" bitfld.long 0x00 24.--27. " NMIPL15 ,(SHE MPU) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " NMIPL13 ,(DMAC MPU #0 protection violation) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NMIPL12 ,(CAN-FD RAMs 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "NMIPL4,Priority Level Register" bitfld.long 0x04 16.--19. " NMIPL18 ,(TPU protection violation) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif !cpuis("S6J351*") group.long 0x8A4++0x03 line.long 0x00 "NMIPL6,Priority Level Register" bitfld.long 0x00 0.--3. " NMIPL24 ,(Bus diagnosis error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif tree.end width 9. tree "IRQ Priority Level Registers" group.long 0x8B0++0x03 line.long 0x00 "IRQPL0,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (SW-WDT pre-warning) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (HW-WDTpre-warning) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1(system control status) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8B8++0x3B line.long 0x00 "IRQPL2,Priority Level Register" bitfld.long 0x00 16.--20. " IRQPL10 ,IRQ10 (work FLASH hang up) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL8 ,IRQ8 (TCFLASH RDY/hang up/single bit error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IRQPL3,Priority Level Register" bitfld.long 0x04 24.--28. " IRQPL15 ,IRQ15 (CAN FD RAM(ch.0 to 4/ch.8) single bit error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " IRQPL14 ,IRQ14 (system SRAM single bit error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "IRQPL4,Priority Level Register" bitfld.long 0x08 0.--4. " IRQPL16 ,IRQ16 (IRC vector address RAM single bit error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "IRQPL5,IRQ Priority Level Register" bitfld.long 0x0C 0.--4. " IRQPL20 ,IRQ20 (work FLASH RDY/write enable release/single bit error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "IRQPL6,Priority Level Register" bitfld.long 0x10 24.--28. " IRQPL27 ,IRQ27 (external interrupt request ch.3/ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 16.--20. " IRQPL26 ,IRQ26 (external interrupt request ch.2/ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 8.--12. " IRQPL25 ,IRQ25 (external interrupt request ch.1/ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. " IRQPL24 ,IRQ24 (external interrupt request ch.0/ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "IRQPL7,Priority Level Register" bitfld.long 0x14 24.--28. " IRQPL31 ,IRQ31 (external interrupt request ch.7/ch.20) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " IRQPL30 ,IRQ30 (external interrupt request ch.6/ch.21) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--12. " IRQPL29 ,IRQ29 (external interrupt request ch.5/ch.22) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 0.--4. " IRQPL28 ,IRQ28 (external interrupt request ch.4/ch.23) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "IRQPL8,Priority Level Register" bitfld.long 0x18 24.--28. " IRQPL35 ,IRQ35 (external interrupt request ch.11/ch.27) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 16.--20. " IRQPL34 ,IRQ34 (external interrupt request ch.10/ch.26) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 8.--12. " IRQPL33 ,IRQ33 (external interrupt request ch.9/ch.25) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 0.--4. " IRQPL32 ,IRQ32 (external interrupt request ch.8/ch.24) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "IRQPL9,Priority Level Register" bitfld.long 0x1C 24.--28. " IRQPL39 ,IRQ39 (external interrupt request ch.15/ch.31) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 16.--20. " IRQPL38 ,IRQ38 (external interrupt request ch.14/ch.30) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 8.--12. " IRQPL37 ,IRQ37 (external interrupt request ch.13/ch.29) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 0.--4. " IRQPL36 ,IRQ36 (external interrupt request ch.12/ch.28) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "IRQPL10,Priority Level Register" bitfld.long 0x20 24.--28. " IRQPL43 ,IRQ43 (CAN FD ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 16.--20. " IRQPL42 ,IRQ42 (CAN FD ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 8.--12. " IRQPL41 ,IRQ41 (CAN FD ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 0.--4. " IRQPL40 ,IRQ40 (CAN FD ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "IRQPL11,Priority Level Register" bitfld.long 0x24 24.--28. " IRQPL47 ,IRQ47 (MFS TX ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 16.--20. " IRQPL46 ,IRQ46 (MFS RX ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 8.--12. " IRQPL45 ,IRQ45 (CAN FD ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 0.--4. " IRQPL44 ,IRQ44 (CAN FD ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "IRQPL12,Priority Level Register" bitfld.long 0x28 24.--28. " IRQPL51 ,IRQ51 (MFS TX ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 16.--20. " IRQPL50 ,IRQ50 (MFS RX ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 8.--12. " IRQPL49 ,IRQ49 (MFS TX ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 0.--4. " IRQPL48 ,IRQ48 (MFS RX ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x2C "IRQPL13,Priority Level Register" bitfld.long 0x2C 24.--28. " IRQPL55 ,IRQ55 (MFS TX ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 16.--20. " IRQPL54 ,IRQ54 (MFS RX ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 8.--12. " IRQPL53 ,IRQ53 (MFS TX ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x2C 0.--4. " IRQPL52 ,IRQ52 (MFS RX ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "IRQPL14,Priority Level Register" bitfld.long 0x30 24.--28. " IRQPL59 ,IRQ59 (MFS TX ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 16.--20. " IRQPL58 ,IRQ58 (MFS RX ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 8.--12. " IRQPL57 ,IRQ57 (MFS TX ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 0.--4. " IRQPL56 ,IRQ56 (MFS RX ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "IRQPL15,Priority Level Register" bitfld.long 0x34 24.--28. " IRQPL63 ,IRQ63 (MFS TX ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 16.--20. " IRQPL62 ,IRQ62 (MFS RX ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 8.--12. " IRQPL61 ,IRQ61 (MFS TX ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x34 0.--4. " IRQPL60 ,IRQ60 (MFS RX ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x38 "IRQPL16,Priority Level Register" bitfld.long 0x38 24.--28. " IRQPL67 ,IRQ67 (MFS TX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 16.--20. " IRQPL66 ,IRQ66 (MFS RX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 8.--12. " IRQPL65 ,IRQ65 (MFS TX ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x38 0.--4. " IRQPL64 ,IRQ64 (MFS RX ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif cpuis("S6J351*") group.long 0x8F4++0x03 line.long 0x00 "IRQPL17,Priority Level Register" bitfld.long 0x00 8.--12. " IRQPL69 ,IRQ69 (MFS TX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL68 ,IRQ68 (MFS RX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x8F4++0x07 line.long 0x00 "IRQPL17,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL71 ,IRQ71 (MFS TX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL70 ,IRQ70 (MFS RX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL69 ,IRQ69 (MFS TX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL68 ,IRQ68 (MFS RX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IRQPL18,Priority Level Register" bitfld.long 0x04 8.--12. " IRQPL73 ,IRQ73 (MFS TX ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " IRQPL72 ,IRQ72 (MFS RX ch.13 priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x908++0x03 line.long 0x00 "IRQPL22,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL91 ,IRQ91 (SHE error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif cpuis("S6J351*") group.long 0x90C++0x03 line.long 0x00 "IRQPL23,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL95 ,IRQ95 (TCRAM diag) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL94 ,IRQ94 (DDR HSSPI RX) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL93 ,IRQ93 (DDR HSSPI RX) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL92 ,IRQ92 (SHE) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x90C++0x03 line.long 0x00 "IRQPL23,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL95 ,IRQ95 (TCRAM diag) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL92 ,IRQ92 (SHE) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x910++0x1B line.long 0x00 "IRQPL24,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL99 ,IRQ99 (CR calibration) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL98 ,IRQ98 (RTC) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL97 ,IRQ97 (global timer) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IRQPL25,Priority Level Register" bitfld.long 0x04 24.--28. " IRQPL103 ,IRQ103 (base timer ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " IRQPL102 ,IRQ102 (base timer ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " IRQPL101 ,IRQ101 (base timer ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " IRQPL100 ,IRQ100 (base timer ch.0/8/9/10/11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "IRQPL26,Priority Level Register" bitfld.long 0x08 24.--28. " IRQPL107 ,IRQ107 (base timer ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 16.--20. " IRQPL106 ,IRQ106 (base timer ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " IRQPL105 ,IRQ105 (base timer ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " IRQPL104 ,IRQ104 (base timer ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "IRQPL27,Priority Level Register" bitfld.long 0x0C 24.--28. " IRQPL111 ,IRQ111 (base timer ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " IRQPL110 ,IRQ110 (base timer ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " IRQPL109 ,IRQ109 (base timer ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 0.--4. " IRQPL108 ,IRQ108 (base timer ch.12/20/21/22/23) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "IRQPL28,Priority Level Register" bitfld.long 0x10 24.--28. " IRQPL115 ,IRQ115 (base timer ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 16.--20. " IRQPL114 ,IRQ114 (base timer ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 8.--12. " IRQPL113 ,IRQ113 (base timer ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. " IRQPL112 ,IRQ112 (base timer ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "IRQPL29,Priority Level Register" bitfld.long 0x14 24.--28. " IRQPL119 ,IRQ119 (base timer ch.27) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " IRQPL118 ,IRQ118 (base timer ch.26) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--12. " IRQPL117 ,IRQ117 (base timer ch.25) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 0.--4. " IRQPL116 ,IRQ116 (base timer ch.24/32/33/34/35) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "IRQPL30,Priority Level Register" bitfld.long 0x18 24.--28. " IRQPL123 ,IRQ123 (base timer ch.31) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 16.--20. " IRQPL122 ,IRQ122 (base timer ch.30) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 8.--12. " IRQPL121 ,IRQ121 (base timer ch.29) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 0.--4. " IRQPL120 ,IRQ120 (base timer ch.28) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif !cpuis("S6J351*") group.long 0x92C++0x13 line.long 0x00 "IRQPL31,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL127 ,IRQ127 (base timer ch.39) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL126 ,IRQ126 (base timer ch.38) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL125 ,IRQ125 (base timer ch.37) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL124 ,IRQ124 (base timer ch.36/44/45/46/47) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IRQPL32,Priority Level Register" bitfld.long 0x04 24.--28. " IRQPL131 ,IRQ131 (base timer ch.43) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " IRQPL130 ,IRQ130 (base timer ch.42) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " IRQPL129 ,IRQ129 (base timer ch.41) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " IRQPL128 ,IRQ128 (base timer ch.40) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "IRQPL33,Priority Level Register" bitfld.long 0x08 24.--28. " IRQPL135 ,IRQ135 (base timer ch.51) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 16.--20. " IRQPL134 ,IRQ134 (base timer ch.50) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " IRQPL133 ,IRQ133 (base timer ch.49) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " IRQPL132 ,IRQ132 (base timer ch.48/56/57/58/59) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "IRQPL34,Priority Level Register" bitfld.long 0x0C 24.--28. " IRQPL139 ,IRQ139 (base timer ch.55) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " IRQPL138 ,IRQ138 (base timer ch.54) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " IRQPL137 ,IRQ137 (base timer ch.53) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 0.--4. " IRQPL136 ,IRQ136 (base timer ch.52) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "IRQPL35,Priority Level Register" bitfld.long 0x10 24.--28. " IRQPL143 ,IRQ143 (base timer ch.63) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 16.--20. " IRQPL142 ,IRQ142 (base timer ch.62) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 8.--12. " IRQPL141 ,IRQ141 (base timer ch.61) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. " IRQPL140 ,IRQ140 (base timer ch.60) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x940++0x2B line.long 0x00 "IRQPL36,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL147 ,IRQ147 (reload timer ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL146 ,IRQ146 (reload timer ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL145 ,IRQ145 (reload timer ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL144 ,IRQ144 (reload timer ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IRQPL37,Priority Level Register" bitfld.long 0x04 24.--28. " IRQPL151 ,IRQ151 (FRT ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " IRQPL150 ,IRQ150 (FRT ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " IRQPL149 ,IRQ149 (reload timer ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " IRQPL148 ,IRQ148 (reload timer ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "IRQPL38,Priority Level Register" bitfld.long 0x08 16.--20. " IRQPL154 ,IRQ154 (FRT ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " IRQPL153 ,IRQ153 (FRT ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " IRQPL152 ,IRQ152 (FRT ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "IRQPL39,Priority Level Register" bitfld.long 0x0C 16.--20. " IRQPL158 ,IRQ158 (FRT ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " IRQPL157 ,IRQ157 (FRT ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 0.--4. " IRQPL156 ,IRQ156 (FRT ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "IRQPL40,Priority Level Register" bitfld.long 0x10 24.--28. " IRQPL163 ,IRQ163 (IRQ0 of input capture 1 (ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 16.--20. " IRQPL162 ,IRQ162 (IRQ0 of input capture 0 (ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "IRQPL41,Priority Level Register" bitfld.long 0x14 24.--28. " IRQPL167 ,IRQ167 (IRQ0 of input capture 10 (ch.20) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " IRQPL166 ,IRQ166 (IRQ0 of input capture 9 (ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--12. " IRQPL165 ,IRQ165 (IRQ0 of input capture 8 (ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 0.--4. " IRQPL164 ,IRQ164 (IRQ0 of input capture 2 (ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "IRQPL42,Priority Level Register" bitfld.long 0x18 24.--28. " IRQPL171 ,IRQ171 (IRQ1 of input capture 8 (ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 16.--20. " IRQPL170 ,IRQ170 (IRQ1 of input capture 2 (ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 8.--12. " IRQPL169 ,IRQ169 (IRQ1 of input capture 1 (ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 0.--4. " IRQPL168 ,IRQ168 (IRQ1 of input capture 0 (ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "IRQPL43,Priority Level Register" bitfld.long 0x1C 24.--28. " IRQPL175 ,IRQ175 (IRQ0 of output compare 1 (ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 16.--20. " IRQPL174 ,IRQ174 (IRQ0 of output compare 0 (ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 8.--12. " IRQPL173 ,IRQ173 (IRQ1 of input capture 10 (ch.21) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 0.--4. " IRQPL172 ,IRQ172 (IRQ1 of input capture 9 (ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "IRQPL44,Priority Level Register" bitfld.long 0x20 24.--28. " IRQPL179 ,IRQ179 (IRQ0 of output compare 9 (ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 16.--20. " IRQPL178 ,IRQ178 (IRQ0 of output compare 8 (ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 0.--4. " IRQPL176 ,IRQ176 (IRQ0 of output compare 2 (ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "IRQPL45,Priority Level Register" bitfld.long 0x24 24.--28. " IRQPL183 ,IRQ183 (IRQ1 of output compare 2 (ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 16.--20. " IRQPL182 ,IRQ182 (IRQ1 of output compare 1 (ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 8.--12. " IRQPL181 ,IRQ181 (IRQ1 of output compare 0 (ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x24 0.--4. " IRQPL180 ,IRQ180 (IRQ0 of output compare 10 (ch.20) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "IRQPL46,Priority Level Register" bitfld.long 0x28 24.--28. " IRQPL187 ,IRQ187 (IRQ1 of output compare 10 (ch.21) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 16.--20. " IRQPL186 ,IRQ186 (IRQ1 of output compare 9 (ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 8.--12. " IRQPL185 ,IRQ185 (IRQ1 of output compare 8 (ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif cpuis("S6J351*") group.long 0x96C++0x07 line.long 0x00 "IRQPL47,Priority Level Register" bitfld.long 0x00 8.--12. " IRQPL189 ,IRQ189 (QPRC ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL188 ,IRQ188 (QPRC ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IRQPL48,Priority Level Register" bitfld.long 0x04 24.--28. " IRQPL195 ,IRQ195 (ADC12B1 group interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " IRQPL194 ,IRQ194 (ADC12B1 conversion done) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x96C++0x07 line.long 0x00 "IRQPL47,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL191 ,IRQ191 (ADC12B0 group interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL190 ,IRQ190 (ADC12B0 conversion done) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL189 ,IRQ189 (QPRC ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL188 ,IRQ188 (QPRC ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IRQPL48,Priority Level Register" bitfld.long 0x04 24.--28. " IRQPL195 ,IRQ195 (ADC12B1 group interrupt) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " IRQPL194 ,IRQ194 (ADC12B1 conversion done) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " IRQPL193 ,IRQ193 (ADC12B0 RCO) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " IRQPL192 ,IRQ192 (ADC12B0 pulse detection function) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x974++0x23 line.long 0x00 "IRQPL49,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL199 ,IRQ199 (DMAC completion ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL198 ,IRQ198 (DMA error) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL197 ,IRQ197 (ADC12B1 RCO) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL196 ,IRQ196 (ADC12B1 pulse detection function) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IRQPL50,Priority Level Register" bitfld.long 0x04 24.--28. " IRQPL203 ,IRQ203 (DMAC completion ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. " IRQPL202 ,IRQ202 (DMAC completion ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " IRQPL201 ,IRQ201 (DMAC completion ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " IRQPL200 ,IRQ200 (DMAC completion ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "IRQPL51,Priority Level Register" bitfld.long 0x08 24.--28. " IRQPL207 ,IRQ207 (DMAC completion ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 16.--20. " IRQPL206 ,IRQ206 (DMAC completion ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " IRQPL205 ,IRQ205 (DMAC completion ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 0.--4. " IRQPL204 ,IRQ204 (DMAC completion ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "IRQPL52,Priority Level Register" bitfld.long 0x0C 24.--28. " IRQPL211 ,IRQ211 (DMAC completion ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " IRQPL210 ,IRQ210 (DMAC completion ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " IRQPL209 ,IRQ209 (DMAC completion ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 0.--4. " IRQPL208 ,IRQ208 (DMAC completion ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "IRQPL53,Priority Level Register" bitfld.long 0x10 16.--20. " IRQPL215 ,IRQ215 (DMAC RLT) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 24.--28. " IRQPL214 ,IRQ214 (DMAC completion ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 8.--12. " IRQPL213 ,IRQ213 (DMAC completion ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. " IRQPL212 ,IRQ212 (DMAC completion ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "IRQPL54,Priority Level Register" bitfld.long 0x14 24.--28. " IRQPL219 ,IRQ219 (SCT sub OSC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " IRQPL218 ,IRQ218 (SCT main OSC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--12. " IRQPL217 ,IRQ217 (SCT SRC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 0.--4. " IRQPL216 ,IRQ216 (SCT RC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "IRQPL55,Priority Level Register" bitfld.long 0x18 24.--28. " IRQPL223 ,IRQ223 (MFS ch.1 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 16.--20. " IRQPL222 ,IRQ222 (MFS ch.0 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 8.--12. " IRQPL221 ,IRQ221 (PRGCRC) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 0.--4. " IRQPL220 ,IRQ220 (CR5 performance monitor unit IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "IRQPL56,Priority Level Register" bitfld.long 0x1C 24.--28. " IRQPL227 ,IRQ227 (MFS ch.5 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 16.--20. " IRQPL226 ,IRQ226 (MFS ch.4 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 8.--12. " IRQPL225 ,IRQ225 (MFS ch.3 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 0.--4. " IRQPL224 ,IRQ224 (MFS ch.2 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "IRQPL57,Priority Level Register" bitfld.long 0x20 24.--28. " IRQPL231 ,IRQ231 (MFS ch.9 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 16.--20. " IRQPL230 ,IRQ230 (MFS ch.8 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 8.--12. " IRQPL229 ,IRQ229 (MFS ch.7 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 0.--4. " IRQPL228 ,IRQ228 (MFS ch.6 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" sif cpuis("S6J351*") group.long 0x998++0x03 line.long 0x00 "IRQPL58,Priority Level Register" bitfld.long 0x00 8.--12. " IRQPL233 ,IRQ233 (MFS ch.11 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL232 ,IRQ232 (MFS ch.10 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x998++0x03 line.long 0x00 "IRQPL58,Priority Level Register" bitfld.long 0x00 24.--28. " IRQPL235 ,IRQ235 (MFS ch.13 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " IRQPL234 ,IRQ234 (MFS ch.12 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " IRQPL233 ,IRQ233 (MFS ch.11 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IRQPL232 ,IRQ232 (MFS ch.10 error (Tx/Rx error/status OR-ed) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif tree.end newline width 16. group.long 0xAB8++0x03 line.long 0x00 "NMISIS_SET/CLR,IRC NMI Software Interrupt Status Register" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " NMISIS[24] ,NMI24 (Bus diagnosis error detection) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,NMI18 (TPU protection violation) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,NMI15 (SHE MPU) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,NMI13 (DMAC MPU #0 protection violation) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,NMI12 (CAN-FD RAMs 2-bit ECC error detection) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x08 08. -0x04 08. " [8] ,NMI8 (IRC 2-bit ECC err detection) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x08 07. -0x04 07. " [7] ,NMI7 (SW-WDT) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x08 06. -0x04 06. " [6] ,NMI6 (HW-WDT) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 05. -0x08 05. -0x04 05. " [5] ,NMI5 (CSV/profile) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x08 04. -0x04 04. " [4] ,NMI4 (LVDs IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x08 01. -0x04 00. " [0] ,NMI0 (NMIX pin(Ext-IRC) software interrupt status bit" "No interrupt,Interrupt" width 17. tree "IRC IRQ Software Interrupt Status Registers" group.long 0xB40++0x03 line.long 0x00 "IRQSIS0_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[31] ,IRQ (external interrupt request ch.7/ch.23) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [30] ,IRQ (external interrupt request ch.6/ch.22) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [29] ,IRQ (external interrupt request ch.5/ch.21) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [28] ,IRQ (external interrupt request ch.4/ch.20) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [27] ,IRQ (external interrupt request ch.3/ch.19) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [26] ,IRQ (external interrupt request ch.2/ch.18) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [25] ,IRQ (external interrupt request ch.1/ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [24] ,IRQ (external interrupt request ch.0/ch.16) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [20] ,IRQ (work FLASH RDY/write enable release/single bit error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [16] ,IRQ (IRC vector address RAM single bit error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [15] ,IRQ (CAN FD RAM) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [14] ,IRQ (system SRAM single bit error) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [10] ,IRQ (work FLASH hang up) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [8] ,IRQ (TCFLASH RDY/hang up/single bit error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [3] ,IRQ (SW-WDT pre-warning) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [2] ,IRQ (HW-WDT pre-warning) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [1] ,IRQ (system control status) software interrupt status bit" "No interrupt,Interrupt" sif cpuis("S6J351*") group.long 0xB44++0x1B line.long 0x00 "IRQSIS1_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[63] ,IRQ (MFS TX ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [62] ,IRQ (MFS RX ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [61] ,IRQ (MFS TX ch.7) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [60] ,IRQ (MFS RX ch.7) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [59] ,IRQ (MFS TX ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [58] ,IRQ (MFS RX ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [57] ,IRQ (MFS TX ch.5) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [56] ,IRQ (MFS RX ch.5) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [55] ,IRQ (MFS TX ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [54] ,IRQ (MFS RX ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [53] ,IRQ (MFS TX ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [52] ,IRQ (MFS RX ch.3) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [51] ,IRQ (MFS TX ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [50] ,IRQ (MFS RX ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [49] ,IRQ (MFS TX ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [48] ,IRQ (MFS RX ch.1) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [47] ,IRQ (MFS TX ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [46] ,IRQ (MFS RX ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [43] ,IRQ (CAN FD ch.3 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [42] ,IRQ (CAN FD ch.2 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [39] ,IRQ (external interrupt request ch.15/ch.31) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [38] ,IRQ (external interrupt request ch.14/ch.30) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [37] ,IRQ (external interrupt request ch.13/ch.29) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [36] ,IRQ (external interrupt request ch.12/ch.28) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [35] ,IRQ (external interrupt request ch.11/ch.27) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [34] ,IRQ (external interrupt request ch.10/ch.26) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [33] ,IRQ (external interrupt request ch.9/ch.25) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " [32] ,IRQ (external interrupt request ch.8/ch.24) software interrupt status bit" "No interrupt,Interrupt" line.long 0x04 "IRQSIS2_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x04 31. -0x7C 31. -0x3C 31. " IRQSIS[95] ,IRQ (TCRAM diag) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 30. -0x7C 30. -0x3C 30. " [94] ,IRQ (DDR HSSPI TX) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 29. -0x7C 29. -0x3C 29. " [93] ,IRQ (DDR HSSPI RX) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 28. -0x7C 28. -0x3C 28. " [92] ,IRQ (SHE) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 27. -0x7C 27. -0x3C 27. " [91] ,IRQ (SHE error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 05. -0x7C 05. -0x3C 05. " [69] ,IRQ (MFS TX ch.11) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 04. -0x7C 04. -0x3C 04. " [68] ,IRQ (MFS RX ch.11) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 03. -0x7C 03. -0x3C 03. " [67] ,IRQ (MFS TX ch.10) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 02. -0x7C 02. -0x3C 02. " [66] ,IRQ (MFS RX ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 01. -0x7C 01. -0x3C 01. " [65] ,IRQ (MFS TX ch.9) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 00. -0x7C 00. -0x3C 00. " [64] ,IRQ (MFS RX ch.9) software interrupt status bit" "No interrupt,Interrupt" line.long 0x08 "IRQSIS3_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x08 27. -0x78 27. -0x38 27. " IRQSIS[123] ,IRQ (base timer ch.31) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 26. -0x78 26. -0x38 26. " [122] ,IRQ (base timer ch.30) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 25. -0x78 25. -0x38 25. " [121] ,IRQ (base timer ch.29) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 24. -0x78 24. -0x38 24. " [120] ,IRQ (base timer ch.28) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 23. -0x78 23. -0x38 23. " [119] ,IRQ (base timer ch.27) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 22. -0x78 22. -0x38 22. " [118] ,IRQ (base timer ch.26) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 21. -0x78 21. -0x38 21. " [117] ,IRQ (base timer ch.25) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 20. -0x78 20. -0x38 20. " [116] ,IRQ (base timer ch.24/32/33/34/35) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 19. -0x78 19. -0x38 19. " [115] ,IRQ (base timer ch.19) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 18. -0x78 18. -0x38 18. " [114] ,IRQ (base timer ch.18) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 17. -0x78 17. -0x38 17. " [113] ,IRQ (base timer ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 16. -0x78 16. -0x38 16. " [112] ,IRQ (base timer ch.16) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 15. -0x78 15. -0x38 15. " [111] ,IRQ (base timer ch.15) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 14. -0x78 14. -0x38 14. " [110] ,IRQ (base timer ch.14) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 13. -0x78 13. -0x38 13. " [109] ,IRQ (base timer ch.13) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 12. -0x78 12. -0x38 12. " [108] ,IRQ (base timer ch.12/20/21/22/23) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 11. -0x78 11. -0x38 11. " [107] ,IRQ (base timer ch.7) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 10. -0x78 10. -0x38 10. " [106] ,IRQ (base timer ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 09. -0x78 09. -0x38 09. " [105] ,IRQ (base timer ch.5) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 08. -0x78 08. -0x38 08. " [104] ,IRQ (base timer ch.4) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 07. -0x78 07. -0x38 07. " [103] ,IRQ (base timer ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 06. -0x78 06. -0x38 06. " [102] ,IRQ (base timer ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 05. -0x78 05. -0x38 05. " [101] ,IRQ (base timer ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 04. -0x78 04. -0x38 04. " [100] ,IRQ (base timer ch.0/8/9/10/11) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 03. -0x78 03. -0x38 03. " [99] ,IRQ (CR CARIBRATION) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 02. -0x78 02. -0x38 02. " [98] ,IRQ (RTC) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 01. -0x78 01. -0x38 01. " [97] ,IRQ (global timer (compare clear interrupt)) software interrupt status bit" "No interrupt,Interrupt" line.long 0x0C "IRQSIS4_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x0C 30. -0x74 30. -0x34 30. " IRQSIS[158] ,IRQ (FRT ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 29. -0x74 29. -0x34 29. " [157] ,IRQ (FRT ch.9) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 28. -0x74 28. -0x34 28. " [156] ,IRQ (FRT ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 26. -0x74 26. -0x34 26. " [154] ,IRQ (FRT ch.4) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 25. -0x74 25. -0x34 25. " [153] ,IRQ (FRT ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 24. -0x74 24. -0x34 24. " [152] ,IRQ (FRT ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 23. -0x74 23. -0x34 23. " [151] ,IRQ (FRT ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 22. -0x74 22. -0x34 22. " [150] ,IRQ (FRT ch.0) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " [149] ,IRQ (reload timer ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 20. -0x74 20. -0x34 20. " [148] ,IRQ (reload timer ch.16) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 19. -0x74 19. -0x34 19. " [147] ,IRQ (reload timer ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 18. -0x74 18. -0x34 18. " [146] ,IRQ (reload timer ch.2) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 17. -0x74 17. -0x34 17. " [145] ,IRQ (reload timer ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 16. -0x74 16. -0x34 16. " [144] ,IRQ (reload timer ch.0) software interrupt status bit" "No interrupt,Interrupt" line.long 0x10 "IRQSIS5_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x10 29. -0x70 29. -0x30 29. " IRQSIS[189] ,IRQ (QPRC ch.9) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 28. -0x70 28. -0x30 28. " [188] ,IRQ (QPRC ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 27. -0x70 27. -0x30 27. " [187] ,IRQ (IRQ1 of output compare 10 (ch.21) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 26. -0x70 26. -0x30 26. " [186] ,IRQ1 of output compare 9 (ch.19) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 25. -0x70 25. -0x30 25. " [185] ,IRQ (IRQ1 of output compare 8 (ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 23. -0x70 23. -0x30 23. " [183] ,IRQ (IRQ1 of output compare 2 (ch.5) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 22. -0x70 22. -0x30 22. " [182] ,IRQ (IRQ1 of output compare 1 (ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 21. -0x70 21. -0x30 21. " [181] ,IRQ (IRQ1 of output compare 0 (ch.1) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 20. -0x70 20. -0x30 20. " [180] ,IRQ (IRQ0 of output compare 10 (ch.20) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 19. -0x70 19. -0x30 19. " [179] ,IRQ (IRQ0 of output compare 9 (ch.18) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 18. -0x70 18. -0x30 18. " [178] ,IRQ (IRQ0 of output compare 8 (ch.16) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 16. -0x70 16. -0x30 16. " [176] ,IRQ (IRQ0 of output compare 2 (ch.4) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 15. -0x70 15. -0x30 15. " [175] ,IRQ (IRQ0 of output compare 1 (ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 14. -0x70 14. -0x30 14. " [174] ,IRQ (IRQ0 of output compare 0 (ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 13. -0x70 13. -0x30 13. " [173] ,IRQ (IRQ1 of input capture 10 (ch.21) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 12. -0x70 12. -0x30 12. " [172] ,IRQ (IRQ1 of input capture 9 (ch.19) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 11. -0x70 11. -0x30 11. " [171] ,IRQ (IRQ1 of input capture 8 (ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 10. -0x70 10. -0x30 10. " [170] ,IRQ (IRQ1 of input capture 2 (ch.5) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 09. -0x70 09. -0x30 09. " [169] ,IRQ (IRQ1 of input capture 1 (ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 08. -0x70 08. -0x30 08. " [168] ,IRQ (IRQ1 of input capture 0 (ch.1) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 07. -0x70 07. -0x30 07. " [167] ,IRQ (IRQ0 of input capture 10 (ch.20) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 06. -0x70 06. -0x30 06. " [166] ,IRQ (IRQ0 of input capture 9 (ch.18) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 05. -0x70 05. -0x30 05. " [165] ,IRQ (IRQ0 of input capture 8 (ch.16) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 04. -0x70 04. -0x30 04. " [164] ,IRQ (IRQ0 of input capture 2 (ch.4) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 03. -0x70 03. -0x30 03. " [163] ,IRQ (RQ0 of input capture 1 (ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 02. -0x70 02. -0x30 02. " [162] ,IRQ (IRQ0 of input capture 0 (ch.0) software interrupt status bit" "No interrupt,Interrupt" line.long 0x14 "IRQSIS6_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x14 31. -0x6C 31. -0x2C 31. " IRQSIS[223] ,IRQ (MFS ch.1 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 30. -0x6C 30. -0x2C 30. " [222] ,IRQ (MFS ch.0 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 29. -0x6C 29. -0x2C 29. " [221] ,IRQ (PRGCRC) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 28. -0x6C 28. -0x2C 28. " [220] ,IRQ (CR5 performance monitor unit IRQ) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 27. -0x6C 27. -0x2C 27. " [219] ,IRQ (SCT Sub OSC IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 26. -0x6C 26. -0x2C 26. " [218] ,IRQ (SCT Main OSC IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 25. -0x6C 25. -0x2C 25. " [217] ,IRQ (SCT SRC IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 24. -0x6C 24. -0x2C 24. " [216] ,IRQ (SCT RC IRQ) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 23. -0x6C 23. -0x2C 23. " [215] ,IRQ (DMAC RLT (ch.0/1/2/3 OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 22. -0x6C 22. -0x2C 22. " [214] ,IRQ (DMAC completion ch.15) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 21. -0x6C 21. -0x2C 21. " [213] ,IRQ (DMAC completion ch.14) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " [212] ,IRQ (DMAC completion ch.13) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " [211] ,IRQ (DMAC completion ch.12) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " [210] ,IRQ (DMAC completion ch.11) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " [209] ,IRQ (DMAC completion ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " [208] ,IRQ (DMAC completion ch.9) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 15. -0x6C 15. -0x2C 15. " [207] ,IRQ (DMAC completion ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 14. -0x6C 14. -0x2C 14. " [206] ,IRQ (DMAC completion ch.7) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 13. -0x6C 13. -0x2C 13. " [205] ,IRQ (DMAC completion ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 12. -0x6C 12. -0x2C 12. " [204] ,IRQ (DMAC completion ch.5) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 11. -0x6C 11. -0x2C 11. " [203] ,IRQ (DMAC completion ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 10. -0x6C 10. -0x2C 10. " [202] ,IRQ (DMAC completion ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 09. -0x6C 09. -0x2C 09. " [201] ,IRQ (DMAC completion ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 08. -0x6C 08. -0x2C 08. " [200] ,IRQ (DMAC completion ch.1) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 07. -0x6C 07. -0x2C 07. " [199] ,IRQ (DMAC completion ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 06. -0x6C 06. -0x2C 06. " [198] ,IRQ (DMA error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 05. -0x6C 05. -0x2C 05. " [197] ,IRQ (ADC12B1 RCO) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 04. -0x6C 04. -0x2C 04. " [196] ,IRQ (ADC12B1 pulse detection function) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 03. -0x6C 03. -0x2C 03. " [195] ,IRQ (ADC12B1 group interrupt) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 02. -0x6C 02. -0x2C 02. " [194] ,IRQ (ADC12B1 conversion done) software interrupt status bit" "No interrupt,Interrupt" line.long 0x18 "IRQSIS7_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x18 09. -0x68 09. -0x28 09. " IRQSIS[233] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 08. -0x68 08. -0x28 08. " [232] ,IRQ (MFS ch.10 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 07. -0x68 07. -0x28 07. " [231] ,IRQ (MFS ch.9 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 06. -0x68 06. -0x28 06. " [230] ,IRQ (MFS ch.8 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 05. -0x68 05. -0x28 05. " [229] ,IRQ (MFS ch.7 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 04. -0x68 04. -0x28 04. " [228] ,IRQ (MFS ch.6 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 03. -0x68 03. -0x28 03. " [227] ,IRQ (MFS ch.5 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 02. -0x68 02. -0x28 02. " [226] ,IRQ (MFS ch.4 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 01. -0x68 01. -0x28 01. " [225] ,IRQ (MFS ch.3 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 00. -0x68 00. -0x28 00. " [224] ,IRQ (MFS ch.2 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" else group.long 0xB44++0x1B line.long 0x00 "IRQSIS1_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS[63] ,IRQ (MFS TX ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [62] ,IRQ (MFS RX ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [61] ,IRQ (MFS TX ch.7) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [60] ,IRQ (MFS RX ch.7) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [59] ,IRQ (MFS TX ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [58] ,IRQ (MFS RX ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [57] ,IRQ (MFS TX ch.5) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [56] ,IRQ (MFS RX ch.5) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [55] ,IRQ (MFS TX ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [54] ,IRQ (MFS RX ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [53] ,IRQ (MFS TX ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [52] ,IRQ (MFS RX ch.3) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [51] ,IRQ (MFS TX ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [50] ,IRQ (MFS RX ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [49] ,IRQ (MFS TX ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [48] ,IRQ (MFS RX ch.1) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [47] ,IRQ (MFS TX ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [46] ,IRQ (MFS RX ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 13. -0x80 13. -0x40 13. " [45] ,IRQ (CAN FD ch.8 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " [44] ,IRQ (CAN FD ch.4 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [43] ,IRQ (CAN FD ch.3 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [42] ,IRQ (CAN FD ch.2 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [39] ,IRQ (external interrupt request ch.15/ch.31) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [38] ,IRQ (external interrupt request ch.14/ch.30) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [37] ,IRQ (external interrupt request ch.13/ch.29) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [36] ,IRQ (external interrupt request ch.12/ch.28) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [35] ,IRQ (external interrupt request ch.11/ch.27) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [34] ,IRQ (external interrupt request ch.10/ch.26) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [33] ,IRQ (external interrupt request ch.9/ch.25) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " [32] ,IRQ (external interrupt request ch.8/ch.24) software interrupt status bit" "No interrupt,Interrupt" line.long 0x04 "IRQSIS2_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x04 31. -0x7C 31. -0x3C 31. " IRQSIS[95] ,IRQ (TCRAM diag) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 28. -0x7C 28. -0x3C 28. " [92] ,IRQ (SHE) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 27. -0x7C 27. -0x3C 27. " [91] ,IRQ (SHE error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 09. -0x7C 09. -0x3C 09. " [73] ,IRQ (MFS TX ch.13) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 08. -0x7C 08. -0x3C 08. " [72] ,IRQ (MFS RX ch.13) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 07. -0x7C 07. -0x3C 07. " [71] ,IRQ (MFS TX ch.12) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 06. -0x7C 06. -0x3C 05. " [70] ,IRQ (MFS RX ch.12) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 05. -0x7C 05. -0x3C 05. " [69] ,IRQ (MFS TX ch.11) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 04. -0x7C 04. -0x3C 04. " [68] ,IRQ (MFS RX ch.11) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 03. -0x7C 03. -0x3C 03. " [67] ,IRQ (MFS TX ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 02. -0x7C 02. -0x3C 02. " [66] ,IRQ (MFS RX ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x04 01. -0x7C 01. -0x3C 01. " [65] ,IRQ (MFS TX ch.9) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x04 00. -0x7C 00. -0x3C 00. " [64] ,IRQ (MFS RX ch.9) software interrupt status bit" "No interrupt,Interrupt" line.long 0x08 "IRQSIS3_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x08 31. -0x78 31. -0x38 31. " IRQSIS[127] ,IRQ (base timer ch.39) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 30. -0x78 30. -0x38 30. " [126] ,IRQ (base timer ch.38) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 29. -0x78 29. -0x38 29. " [125] ,IRQ (base timer ch.37) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 28. -0x78 28. -0x38 28. " [124] ,IRQ (base timer ch.36/44/45/46/47) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 27. -0x78 27. -0x38 27. " [123] ,IRQ (base timer ch.31) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 26. -0x78 26. -0x38 26. " [122] ,IRQ (base timer ch.30) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 25. -0x78 25. -0x38 25. " [121] ,IRQ (base timer ch.29) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 24. -0x78 24. -0x38 24. " [120] ,IRQ (base timer ch.28) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 23. -0x78 23. -0x38 23. " [119] ,IRQ (base timer ch.27) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 22. -0x78 22. -0x38 22. " [118] ,IRQ (base timer ch.26) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 21. -0x78 21. -0x38 21. " [117] ,IRQ (base timer ch.25) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 20. -0x78 20. -0x38 20. " [116] ,IRQ (base timer ch.24/32/33/34/35) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 19. -0x78 19. -0x38 19. " [115] ,IRQ (base timer ch.19) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 18. -0x78 18. -0x38 18. " [114] ,IRQ (base timer ch.18) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 17. -0x78 17. -0x38 17. " [113] ,IRQ (base timer ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 16. -0x78 16. -0x38 16. " [112] ,IRQ (base timer ch.16) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 15. -0x78 15. -0x38 15. " [111] ,IRQ (base timer ch.15) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 14. -0x78 14. -0x38 14. " [110] ,IRQ (base timer ch.14) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 13. -0x78 13. -0x38 13. " [109] ,IRQ (base timer ch.13) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 12. -0x78 12. -0x38 12. " [108] ,IRQ (base timer ch.12/20/21/22/23) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 11. -0x78 11. -0x38 11. " [107] ,IRQ (base timer ch.7) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 10. -0x78 10. -0x38 10. " [106] ,IRQ (base timer ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 09. -0x78 09. -0x38 09. " [105] ,IRQ (base timer ch.5) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 08. -0x78 08. -0x38 08. " [104] ,IRQ (base timer ch.4) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 07. -0x78 07. -0x38 07. " [103] ,IRQ (base timer ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 06. -0x78 06. -0x38 06. " [102] ,IRQ (base timer ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 05. -0x78 05. -0x38 05. " [101] ,IRQ (base timer ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 04. -0x78 04. -0x38 04. " [100] ,IRQ (base timer ch.0/8/9/10/11) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x08 03. -0x78 03. -0x38 03. " [99] ,IRQ (CR CARIBRATION) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 02. -0x78 02. -0x38 02. " [98] ,IRQ (RTC) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x08 01. -0x78 01. -0x38 01. " [97] ,IRQ (global timer (compare clear interrupt)) software interrupt status bit" "No interrupt,Interrupt" line.long 0x0C "IRQSIS4_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x0C 30. -0x74 30. -0x34 30. " IRQSIS[158] ,IRQ (FRT ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 29. -0x74 29. -0x34 29. " [157] ,IRQ (FRT ch.9) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 28. -0x74 28. -0x34 28. " [156] ,IRQ (FRT ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 26. -0x74 26. -0x34 26. " [154] ,IRQ (FRT ch.4) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 25. -0x74 25. -0x34 25. " [153] ,IRQ (FRT ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 24. -0x74 24. -0x34 24. " [152] ,IRQ (FRT ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 23. -0x74 23. -0x34 23. " [151] ,IRQ (FRT ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 22. -0x74 22. -0x34 22. " [150] ,IRQ (FRT ch.0) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " [149] ,IRQ (reload timer ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 20. -0x74 20. -0x34 20. " [148] ,IRQ (reload timer ch.16) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 19. -0x74 19. -0x34 19. " [147] ,IRQ (reload timer ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 18. -0x74 18. -0x34 18. " [146] ,IRQ (reload timer ch.2) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 17. -0x74 17. -0x34 17. " [145] ,IRQ (reload timer ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 16. -0x74 16. -0x34 16. " [144] ,IRQ (reload timer ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 15. -0x74 15. -0x34 15. " [143] ,IRQ (base timer ch.63) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 14. -0x74 14. -0x34 14. " [142] ,IRQ (base timer ch.62) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 13. -0x74 13. -0x34 13. " [141] ,IRQ (base timer ch.61) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 12. -0x74 12. -0x34 12. " [140] ,IRQ (base timer ch.60) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 11. -0x74 11. -0x34 11. " [139] ,IRQ (base timer ch.55) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 10. -0x74 10. -0x34 10. " [138] ,IRQ (base timer ch.54) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 09. -0x74 09. -0x34 09. " [137] ,IRQ (base timer ch.53) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 08. -0x74 08. -0x34 08. " [136] ,IRQ (base timer ch.52) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 07. -0x74 07. -0x34 07. " [135] ,IRQ (base timer ch.51) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 06. -0x74 06. -0x34 06. " [134] ,IRQ (base timer ch.50) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 05. -0x74 05. -0x34 05. " [133] ,IRQ (base timer ch.49) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 04. -0x74 04. -0x34 04. " [132] ,IRQ (base timer ch.48/56/57/58/59) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 03. -0x74 03. -0x34 03. " [131] ,IRQ (base timer ch.43) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 02. -0x74 02. -0x34 02. " [130] ,IRQ (base timer ch.42) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x0C 01. -0x74 01. -0x34 01. " [129] ,IRQ (base timer ch.41) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x0C 00. -0x74 00. -0x34 00. " [128] ,IRQ (base timer ch.40) software interrupt status bit" "No interrupt,Interrupt" line.long 0x10 "IRQSIS5_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x10 31. -0x70 31. -0x30 31. " IRQSIS[191] ,IRQ (ADC12B0 group interrupt) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 30. -0x70 30. -0x30 30. " [190] ,IRQ (ADC12B0 conversion done) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 29. -0x70 29. -0x30 29. " [189] ,IRQ (QPRC ch.9) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 28. -0x70 28. -0x30 28. " [188] ,IRQ (QPRC ch.8) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 27. -0x70 27. -0x30 27. " [187] ,IRQ (IRQ1 of output compare 10 (ch.21) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 26. -0x70 26. -0x30 26. " [186] ,IRQ1 of output compare 9 (ch.19) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 25. -0x70 25. -0x30 25. " [185] ,IRQ (IRQ1 of output compare 8 (ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 23. -0x70 23. -0x30 23. " [183] ,IRQ (IRQ1 of output compare 2 (ch.5) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 22. -0x70 22. -0x30 22. " [182] ,IRQ (IRQ1 of output compare 1 (ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 21. -0x70 21. -0x30 21. " [181] ,IRQ (IRQ1 of output compare 0 (ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 20. -0x70 20. -0x30 20. " [180] ,IRQ (IRQ0 of output compare 10 (ch.20) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 19. -0x70 19. -0x30 19. " [179] ,IRQ (IRQ0 of output compare 9 (ch.18) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 18. -0x70 18. -0x30 18. " [178] ,IRQ (IRQ0 of output compare 8 (ch.16) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 16. -0x70 16. -0x30 16. " [176] ,IRQ (IRQ0 of output compare 2 (ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 15. -0x70 15. -0x30 15. " [175] ,IRQ (IRQ0 of output compare 1 (ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 14. -0x70 14. -0x30 14. " [174] ,IRQ (IRQ0 of output compare 0 (ch.0) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 13. -0x70 13. -0x30 13. " [173] ,IRQ (IRQ1 of input capture 10 (ch.21) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 12. -0x70 12. -0x30 12. " [172] ,IRQ (IRQ1 of input capture 9 (ch.19) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 11. -0x70 11. -0x30 11. " [171] ,IRQ (IRQ1 of input capture 8 (ch.17) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 10. -0x70 10. -0x30 10. " [170] ,IRQ (IRQ1 of input capture 2 (ch.5) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 09. -0x70 09. -0x30 09. " [169] ,IRQ (IRQ1 of input capture 1 (ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 08. -0x70 08. -0x30 08. " [168] ,IRQ (IRQ1 of input capture 0 (ch.1) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 07. -0x70 07. -0x30 07. " [167] ,IRQ (IRQ0 of input capture 10 (ch.20) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 06. -0x70 06. -0x30 06. " [166] ,IRQ (IRQ0 of input capture 9 (ch.18) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x10 05. -0x70 05. -0x30 05. " [165] ,IRQ (IRQ0 of input capture 8 (ch.16) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 04. -0x70 04. -0x30 04. " [164] ,IRQ (IRQ0 of input capture 2 (ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 03. -0x70 03. -0x30 03. " [163] ,IRQ (RQ0 of input capture 1 (ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x10 02. -0x70 02. -0x30 02. " [162] ,IRQ (IRQ0 of input capture 0 (ch.0) software interrupt status bit" "No interrupt,Interrupt" line.long 0x14 "IRQSIS6_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x14 31. -0x6C 31. -0x2C 31. " IRQSIS[223] ,IRQ (MFS ch.1 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 30. -0x6C 30. -0x2C 30. " [222] ,IRQ (MFS ch.0 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 29. -0x6C 29. -0x2C 29. " [221] ,IRQ (PRGCRC) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 28. -0x6C 28. -0x2C 28. " [220] ,IRQ (CR5 performance monitor unit IRQ) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 27. -0x6C 27. -0x2C 27. " [219] ,IRQ (SCT Sub OSC IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 26. -0x6C 26. -0x2C 26. " [218] ,IRQ (SCT Main OSC IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 25. -0x6C 25. -0x2C 25. " [217] ,IRQ (SCT SRC IRQ) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 24. -0x6C 24. -0x2C 24. " [216] ,IRQ (SCT RC IRQ) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 23. -0x6C 23. -0x2C 23. " [215] ,IRQ (DMAC RLT (ch.0/1/2/3 OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 22. -0x6C 22. -0x2C 22. " [214] ,IRQ (DMAC completion ch.15) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 21. -0x6C 21. -0x2C 21. " [213] ,IRQ (DMAC completion ch.14) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " [212] ,IRQ (DMAC completion ch.13) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " [211] ,IRQ (DMAC completion ch.12) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " [210] ,IRQ (DMAC completion ch.11) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " [209] ,IRQ (DMAC completion ch.10) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " [208] ,IRQ (DMAC completion ch.9) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 15. -0x6C 15. -0x2C 15. " [207] ,IRQ (DMAC completion ch.8) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 14. -0x6C 14. -0x2C 14. " [206] ,IRQ (DMAC completion ch.7) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 13. -0x6C 13. -0x2C 13. " [205] ,IRQ (DMAC completion ch.6) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 12. -0x6C 12. -0x2C 12. " [204] ,IRQ (DMAC completion ch.5) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 11. -0x6C 11. -0x2C 11. " [203] ,IRQ (DMAC completion ch.4) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 10. -0x6C 10. -0x2C 10. " [202] ,IRQ (DMAC completion ch.3) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 09. -0x6C 09. -0x2C 09. " [201] ,IRQ (DMAC completion ch.2) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 08. -0x6C 08. -0x2C 08. " [200] ,IRQ (DMAC completion ch.1) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 07. -0x6C 07. -0x2C 07. " [199] ,IRQ (DMAC completion ch.0) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 06. -0x6C 06. -0x2C 06. " [198] ,IRQ (DMA error) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 05. -0x6C 05. -0x2C 05. " [197] ,IRQ (ADC12B1 RCO) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 04. -0x6C 04. -0x2C 04. " [196] ,IRQ (ADC12B1 pulse detection function) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x14 03. -0x6C 03. -0x2C 03. " [195] ,IRQ (ADC12B1 group interrupt) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 02. -0x6C 02. -0x2C 02. " [194] ,IRQ (ADC12B1 conversion done) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 01. -0x6C 01. -0x2C 01. " [193] ,IRQ (ADC12B0 RCO) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x14 00. -0x6C 00. -0x2C 00. " [192] ,IRQ (ADC12B0 pulse detection function) software interrupt status bit" "No interrupt,Interrupt" line.long 0x18 "IRQSIS7_SET/CLR,Software Interrupt Status Register" setclrfld.long 0x18 13. -0x68 13. -0x28 13. " IRQSIS[235] ,IRQ (MFS ch.13 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 12. -0x68 12. -0x28 12. " [234] ,IRQ (MFS ch.12 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 09. -0x68 09. -0x28 09. " [233] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 08. -0x68 08. -0x28 08. " [232] ,IRQ (MFS ch.10 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 07. -0x68 07. -0x28 07. " [231] ,IRQ (MFS ch.9 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 06. -0x68 06. -0x28 06. " [230] ,IRQ (MFS ch.8 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 05. -0x68 05. -0x28 05. " [229] ,IRQ (MFS ch.7 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 04. -0x68 04. -0x28 04. " [228] ,IRQ (MFS ch.6 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" newline setclrfld.long 0x18 03. -0x68 03. -0x28 03. " [227] ,IRQ (MFS ch.5 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 02. -0x68 02. -0x28 02. " [226] ,IRQ (MFS ch.4 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 01. -0x68 01. -0x28 01. " [225] ,IRQ (MFS ch.3 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" setclrfld.long 0x18 00. -0x68 00. -0x28 00. " [224] ,IRQ (MFS ch.2 error (Tx/Rx error/status OR-ed) software interrupt status bit" "No interrupt,Interrupt" endif tree.end width 17. tree "IRC IRQ Channel Enable Registers" group.long 0xC00++0x03 line.long 0x00 "IRQCE0_SET/CLR,Channel Enable Setting Register 0" setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[31] ,IRQ (external interrupt request ch.7/ch.23) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [30] ,IRQ (external interrupt request ch.6/ch.22) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [29] ,IRQ (external interrupt request ch.5/ch.21) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [28] ,IRQ (external interrupt request ch.4/ch.20) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [27] ,IRQ (external interrupt request ch.3/ch.19) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [26] ,IRQ (external interrupt request ch.2/ch.18) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [25] ,IRQ (external interrupt request ch.1/ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [24] ,IRQ (external interrupt request ch.0/ch.16) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [20] ,IRQ (work FLASH RDY/write enable release/single bit error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [16] ,IRQ (IRC vector address RAM single bit error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [15] ,IRQ (CAN FD RAM(ch.0 to 4/ch.8) single bit error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [14] ,IRQ (system SRAM single bit error) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [10] ,IRQ (work FLASH hang up) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [8] ,IRQ (TCFLASH RDY/hng up/single bit error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [3] ,IRQ (SW-WDT pre-warning) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [2] ,IRQ (HW-WDT pre-warning) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [1] ,IRQ (system control status) channel enable setting bit" "Disabled,Enabled" sif cpuis("S6J351*") group.long 0xC04++0x1B line.long 0x00 "IRQCE1_SET/CLR,Channel Enable Setting Register 1" setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[63] ,IRQ (MFS TX ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [62] ,IRQ (MFS RX ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [61] ,IRQ (MFS TX ch.7) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [60] ,IRQ (MFS RX ch.7) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [59] ,IRQ (MFS TX ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [58] ,IRQ (MFS RX ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [57] ,IRQ (MFS TX ch.5) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [56] ,IRQ (MFS RX ch.5) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [55] ,IRQ (MFS TX ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [54] ,IRQ (MFS RX ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [53] ,IRQ (MFS TX ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [52] ,IRQ (MFS RX ch.3) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [51] ,IRQ (MFS TX ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [50] ,IRQ (MFS RX ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [49] ,IRQ (MFS TX ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [48] ,IRQ (MFS RX ch.1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [47] ,IRQ (MFS TX ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [46] ,IRQ (MFS RX ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [43] ,IRQ (CAN FD ch.3 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [42] ,IRQ (CAN FD ch.2 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [39] ,IRQ (external interrupt request ch.15/ch.31) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [38] ,IRQ (external interrupt request ch.14/ch.30) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [37] ,IRQ (external interrupt request ch.13/ch.29) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [36] ,IRQ (external interrupt request ch.12/ch.28) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [35] ,IRQ (external interrupt request ch.11/ch.27) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [34] ,IRQ (external interrupt request ch.10/ch.26) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [33] ,IRQ (external interrupt request ch.9/ch.25) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " [32] ,IRQ (external interrupt request ch.8/ch.24) channel enable setting bit" "Disabled,Enabled" line.long 0x04 "IRQCE2_SET/CLR,Channel Enable Setting Register 2" setclrfld.long 0x04 31. -0x7C 31. -0x3C 31. " IRQCE[95] ,IRQ (TCRAM diag) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 30. -0x7C 30. -0x3C 30. " [94] ,IRQ (DDR HSSPI TX) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 29. -0x7C 29. -0x3C 29. " [93] ,IRQ (DDR HSSPI RX) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 28. -0x7C 28. -0x3C 28. " [92] ,IRQ (SHE) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 27. -0x7C 27. -0x3C 27. " [91] ,IRQ (SHE error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 05. -0x7C 05. -0x3C 05. " [69] ,IRQ (MFS TX ch.11) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 04. -0x7C 04. -0x3C 04. " [68] ,IRQ (MFS RX ch.11) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 03. -0x7C 03. -0x3C 03. " [67] ,IRQ (MFS TX ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 02. -0x7C 02. -0x3C 02. " [66] ,IRQ (MFS RX ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 01. -0x7C 01. -0x3C 01. " [65] ,IRQ (MFS TX ch.9) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 00. -0x7C 00. -0x3C 00. " [64] ,IRQ (MFS RX ch.9) channel enable setting bit" "Disabled,Enabled" line.long 0x08 "IRQCE3_SET/CLR,Channel Enable Setting Register 3" setclrfld.long 0x08 27. -0x78 27. -0x38 27. " IRQCE[123] ,IRQ (base timer ch.31) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 26. -0x78 26. -0x38 26. " [122] ,IRQ (base timer ch.30) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 25. -0x78 25. -0x38 25. " [121] ,IRQ (base timer ch.29) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 24. -0x78 24. -0x38 24. " [120] ,IRQ (base timer ch.28) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 23. -0x78 23. -0x38 23. " [119] ,IRQ (base timer ch.27) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 22. -0x78 22. -0x38 22. " [118] ,IRQ (base timer ch.26) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 21. -0x78 21. -0x38 21. " [117] ,IRQ (base timer ch.25) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 20. -0x78 20. -0x38 20. " [116] ,IRQ (base timer ch.24/32/33/34/35) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 19. -0x78 19. -0x38 19. " [115] ,IRQ (base timer ch.19) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 18. -0x78 18. -0x38 18. " [114] ,IRQ (base timer ch.18) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 17. -0x78 17. -0x38 17. " [113] ,IRQ (base timer ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 16. -0x78 16. -0x38 16. " [112] ,IRQ (base timer ch.16) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 15. -0x78 15. -0x38 15. " [111] ,IRQ (base timer ch.15) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 14. -0x78 14. -0x38 14. " [110] ,IRQ (base timer ch.14) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 13. -0x78 13. -0x38 13. " [109] ,IRQ (base timer ch.13) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 12. -0x78 12. -0x38 12. " [108] ,IRQ (base timer ch.12/20/21/22/23) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 11. -0x78 11. -0x38 11. " [107] ,IRQ (base timer ch.7) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 10. -0x78 10. -0x38 10. " [106] ,IRQ (base timer ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 09. -0x78 09. -0x38 09. " [105] ,IRQ (base timer ch.5) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 08. -0x78 08. -0x38 08. " [104] ,IRQ (base timer ch.4) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 07. -0x78 07. -0x38 07. " [103] ,IRQ (base timer ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 06. -0x78 06. -0x38 06. " [102] ,IRQ (base timer ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 05. -0x78 05. -0x38 05. " [101] ,IRQ (base timer ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 04. -0x78 04. -0x38 04. " [100] ,IRQ (base timer ch.0/8/9/10/11) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 03. -0x78 03. -0x38 03. " [99] ,IRQ (CR CARIBRATION) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 02. -0x78 02. -0x38 02. " [98] ,IRQ (RTC) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 01. -0x78 01. -0x38 01. " [97] ,IRQ (global timer (compare clear interrupt)) channel enable setting bit" "Disabled,Enabled" line.long 0x0C "IRQCE4_SET/CLR,Channel Enable Setting Register 4" setclrfld.long 0x0C 30. -0x74 30. -0x34 30. " IRQCE[158] ,IRQ (FRT ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 29. -0x74 29. -0x34 29. " [157] ,IRQ (FRT ch.9) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 28. -0x74 28. -0x34 28. " [156] ,IRQ (FRT ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 26. -0x74 26. -0x34 26. " [154] ,IRQ (FRT ch.4) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 25. -0x74 25. -0x34 25. " [153] ,IRQ (FRT ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 24. -0x74 24. -0x34 24. " [152] ,IRQ (FRT ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 23. -0x74 23. -0x34 23. " [151] ,IRQ (FRT ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 22. -0x74 22. -0x34 22. " [150] ,IRQ (FRT ch.0) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " [149] ,IRQ (reload timer ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 20. -0x74 20. -0x34 20. " [148] ,IRQ (reload timer ch.16) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 19. -0x74 19. -0x34 19. " [147] ,IRQ (reload timer ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 18. -0x74 18. -0x34 18. " [146] ,IRQ (reload timer ch.2) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 17. -0x74 17. -0x34 17. " [145] ,IRQ (reload timer ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 16. -0x74 16. -0x34 16. " [144] ,IRQ (reload timer ch.0) channel enable setting bit" "Disabled,Enabled" line.long 0x10 "IRQCE5_SET/CLR,Channel Enable Setting Register 5" setclrfld.long 0x10 29. -0x70 29. -0x30 29. " IRQCE[189] ,IRQ (QPRC ch.9) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 28. -0x70 28. -0x30 28. " [188] ,IRQ (QPRC ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 27. -0x70 27. -0x30 27. " [187] ,IRQ (IRQ1 of output compare 10 (ch.21) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 26. -0x70 26. -0x30 26. " [186] ,IRQ1 of output compare 9 (ch.19) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 25. -0x70 25. -0x30 25. " [185] ,IRQ (IRQ1 of output compare 8 (ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 23. -0x70 23. -0x30 23. " [183] ,IRQ (IRQ1 of output compare 2 (ch.5) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 22. -0x70 22. -0x30 22. " [182] ,IRQ (IRQ1 of output compare 1 (ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 21. -0x70 21. -0x30 21. " [181] ,IRQ (IRQ1 of output compare 0 (ch.1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 20. -0x70 20. -0x30 20. " [180] ,IRQ (IRQ0 of output compare 10 (ch.20) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 19. -0x70 19. -0x30 19. " [179] ,IRQ (IRQ0 of output compare 9 (ch.18) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 18. -0x70 18. -0x30 18. " [178] ,IRQ (IRQ0 of output compare 8 (ch.16) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 16. -0x70 16. -0x30 16. " [176] ,IRQ (IRQ0 of output compare 2 (ch.4) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 15. -0x70 15. -0x30 15. " [175] ,IRQ (IRQ0 of output compare 1 (ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 14. -0x70 14. -0x30 14. " [174] ,IRQ (IRQ0 of output compare 0 (ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 13. -0x70 13. -0x30 13. " [173] ,IRQ (IRQ1 of input capture 10 (ch.21) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 12. -0x70 12. -0x30 12. " [172] ,IRQ (IRQ1 of input capture 9 (ch.19) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 11. -0x70 11. -0x30 11. " [171] ,IRQ (IRQ1 of input capture 8 (ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 10. -0x70 10. -0x30 10. " [170] ,IRQ (IRQ1 of input capture 2 (ch.5) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 09. -0x70 09. -0x30 09. " [169] ,IRQ (IRQ1 of input capture 1 (ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 08. -0x70 08. -0x30 08. " [168] ,IRQ (IRQ1 of input capture 0 (ch.1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 07. -0x70 07. -0x30 07. " [167] ,IRQ (IRQ0 of input capture 10 (ch.20) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 06. -0x70 06. -0x30 06. " [166] ,IRQ (IRQ0 of input capture 9 (ch.18) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 05. -0x70 05. -0x30 05. " [165] ,IRQ (IRQ0 of input capture 8 (ch.16) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 04. -0x70 04. -0x30 04. " [164] ,IRQ (IRQ0 of input capture 2 (ch.4) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 03. -0x70 03. -0x30 03. " [163] ,IRQ (IRQ0 of input capture 1 (ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 02. -0x70 02. -0x30 02. " [162] ,IRQ (IRQ0 of input capture 0 (ch.0) channel enable setting bit" "Disabled,Enabled" line.long 0x14 "IRQCE6_SET/CLR,70annel Enable Setting Register 6" setclrfld.long 0x14 31. -0x6C 31. -0x2C 31. " IRQCE[223] ,IRQ (MFS ch.1 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 30. -0x6C 30. -0x2C 30. " [222] ,IRQ (MFS ch.0 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 29. -0x6C 29. -0x2C 29. " [221] ,IRQ (PRGCRC) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 28. -0x6C 28. -0x2C 28. " [220] ,IRQ (CR5 performance monitor unit IRQ) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 27. -0x6C 27. -0x2C 27. " [219] ,IRQ (SCT Sub OSC IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 26. -0x6C 26. -0x2C 26. " [218] ,IRQ (SCT Main OSC IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 25. -0x6C 25. -0x2C 25. " [217] ,IRQ (SCT SRC IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 24. -0x6C 24. -0x2C 24. " [216] ,IRQ (SCT RC IRQ) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 23. -0x6C 23. -0x2C 23. " [215] ,IRQ (DMAC RLT (ch.0/1/2/3 OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 22. -0x6C 22. -0x2C 22. " [214] ,IRQ (DMAC completion ch.15) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 21. -0x6C 21. -0x2C 21. " [213] ,IRQ (DMAC completion ch.14) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " [212] ,IRQ (DMAC completion ch.13) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " [211] ,IRQ (DMAC completion ch.12) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " [210] ,IRQ (DMAC completion ch.11) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " [209] ,IRQ (DMAC completion ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " [208] ,IRQ (DMAC completion ch.9) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 15. -0x6C 15. -0x2C 15. " [207] ,IRQ (DMAC completion ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 14. -0x6C 14. -0x2C 14. " [206] ,IRQ (DMAC completion ch.7) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 13. -0x6C 13. -0x2C 13. " [205] ,IRQ (DMAC completion ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 12. -0x6C 12. -0x2C 12. " [204] ,IRQ (DMAC completion ch.5) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 11. -0x6C 11. -0x2C 11. " [203] ,IRQ (DMAC completion ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 10. -0x6C 10. -0x2C 10. " [202] ,IRQ (DMAC completion ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 09. -0x6C 09. -0x2C 09. " [201] ,IRQ (DMAC completion ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 08. -0x6C 08. -0x2C 08. " [200] ,IRQ (DMAC completion ch.1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 07. -0x6C 07. -0x2C 07. " [199] ,IRQ (DMAC completion ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 06. -0x6C 06. -0x2C 06. " [198] ,IRQ (DMA error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 05. -0x6C 05. -0x2C 05. " [197] ,IRQ (ADC12B1 RCO) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 04. -0x6C 04. -0x2C 04. " [196] ,IRQ (ADC12B1 pulse detection function) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 03. -0x6C 03. -0x2C 03. " [195] ,IRQ (ADC12B1 group interrupt) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 02. -0x6C 02. -0x2C 02. " [194] ,IRQ (ADC12B1 conversion done) channel enable setting bit" "Disabled,Enabled" line.long 0x18 "IRQCE7_SET/CLR,Channel Enable Setting Register 7" setclrfld.long 0x18 09. -0x68 09. -0x28 09. " IRQCE[233] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 08. -0x68 08. -0x28 08. " [232] ,IRQ (MFS ch.10 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 07. -0x68 07. -0x28 07. " [231] ,IRQ (MFS ch.9 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 06. -0x68 06. -0x28 06. " [230] ,IRQ (MFS ch.8 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 05. -0x68 05. -0x28 05. " [229] ,IRQ (MFS ch.7 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 04. -0x68 04. -0x28 04. " [228] ,IRQ (MFS ch.6 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 03. -0x68 03. -0x28 03. " [227] ,IRQ (MFS ch.5 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 02. -0x68 02. -0x28 02. " [226] ,IRQ (MFS ch.4 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 01. -0x68 01. -0x28 01. " [225] ,IRQ (MFS ch.3 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 00. -0x68 00. -0x28 00. " [224] ,IRQ (MFS ch.2 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" else group.long 0xC00++0x1B line.long 0x00 "IRQCE1_SET/CLR,Channel Enable Setting Register 1" setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE[63] ,IRQ (MFS TX ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [62] ,IRQ (MFS RX ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [61] ,IRQ (MFS TX ch.7) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [60] ,IRQ (MFS RX ch.7) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [59] ,IRQ (MFS TX ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [58] ,IRQ (MFS RX ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [57] ,IRQ (MFS TX ch.5) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [56] ,IRQ (MFS RX ch.5) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [55] ,IRQ (MFS TX ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [54] ,IRQ (MFS RX ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [53] ,IRQ (MFS TX ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [52] ,IRQ (MFS RX ch.3) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [51] ,IRQ (MFS TX ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [50] ,IRQ (MFS RX ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [49] ,IRQ (MFS TX ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [48] ,IRQ (MFS RX ch.1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [47] ,IRQ (MFS TX ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [46] ,IRQ (MFS RX ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 13. -0x80 13. -0x40 13. " [45] ,IRQ (CAN FD ch.8 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 12. -0x80 12. -0x40 12. " [44] ,IRQ (CAN FD ch.4 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [43] ,IRQ (CAN FD ch.3 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [42] ,IRQ (CAN FD ch.2 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [39] ,IRQ (external interrupt request ch.15/ch.31) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [38] ,IRQ (external interrupt request ch.14/ch.30) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [37] ,IRQ (external interrupt request ch.13/ch.29) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [36] ,IRQ (external interrupt request ch.12/ch.28) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [35] ,IRQ (external interrupt request ch.11/ch.27) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [34] ,IRQ (external interrupt request ch.10/ch.26) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [33] ,IRQ (external interrupt request ch.9/ch.25) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x00 00. -0x80 00. -0x40 00. " [32] ,IRQ (external interrupt request ch.8/ch.24) channel enable setting bit" "Disabled,Enabled" line.long 0x04 "IRQCE2_SET/CLR,Channel Enable Setting Register 2" setclrfld.long 0x04 31. -0x7C 31. -0x3C 31. " IRQCE[95] ,IRQ (TCRAM diag) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 28. -0x7C 28. -0x3C 28. " [92] ,IRQ (SHE) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 27. -0x7C 27. -0x3C 27. " [91] ,IRQ (SHE error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 09. -0x7C 09. -0x3C 09. " [73] ,IRQ (MFS TX ch.13) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 08. -0x7C 08. -0x3C 08. " [72] ,IRQ (MFS RX ch.13) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 07. -0x7C 07. -0x3C 07. " [71] ,IRQ (MFS TX ch.12) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 06. -0x7C 06. -0x3C 06. " [70] ,IRQ (MFS RX ch.12) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 05. -0x7C 05. -0x3C 05. " [69] ,IRQ (MFS TX ch.11) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 04. -0x7C 04. -0x3C 04. " [68] ,IRQ (MFS RX ch.11) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 03. -0x7C 03. -0x3C 03. " [67] ,IRQ (MFS TX ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 02. -0x7C 02. -0x3C 02. " [66] ,IRQ (MFS RX ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x04 01. -0x7C 01. -0x3C 01. " [65] ,IRQ (MFS TX ch.9) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x04 00. -0x7C 00. -0x3C 00. " [64] ,IRQ (MFS RX ch.9) channel enable setting bit" "Disabled,Enabled" line.long 0x08 "IRQCE3_SET/CLR,Channel Enable Setting Register 3" setclrfld.long 0x08 31. -0x78 31. -0x38 31. " IRQCE[127] ,IRQ (base timer ch.39) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 30. -0x78 30. -0x38 30. " [126] ,IRQ (base timer ch.38) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 29. -0x78 29. -0x38 29. " [125] ,IRQ (base timer ch.37) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 28. -0x78 28. -0x38 28. " [124] ,IRQ (base timer ch.36/44/45/46/47) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 27. -0x78 27. -0x38 27. " [123] ,IRQ (base timer ch.31) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 26. -0x78 26. -0x38 26. " [122] ,IRQ (base timer ch.30) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 25. -0x78 25. -0x38 25. " [121] ,IRQ (base timer ch.29) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 24. -0x78 24. -0x38 24. " [120] ,IRQ (base timer ch.28) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 23. -0x78 23. -0x38 23. " [119] ,IRQ (base timer ch.27) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 22. -0x78 22. -0x38 22. " [118] ,IRQ (base timer ch.26) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 21. -0x78 21. -0x38 21. " [117] ,IRQ (base timer ch.25) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 20. -0x78 20. -0x38 20. " [116] ,IRQ (base timer ch.24/32/33/34/35) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 19. -0x78 19. -0x38 19. " [115] ,IRQ (base timer ch.19) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 18. -0x78 18. -0x38 18. " [114] ,IRQ (base timer ch.18) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 17. -0x78 17. -0x38 17. " [113] ,IRQ (base timer ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 16. -0x78 16. -0x38 16. " [112] ,IRQ (base timer ch.16) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 15. -0x78 15. -0x38 15. " [111] ,IRQ (base timer ch.15) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 14. -0x78 14. -0x38 14. " [110] ,IRQ (base timer ch.14) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 13. -0x78 13. -0x38 13. " [109] ,IRQ (base timer ch.13) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 12. -0x78 12. -0x38 12. " [108] ,IRQ (base timer ch.12/20/21/22/23) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 11. -0x78 11. -0x38 11. " [107] ,IRQ (base timer ch.7) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 10. -0x78 10. -0x38 10. " [106] ,IRQ (base timer ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 09. -0x78 09. -0x38 09. " [105] ,IRQ (base timer ch.5) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 08. -0x78 08. -0x38 08. " [104] ,IRQ (base timer ch.4) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 07. -0x78 07. -0x38 07. " [103] ,IRQ (base timer ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 06. -0x78 06. -0x38 06. " [102] ,IRQ (base timer ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 05. -0x78 05. -0x38 05. " [101] ,IRQ (base timer ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 04. -0x78 04. -0x38 04. " [100] ,IRQ (base timer ch.0/8/9/10/11) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x08 03. -0x78 03. -0x38 03. " [99] ,IRQ (CR CARIBRATION) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 02. -0x78 02. -0x38 02. " [98] ,IRQ (RTC) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x08 01. -0x78 01. -0x38 01. " [97] ,IRQ (global timer (compare clear interrupt)) channel enable setting bit" "Disabled,Enabled" line.long 0x0C "IRQCE4_SET/CLR,Channel Enable Setting Register 4" setclrfld.long 0x0C 30. -0x74 30. -0x34 34. " IRQCE[158] ,IRQ (FRT ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 29. -0x74 29. -0x34 29. " [157] ,IRQ (FRT ch.9) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 28. -0x74 28. -0x34 28. " [156] ,IRQ (FRT ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 26. -0x74 26. -0x34 26. " [154] ,IRQ (FRT ch.4) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 25. -0x74 25. -0x34 25. " [153] ,IRQ (FRT ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 24. -0x74 24. -0x34 24. " [152] ,IRQ (FRT ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 23. -0x74 23. -0x34 23. " [151] ,IRQ (FRT ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 22. -0x74 22. -0x34 22. " [150] ,IRQ (FRT ch.0) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 21. -0x74 21. -0x34 21. " [149] ,IRQ (reload timer ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 20. -0x74 20. -0x34 20. " [148] ,IRQ (reload timer ch.16) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 19. -0x74 19. -0x34 19. " [147] ,IRQ (reload timer ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 18. -0x74 18. -0x34 18. " [146] ,IRQ (reload timer ch.2) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 17. -0x74 17. -0x34 17. " [145] ,IRQ (reload timer ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 16. -0x74 16. -0x34 16. " [144] ,IRQ (reload timer ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 15. -0x74 15. -0x34 15. " [143] ,IRQ (base timer ch.63) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 14. -0x74 14. -0x34 14. " [142] ,IRQ (base timer ch.62) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 13. -0x74 13. -0x34 13. " [141] ,IRQ (base timer ch.61) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 12. -0x74 12. -0x34 12. " [140] ,IRQ (base timer ch.60) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 11. -0x74 11. -0x34 11. " [139] ,IRQ (base timer ch.55) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 10. -0x74 10. -0x34 10. " [138] ,IRQ (base timer ch.54) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 09. -0x74 09. -0x34 09. " [137] ,IRQ (base timer ch.53) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 08. -0x74 08. -0x34 08. " [136] ,IRQ (base timer ch.52) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 07. -0x74 07. -0x34 07. " [135] ,IRQ (base timer ch.51) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 06. -0x74 06. -0x34 06. " [134] ,IRQ (base timer ch.50) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 05. -0x74 05. -0x34 05. " [133] ,IRQ (base timer ch.49) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 04. -0x74 04. -0x34 04. " [132] ,IRQ (base timer ch.48/56/57/58/59) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 03. -0x74 03. -0x34 03. " [131] ,IRQ (base timer ch.43) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 02. -0x74 02. -0x34 02. " [130] ,IRQ (base timer ch.42) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x0C 01. -0x74 01. -0x34 01. " [129] ,IRQ (base timer ch.41) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x0C 00. -0x74 00. -0x34 00. " [128] ,IRQ (base timer ch.40) channel enable setting bit" "Disabled,Enabled" line.long 0x10 "IRQCE5_SET/CLR,Channel Enable Setting Register 5" setclrfld.long 0x10 31. -0x70 31. -0x30 31. " IRQCE[191] ,IRQ (ADC12B0 group interrupt) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 30. -0x70 30. -0x30 30. " [190] ,IRQ (ADC12B0 conversion done) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 29. -0x70 29. -0x30 29. " [189] ,IRQ (QPRC ch.9) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 28. -0x70 28. -0x30 28. " [188] ,IRQ (QPRC ch.8) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 27. -0x70 27. -0x30 27. " [187] ,IRQ (IRQ1 of output compare 10 (ch.21) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 26. -0x70 26. -0x30 26. " [186] ,IRQ1 of output compare 9 (ch.19) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 25. -0x70 25. -0x30 25. " [185] ,IRQ (IRQ1 of output compare 8 (ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 23. -0x70 23. -0x30 23. " [183] ,IRQ (IRQ1 of output compare 2 (ch.5) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 22. -0x70 22. -0x30 22. " [182] ,IRQ (IRQ1 of output compare 1 (ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 21. -0x70 21. -0x30 21. " [181] ,IRQ (IRQ1 of output compare 0 (ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 20. -0x70 20. -0x30 20. " [180] ,IRQ (IRQ0 of output compare 10 (ch.20) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 19. -0x70 19. -0x30 19. " [179] ,IRQ (IRQ0 of output compare 9 (ch.18) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 18. -0x70 18. -0x30 18. " [178] ,IRQ (IRQ0 of output compare 8 (ch.16) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 16. -0x70 16. -0x30 16. " [176] ,IRQ (IRQ0 of output compare 2 (ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 15. -0x70 15. -0x30 15. " [175] ,IRQ (IRQ0 of output compare 1 (ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 14. -0x70 14. -0x30 14. " [174] ,IRQ (IRQ0 of output compare 0 (ch.0) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 13. -0x70 13. -0x30 13. " [173] ,IRQ (IRQ1 of input capture 10 (ch.21) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 12. -0x70 12. -0x30 12. " [172] ,IRQ (IRQ1 of input capture 9 (ch.19) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 11. -0x70 11. -0x30 11. " [171] ,IRQ (IRQ1 of input capture 8 (ch.17) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 10. -0x70 10. -0x30 10. " [170] ,IRQ (IRQ1 of input capture 2 (ch.5) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 09. -0x70 09. -0x30 09. " [169] ,IRQ (IRQ1 of input capture 1 (ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 08. -0x70 08. -0x30 08. " [168] ,IRQ (IRQ1 of input capture 0 (ch.1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 07. -0x70 07. -0x30 07. " [167] ,IRQ (IRQ0 of input capture 10 (ch.20) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 06. -0x70 06. -0x30 06. " [166] ,IRQ (IRQ0 of input capture 9 (ch.18) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x10 05. -0x70 05. -0x30 05. " [165] ,IRQ (IRQ0 of input capture 8 (ch.16) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 04. -0x70 04. -0x30 04. " [164] ,IRQ (IRQ0 of input capture 2 (ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 03. -0x70 03. -0x30 03. " [163] ,IRQ (IRQ0 of input capture 1 (ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x10 02. -0x70 02. -0x30 02. " [162] ,IRQ (IRQ0 of input capture 0 (ch.0) channel enable setting bit" "Disabled,Enabled" line.long 0x14 "IRQCE6_SET/CLR,Channel Enable Setting Register 6" setclrfld.long 0x14 31. -0x6C 31. -0x2C 31. " IRQCE[223] ,IRQ (MFS ch.1 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 30. -0x6C 30. -0x2C 30. " [222] ,IRQ (MFS ch.0 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 29. -0x6C 29. -0x2C 29. " [221] ,IRQ (PRGCRC) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 28. -0x6C 28. -0x2C 28. " [220] ,IRQ (CR5 performance monitor unit IRQ) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 27. -0x6C 27. -0x2C 27. " [219] ,IRQ (SCT Sub OSC IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 26. -0x6C 26. -0x2C 26. " [218] ,IRQ (SCT Main OSC IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 25. -0x6C 25. -0x2C 25. " [217] ,IRQ (SCT SRC IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 24. -0x6C 24. -0x2C 24. " [216] ,IRQ (SCT RC IRQ) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 23. -0x6C 23. -0x2C 23. " [215] ,IRQ (DMAC RLT (ch.0/1/2/3 OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 22. -0x6C 22. -0x2C 22. " [214] ,IRQ (DMAC completion ch.15) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 21. -0x6C 21. -0x2C 21. " [213] ,IRQ (DMAC completion ch.14) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 20. -0x6C 20. -0x2C 20. " [212] ,IRQ (DMAC completion ch.13) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 19. -0x6C 19. -0x2C 19. " [211] ,IRQ (DMAC completion ch.12) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 18. -0x6C 18. -0x2C 18. " [210] ,IRQ (DMAC completion ch.11) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 17. -0x6C 17. -0x2C 17. " [209] ,IRQ (DMAC completion ch.10) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 16. -0x6C 16. -0x2C 16. " [208] ,IRQ (DMAC completion ch.9) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 15. -0x6C 15. -0x2C 15. " [207] ,IRQ (DMAC completion ch.8) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 14. -0x6C 14. -0x2C 14. " [206] ,IRQ (DMAC completion ch.7) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 13. -0x6C 13. -0x2C 13. " [205] ,IRQ (DMAC completion ch.6) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 12. -0x6C 12. -0x2C 12. " [204] ,IRQ (DMAC completion ch.5) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 11. -0x6C 11. -0x2C 11. " [203] ,IRQ (DMAC completion ch.4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 10. -0x6C 10. -0x2C 10. " [202] ,IRQ (DMAC completion ch.3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 09. -0x6C 09. -0x2C 09. " [201] ,IRQ (DMAC completion ch.2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 08. -0x6C 08. -0x2C 08. " [200] ,IRQ (DMAC completion ch.1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 07. -0x6C 07. -0x2C 07. " [199] ,IRQ (DMAC completion ch.0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 06. -0x6C 06. -0x2C 06. " [198] ,IRQ (DMA error) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 05. -0x6C 05. -0x2C 05. " [197] ,IRQ (ADC12B1 RCO) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 04. -0x6C 04. -0x2C 04. " [196] ,IRQ (ADC12B1 pulse detection function) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x14 03. -0x6C 03. -0x2C 03. " [195] ,IRQ (ADC12B1 group interrupt) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 02. -0x6C 02. -0x2C 02. " [194] ,IRQ (ADC12B1 conversion done) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 01. -0x6C 01. -0x2C 01. " [193] ,IRQ (ADC12B0 RCO) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x14 00. -0x6C 00. -0x2C 00. " [192] ,IRQ (ADC12B0 pulse detection function) channel enable setting bit" "Disabled,Enabled" line.long 0x18 "IRQCE7_SET/CLR,Channel Enable Setting Register 7" setclrfld.long 0x18 30. -0x68 30. -0x28 30. " IRQCE[254] ,IRQ (MX_DATA_REQ_IRQ4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 29. -0x68 29. -0x28 29. " [253] ,IRQ (MX_DATA_REQ_IRQ3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 28. -0x68 28. -0x28 28. " [252] ,IRQ (MX_DATA_REQ_IRQ2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 27. -0x68 27. -0x28 27. " [251] ,IRQ (MX_DATA_REQ_IRQ1) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 26. -0x68 26. -0x28 26. " [250] ,IRQ (MX_DATA_REQ_IRQ0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 25. -0x68 25. -0x28 25. " [249] ,IRQ (MX_OVFL_IRQ4/MX_DMA_ERR_IRQ4) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 24. -0x68 24. -0x28 24. " [248] ,IRQ (MX_OVFL_IRQ3/MX_DMA_ERR_IRQ3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 23. -0x68 23. -0x28 23. " [247] ,IRQ (MX_OVFL_IRQ2/MX_DMA_ERR_IRQ2) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 22. -0x68 22. -0x28 22. " [246] ,IRQ (MX_OVFL_IRQ1/MX_DMA_ERR_IRQ1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 21. -0x68 21. -0x28 21. " [245] ,IRQ (MX_OVFL_IRQ0/MX_DMA_ERR_IRQ0) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 20. -0x68 20. -0x28 20. " [244] ,IRQ (MX_AHB_ERR_IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 19. -0x68 19. -0x28 19. " [243] ,IRQ (WG_END_IRQ4) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 18. -0x68 18. -0x28 18. " [242] ,IRQ (WG_END_IRQ3) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 17. -0x68 17. -0x28 17. " [241] ,IRQ (WG_END_IRQ2) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 16. -0x68 16. -0x28 16. " [240] ,IRQ (WG_END_IRQ1) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 15. -0x68 15. -0x28 15. " [239] ,IRQ (WG_END_IRQ0) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 14. -0x68 14. -0x28 14. " [238] ,IRQ (WG_AHB_ERR_IRQ) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 11. -0x68 11. -0x28 11. " [235] ,IRQ (MFS ch.13 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 10. -0x68 10. -0x28 10. " [234] ,IRQ (MFS ch.12 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 09. -0x68 09. -0x28 09. " [233] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 08. -0x68 08. -0x28 08. " [232] ,IRQ (MFS ch.10 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 07. -0x68 07. -0x28 07. " [231] ,IRQ (MFS ch.9 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 06. -0x68 06. -0x28 06. " [230] ,IRQ (MFS ch.8 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 05. -0x68 05. -0x28 05. " [229] ,IRQ (MFS ch.7 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 04. -0x68 04. -0x28 04. " [228] ,IRQ (MFS ch.6 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 03. -0x68 03. -0x28 03. " [227] ,IRQ (MFS ch.5 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 02. -0x68 02. -0x28 02. " [226] ,IRQ (MFS ch.4 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" setclrfld.long 0x18 01. -0x68 01. -0x28 01. " [225] ,IRQ (MFS ch.3 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" newline setclrfld.long 0x18 00. -0x68 00. -0x28 00. " [224] ,IRQ (MFS ch.2 error (Tx/Rx error/status OR-ed) channel enable setting bit" "Disabled,Enabled" endif tree.end newline group.long 0xC40++0x03 line.long 0x00 "NMIHC,IRC NMI Hold Clear Register" bitfld.long 0x00 0.--4. " NMIHCN ,Hold clear NMI channel number bits" "0,,,,4,5,6,7,8,,,,12,13,,15,,,18,,,,,,24,?..." sif cpuis("S6J351*") rgroup.long 0xC44++0x03 line.long 0x00 "NMIHS,IRC NMI Hold Status Register" bitfld.long 0x00 18. " NMISIS[18] ,NMI18 (TPU protection violation) hold status bit" "Not applied,Applied" bitfld.long 0x00 15. " [15] ,NMI15 (SHE MPU) hold status bit" "Not applied,Applied" bitfld.long 0x00 13. " [13] ,NMI13 (DMAC MPU #0 protection violation) hold status bit" "Not applied,Applied" newline bitfld.long 0x00 12. " [12] ,NMI12 (CAN-FD RAMs 2-bit ECC error detection) hold status bit" "Not applied,Applied" bitfld.long 0x00 09. " [9] ,NMI9 expand PLL CSV(OR-ed of all factors) hold status bit" "Not applied,Applied" bitfld.long 0x00 08. " [8] ,NMI8 (IRC 2-bit ECC err detection) hold status bit" "Not applied,Applied" bitfld.long 0x00 07. " [7] ,NMI7 (SW-WDT) hold status bit" "Not applied,Applied" newline bitfld.long 0x00 06. " [6] ,NMI6 (HW-WDT) hold status bit" "Not applied,Applied" bitfld.long 0x00 05. " [5] ,NMI5 (CSV/profile) hold status bit" "Not applied,Applied" bitfld.long 0x00 04. " [4] ,NMI4 LVDs IRQ hold status bit" "Not applied,Applied" bitfld.long 0x00 00. " [0] ,NMI0 (NMIX pin(Ext-IRC) hold status bit" "Not applied,Applied" else rgroup.long 0xC44++0x03 line.long 0x00 "NMIHS,IRC NMI Hold Status Register" bitfld.long 0x00 20. " NMISIS[24] ,NMI24 (bus diagnosis error detection) hold status bit" "Not applied,Applied" bitfld.long 0x00 18. " [18] ,NMI18 (TPU protection violation) hold status bit" "Not applied,Applied" bitfld.long 0x00 15. " [15] ,NMI15 (SHE MPU) hold status bit" "Not applied,Applied" bitfld.long 0x00 13. " [13] ,NMI13 (DMAC MPU #0 protection violation) hold status bit" "Not applied,Applied" newline bitfld.long 0x00 12. " [12] ,NMI12 (CAN-FD RAMs 2-bit ECC error detection) hold status bit" "Not applied,Applied" bitfld.long 0x00 09. " [9] ,NMI9 expand PLL CSV(OR-ed of all factors) hold status bit" "Not applied,Applied" bitfld.long 0x00 08. " [8] ,NMI8 (IRC 2-bit ECC err detection) hold status bit" "Not applied,Applied" bitfld.long 0x00 07. " [7] ,NMI7 (SW-WDT) hold status bit" "Not applied,Applied" newline bitfld.long 0x00 06. " [6] ,NMI6 (HW-WDT) hold status bit" "Not applied,Applied" bitfld.long 0x00 05. " [5] ,NMI5 (CSV/profile) hold status bit" "Not applied,Applied" bitfld.long 0x00 04. " [4] ,NMI4 LVDs IRQ hold status bit" "Not applied,Applied" bitfld.long 0x00 00. " [0] ,NMI0 (NMIX pin(Ext-IRC) hold status bit" "Not applied,Applied" endif group.long 0xC48++0x03 line.long 0x00 "IRQHC,IRC IRQ Hold Clear Register" hexmask.long.word 0x00 0.--8. 1. " IRQHCN ,Bits for IRQ channel number for which holds to be cleared" width 8. tree "IRQHS IRC IRQ Hold Status Register" rgroup.long 0xC50++0x03 line.long 0x00 "IRQHS0,Hold Status Register 0" bitfld.long 0x00 31. " IRQHS[31] ,IRQ (external interrupt request ch.7/ch.23) hold status bits" "Not applied,Applied" bitfld.long 0x00 30. " [30] ,IRQ (external interrupt request ch.6/ch.22) hold status bits" "Not applied,Applied" bitfld.long 0x00 29. " [29] ,IRQ (external interrupt request ch.5/ch.21) hold status bits" "Not applied,Applied" bitfld.long 0x00 28. " [28] ,IRQ (external interrupt request ch.4/ch.20) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 27. " [27] ,IRQ (external interrupt request ch.3/ch.19) hold status bits" "Not applied,Applied" bitfld.long 0x00 26. " [26] ,IRQ (external interrupt request ch.2/ch.18) hold status bits" "Not applied,Applied" bitfld.long 0x00 25. " [25] ,IRQ (external interrupt request ch.1/ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x00 24. " [24] ,IRQ (external interrupt request ch.0/ch.16) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 20. " [20] ,IRQ (work FLASH write completion) hold status bits" "Not applied,Applied" bitfld.long 0x00 16. " [16] ,IRQ (IRC vector address RAM single bit error) hold status bits" "Not applied,Applied" bitfld.long 0x00 15. " [15] ,IRQ (CAN FD RAM(ch.0 to 4/ch.8) single bit error) hold status bits" "Not applied,Applied" bitfld.long 0x00 14. " [14] ,IRQ (system SRAM single bit error) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 10. " [10] ,IRQ (work FLASH hang up) hold status bits" "Not applied,Applied" bitfld.long 0x00 08. " [8] ,IRQ (TCFLASH RDY/hang up/single bit error) hold status bits" "Not applied,Applied" bitfld.long 0x00 03. " [3] ,IRQ (SW-WDT pre-warning) hold status bits" "Not applied,Applied" bitfld.long 0x00 02. " [2] ,IRQ (HW-WDT pre-warning) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 01. " [1] ,IRQ (system control status) hold status bits" "Not applied,Applied" sif cpuis("S6J351*") rgroup.long 0xC54++0x1B line.long 0x00 "IRQHS1,Hold Status Register 1" bitfld.long 0x00 31. " IRQHS[63] ,IRQ (MFS TX ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x00 30. " [62] ,IRQ (MFS RX ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x00 29. " [61] ,IRQ (MFS TX ch.7) hold status bits" "Not applied,Applied" bitfld.long 0x00 28. " [60] ,IRQ (MFS RX ch.7) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 27. " [59] ,IRQ (MFS TX ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x00 26. " [58] ,IRQ (MFS RX ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x00 25. " [57] ,IRQ (MFS TX ch.5) hold status bits" "Not applied,Applied" bitfld.long 0x00 24. " [56] ,IRQ (MFS RX ch.5) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 23. " [55] ,IRQ (MFS TX ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x00 22. " [54] ,IRQ (MFS RX ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x00 21. " [53] ,IRQ (MFS TX ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x00 20. " [52] ,IRQ (MFS RX ch.3) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 19. " [51] ,IRQ (MFS TX ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x00 18. " [50] ,IRQ (MFS RX ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x00 17. " [49] ,IRQ (MFS TX ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x00 16. " [48] ,IRQ (MFS RX ch.1) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 15. " [47] ,IRQ (MFS TX ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x00 14. " [46] ,IRQ (MFS RX ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x00 11. " [43] ,IRQ (CAN FD ch.3 (OR-ed of all factors) hold status bits" "Not applied,Applied" bitfld.long 0x00 10. " [42] ,IRQ (CAN FD ch.2 (OR-ed of all factors) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 09. " [41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) hold status bits" "Not applied,Applied" bitfld.long 0x00 08. " [40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) hold status bits" "Not applied,Applied" bitfld.long 0x00 07. " [39] ,IRQ (external interrupt request ch.15/ch.31) hold status bits" "Not applied,Applied" bitfld.long 0x00 06. " [38] ,IRQ (external interrupt request ch.14/ch.30) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 05. " [37] ,IRQ (external interrupt request ch.13/ch.29) hold status bits" "Not applied,Applied" bitfld.long 0x00 04. " [36] ,IRQ (external interrupt request ch.12/ch.28) hold status bits" "Not applied,Applied" bitfld.long 0x00 03. " [35] ,IRQ (external interrupt request ch.11/ch.27) hold status bits" "Not applied,Applied" bitfld.long 0x00 02. " [34] ,IRQ (external interrupt request ch.10/ch.26) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 01. " [33] ,IRQ (external interrupt request ch.9/ch.25) hold status bits" "Not applied,Applied" bitfld.long 0x00 00. " [32] ,IRQ (external interrupt request ch.8/ch.24) hold status bits" "Not applied,Applied" line.long 0x04 "IRQHS2,Hold Status Register 2" bitfld.long 0x04 31. " IRQHS[95] ,IRQ (TCRAM diag) hold status bits" "Not applied,Applied" bitfld.long 0x04 30. " [94] ,IRQ (DDR HSSPI TX) hold status bits" "Not applied,Applied" bitfld.long 0x04 29. " [93] ,IRQ (DDR HSSPI RX) hold status bits" "Not applied,Applied" bitfld.long 0x04 28. " [92] ,IRQ (SHE) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 27. " [91] ,IRQ (SHE error) hold status bits" "Not applied,Applied" bitfld.long 0x04 05. " [69] ,IRQ (MFS TX ch.11) hold status bits" "Not applied,Applied" bitfld.long 0x04 04. " [68] ,IRQ (MFS RX ch.11) hold status bits" "Not applied,Applied" bitfld.long 0x04 03. " [67] ,IRQ (MFS TX ch.10) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 02. " [66] ,IRQ (MFS RX ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x04 01. " [65] ,IRQ (MFS TX ch.9) hold status bits" "Not applied,Applied" bitfld.long 0x04 00. " [64] ,IRQ (MFS RX ch.9) hold status bits" "Not applied,Applied" line.long 0x08 "IRQHS3,Hold Status Register 3" bitfld.long 0x08 27. " IRQHS[123] ,IRQ (base timer ch.31) hold status bits" "Not applied,Applied" bitfld.long 0x08 26. " [122] ,IRQ (base timer ch.30) hold status bits" "Not applied,Applied" bitfld.long 0x08 25. " [121] ,IRQ (base timer ch.29) hold status bits" "Not applied,Applied" bitfld.long 0x08 24. " [120] ,IRQ (base timer ch.28) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 23. " [119] ,IRQ (base timer ch.27) hold status bits" "Not applied,Applied" bitfld.long 0x08 22. " [118] ,IRQ (base timer ch.26) hold status bits" "Not applied,Applied" bitfld.long 0x08 21. " [117] ,IRQ (base timer ch.25) hold status bits" "Not applied,Applied" bitfld.long 0x08 20. " [116] ,IRQ (base timer ch.24/32/33/34/35) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 19. " [115] ,IRQ (base timer ch.19) hold status bits" "Not applied,Applied" bitfld.long 0x08 18. " [114] ,IRQ (base timer ch.18) hold status bits" "Not applied,Applied" bitfld.long 0x08 17. " [113] ,IRQ (base timer ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x08 16. " [112] ,IRQ (base timer ch.16) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 15. " [111] ,IRQ (base timer ch.15) hold status bits" "Not applied,Applied" bitfld.long 0x08 14. " [110] ,IRQ (base timer ch.14) hold status bits" "Not applied,Applied" bitfld.long 0x08 13. " [109] ,IRQ (base timer ch.13) hold status bits" "Not applied,Applied" bitfld.long 0x08 12. " [108] ,IRQ (base timer ch.12/20/21/22/23) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 11. " [107] ,IRQ (base timer ch.7) hold status bits" "Not applied,Applied" bitfld.long 0x08 10. " [106] ,IRQ (base timer ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x08 09. " [105] ,IRQ (base timer ch.5) hold status bits" "Not applied,Applied" bitfld.long 0x08 08. " [104] ,IRQ (base timer ch.4) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 07. " [103] ,IRQ (base timer ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x08 06. " [102] ,IRQ (base timer ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x08 05. " [101] ,IRQ (base timer ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x08 04. " [100] ,IRQ (base timer ch.0/8/9/10/11) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 03. " [99] ,IRQ (CR calibration) hold status bits" "Not applied,Applied" bitfld.long 0x08 02. " [98] ,IRQ (RTC) hold status bits" "Not applied,Applied" bitfld.long 0x08 01. " [97] ,IRQ (global timer (compare clear interrupt) hold status bits" "Not applied,Applied" line.long 0x0C "IRQHS4,Hold Status Register 4" bitfld.long 0x0C 30. " IRQHS[158] ,IRQ (FRT ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x0C 29. " [157] ,IRQ (FRT ch.9) hold status bits" "Not applied,Applied" bitfld.long 0x0C 28. " [156] ,IRQ (FRT ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x0C 26. " [154] ,IRQ (FRT ch.4) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 25. " [153] ,IRQ (FRT ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x0C 24. " [152] ,IRQ (FRT ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x0C 23. " [151] ,IRQ (FRT ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x0C 22. " [150] ,IRQ (FRT ch.0) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 21. " [149] ,IRQ (reload timer ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x0C 20. " [148] ,IRQ (reload timer ch.16) hold status bits" "Not applied,Applied" bitfld.long 0x0C 19. " [147] ,IRQ (reload timer ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x0C 18. " [146] ,IRQ (reload timer ch.2) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 17. " [145] ,IRQ (reload timer ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x0C 16. " [144] ,IRQ (reload timer ch.0) hold status bits" "Not applied,Applied" line.long 0x10 "IRQHS5,Hold Status Register 5" bitfld.long 0x10 29. " IRQHS[189] ,IRQ (QPRC ch.9) hold status bits" "Not applied,Applied" bitfld.long 0x10 28. " [188] ,IRQ (QPRC ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x10 27. " [187] ,IRQ (IRQ1 of output compare 10 (ch.21) hold status bits" "Not applied,Applied" bitfld.long 0x10 26. " [186] ,IRQ1 of output compare 9 (ch.19) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 25. " [185] ,IRQ (IRQ1 of output compare 8 (ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x10 23. " [183] ,IRQ (IRQ1 of output compare 2 (ch.5) hold status bits" "Not applied,Applied" bitfld.long 0x10 22. " [182] ,IRQ (IRQ1 of output compare 1 (ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x10 21. " [181] ,IRQ (IRQ1 of output compare 0 (ch.1) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 20. " [180] ,IRQ (IRQ0 of output compare 10 (ch.20) hold status bits" "Not applied,Applied" bitfld.long 0x10 19. " [179] ,IRQ (IRQ0 of output compare 9 (ch.18) hold status bits" "Not applied,Applied" bitfld.long 0x10 18. " [178] ,IRQ (IRQ0 of output compare 8 (ch.16) hold status bits" "Not applied,Applied" bitfld.long 0x10 16. " [176] ,IRQ (IRQ0 of output compare 2 (ch.4) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 15. " [175] ,IRQ (IRQ0 of output compare 1 (ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x10 14. " [174] ,IRQ (IRQ0 of output compare 0 (ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x10 13. " [173] ,IRQ (IRQ1 of input capture 10 (ch.21) hold status bits" "Not applied,Applied" bitfld.long 0x10 12. " [172] ,IRQ (IRQ1 of input capture 9 (ch.19) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 11. " [171] ,IRQ (IRQ1 of input capture 8 (ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x10 10. " [170] ,IRQ (IRQ1 of input capture 2 (ch.5) hold status bits" "Not applied,Applied" bitfld.long 0x10 09. " [169] ,IRQ (IRQ1 of input capture 1 (ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x10 08. " [168] ,IRQ (IRQ1 of input capture 0 (ch.1) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 07. " [167] ,IRQ (IRQ0 of input capture 10 (ch.20) hold status bits" "Not applied,Applied" bitfld.long 0x10 06. " [166] ,IRQ (IRQ0 of input capture 9 (ch.18) hold status bits" "Not applied,Applied" bitfld.long 0x10 05. " [165] ,IRQ (IRQ0 of input capture 8 (ch.16) hold status bits" "Not applied,Applied" bitfld.long 0x10 04. " [164] ,IRQ (IRQ0 of input capture 2 (ch.4) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 03. " [163] ,IRQ (RQ0 of input capture 1 (ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x10 02. " [162] ,IRQ (IRQ0 of input capture 0 (ch.0) hold status bits" "Not applied,Applied" line.long 0x14 "IRQHS6,Hold Status Register 6" bitfld.long 0x14 31. " IRQHS[223] ,IRQ (MFS ch.1 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x14 30. " [222] ,IRQ (MFS ch.0 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x14 29. " [221] ,IRQ (PRGCRC) hold status bits" "Not applied,Applied" bitfld.long 0x14 28. " [220] ,IRQ (CR5 performance monitor unit IRQ) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 27. " [219] ,IRQ (SCT sub OSC IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x14 26. " [218] ,IRQ (SCT main OSC IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x14 25. " [217] ,IRQ (SCT SRC IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x14 24. " [216] ,IRQ (SCT RC IRQ) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 23. " [215] ,IRQ (DMAC RLT (ch.0/1/2/3 OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x14 22. " [214] ,IRQ (DMAC completion ch.15) hold status bits" "Not applied,Applied" bitfld.long 0x14 21. " [213] ,IRQ (DMAC completion ch.14) hold status bits" "Not applied,Applied" bitfld.long 0x14 20. " [212] ,IRQ (DMAC completion ch.13) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 19. " [211] ,IRQ (DMAC completion ch.12) hold status bits" "Not applied,Applied" bitfld.long 0x14 18. " [210] ,IRQ (DMAC completion ch.11) hold status bits" "Not applied,Applied" bitfld.long 0x14 17. " [209] ,IRQ (DMAC completion ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x14 16. " [208] ,IRQ (DMAC completion ch.9) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 15. " [207] ,IRQ (DMAC completion ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x14 14. " [206] ,IRQ (DMAC completion ch.7) hold status bits" "Not applied,Applied" bitfld.long 0x14 13. " [205] ,IRQ (DMAC completion ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x14 12. " [204] ,IRQ (DMAC completion ch.5) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 11. " [203] ,IRQ (DMAC completion ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x14 10. " [202] ,IRQ (DMAC completion ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x14 09. " [201] ,IRQ (DMAC completion ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x14 08. " [200] ,IRQ (DMAC completion ch.1) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 07. " [199] ,IRQ (DMAC completion ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x14 06. " [198] ,IRQ (DMA error) hold status bits" "Not applied,Applied" bitfld.long 0x14 05. " [197] ,IRQ (ADC12B1 RCO) hold status bits" "Not applied,Applied" bitfld.long 0x14 04. " [196] ,IRQ (ADC12B1 pulse detection function) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 03. " [195] ,IRQ (ADC12B1 group interrupt) hold status bits" "Not applied,Applied" bitfld.long 0x14 02. " [194] ,IRQ (ADC12B1 conversion done) hold status bits" "Not applied,Applied" line.long 0x18 "IRQHS7,Hold Status Register 7" bitfld.long 0x18 09. " IRQHS[233] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 08. " [232] ,IRQ (MFS ch.10 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 07. " [231] ,IRQ (MFS ch.9 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 06. " [230] ,IRQ (MFS ch.8 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 05. " [229] ,IRQ (MFS ch.7 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 04. " [228] ,IRQ (MFS ch.6 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 03. " [227] ,IRQ (MFS ch.5 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 02. " [226] ,IRQ (MFS ch.4 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 01. " [225] ,IRQ (MFS ch.3 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 00. " [224] ,IRQ (MFS ch.2 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" else rgroup.long 0xC50++0x1B line.long 0x00 "IRQHS1,Hold Status Register 1" bitfld.long 0x00 31. " IRQHS[63] ,IRQ (MFS TX ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x00 30. " [62] ,IRQ (MFS RX ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x00 29. " [61] ,IRQ (MFS TX ch.7) hold status bits" "Not applied,Applied" bitfld.long 0x00 28. " [60] ,IRQ (MFS RX ch.7) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 27. " [59] ,IRQ (MFS TX ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x00 26. " [58] ,IRQ (MFS RX ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x00 25. " [57] ,IRQ (MFS TX ch.5) hold status bits" "Not applied,Applied" bitfld.long 0x00 24. " [56] ,IRQ (MFS RX ch.5) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 23. " [55] ,IRQ (MFS TX ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x00 22. " [54] ,IRQ (MFS RX ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x00 21. " [53] ,IRQ (MFS TX ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x00 20. " [52] ,IRQ (MFS RX ch.3) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 19. " [51] ,IRQ (MFS TX ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x00 18. " [50] ,IRQ (MFS RX ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x00 17. " [49] ,IRQ (MFS TX ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x00 16. " [48] ,IRQ (MFS RX ch.1) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 15. " [47] ,IRQ (MFS TX ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x00 14. " [46] ,IRQ (MFS RX ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x00 11. " [45] ,IRQ (CAN FD ch.8 (OR-ed of all factors) hold status bits" "Not applied,Applied" bitfld.long 0x00 10. " [44] ,IRQ (CAN FD ch.4 (OR-ed of all factors) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 11. " [43] ,IRQ (CAN FD ch.3 (OR-ed of all factors) hold status bits" "Not applied,Applied" bitfld.long 0x00 10. " [42] ,IRQ (CAN FD ch.2 (OR-ed of all factors) hold status bits" "Not applied,Applied" bitfld.long 0x00 09. " [41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) hold status bits" "Not applied,Applied" bitfld.long 0x00 08. " [40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 07. " [39] ,IRQ (external interrupt request ch.15/ch.31) hold status bits" "Not applied,Applied" bitfld.long 0x00 06. " [38] ,IRQ (external interrupt request ch.14/ch.30) hold status bits" "Not applied,Applied" bitfld.long 0x00 05. " [37] ,IRQ (external interrupt request ch.13/ch.29) hold status bits" "Not applied,Applied" bitfld.long 0x00 04. " [36] ,IRQ (external interrupt request ch.12/ch.28) hold status bits" "Not applied,Applied" newline bitfld.long 0x00 03. " [35] ,IRQ (external interrupt request ch.11/ch.27) hold status bits" "Not applied,Applied" bitfld.long 0x00 02. " [34] ,IRQ (external interrupt request ch.10/ch.26) hold status bits" "Not applied,Applied" bitfld.long 0x00 01. " [33] ,IRQ (external interrupt request ch.9/ch.25) hold status bits" "Not applied,Applied" bitfld.long 0x00 00. " [32] ,IRQ (external interrupt request ch.8/ch.24) hold status bits" "Not applied,Applied" line.long 0x04 "IRQHS2,Hold Status Register 2" bitfld.long 0x04 31. " IRQHS[95] ,IRQ (TCRAM diag) hold status bits" "Not applied,Applied" bitfld.long 0x04 28. " [92] ,IRQ (SHE) hold status bits" "Not applied,Applied" bitfld.long 0x04 27. " [91] ,IRQ (SHE error) hold status bits" "Not applied,Applied" bitfld.long 0x04 09. " [73] ,IRQ (MFS TX ch.13) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 08. " [72] ,IRQ (MFS RX ch.13) hold status bits" "Not applied,Applied" bitfld.long 0x04 07. " [71] ,IRQ (MFS TX ch.12) hold status bits" "Not applied,Applied" bitfld.long 0x04 06. " [70] ,IRQ (MFS RX ch.12) hold status bits" "Not applied,Applied" bitfld.long 0x04 05. " [69] ,IRQ (MFS TX ch.11) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 04. " [68] ,IRQ (MFS RX ch.11) hold status bits" "Not applied,Applied" bitfld.long 0x04 03. " [67] ,IRQ (MFS TX ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x04 02. " [66] ,IRQ (MFS RX ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x04 01. " [65] ,IRQ (MFS TX ch.9) hold status bits" "Not applied,Applied" newline bitfld.long 0x04 00. " [64] ,IRQ (MFS RX ch.9) hold status bits" "Not applied,Applied" line.long 0x08 "IRQHS3,Hold Status Register 3" bitfld.long 0x08 31. " IRQHS[127] ,IRQ (base timer ch.39) hold status bits" "Not applied,Applied" bitfld.long 0x08 30. " [126] ,IRQ (base timer ch.38) hold status bits" "Not applied,Applied" bitfld.long 0x08 29. " [125] ,IRQ (base timer ch.37) hold status bits" "Not applied,Applied" bitfld.long 0x08 28. " [124] ,IRQ (base timer ch.36/44/45/46/47) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 27. " [123] ,IRQ (base timer ch.31) hold status bits" "Not applied,Applied" bitfld.long 0x08 26. " [122] ,IRQ (base timer ch.30) hold status bits" "Not applied,Applied" bitfld.long 0x08 25. " [121] ,IRQ (base timer ch.29) hold status bits" "Not applied,Applied" bitfld.long 0x08 24. " [120] ,IRQ (base timer ch.28) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 23. " [119] ,IRQ (base timer ch.27) hold status bits" "Not applied,Applied" bitfld.long 0x08 22. " [118] ,IRQ (base timer ch.26) hold status bits" "Not applied,Applied" bitfld.long 0x08 21. " [117] ,IRQ (base timer ch.25) hold status bits" "Not applied,Applied" bitfld.long 0x08 20. " [116] ,IRQ (base timer ch.24/32/33/34/35) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 19. " [115] ,IRQ (base timer ch.19) hold status bits" "Not applied,Applied" bitfld.long 0x08 18. " [114] ,IRQ (base timer ch.18) hold status bits" "Not applied,Applied" bitfld.long 0x08 17. " [113] ,IRQ (base timer ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x08 16. " [112] ,IRQ (base timer ch.16) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 15. " [111] ,IRQ (base timer ch.15) hold status bits" "Not applied,Applied" bitfld.long 0x08 14. " [110] ,IRQ (base timer ch.14) hold status bits" "Not applied,Applied" bitfld.long 0x08 13. " [109] ,IRQ (base timer ch.13) hold status bits" "Not applied,Applied" bitfld.long 0x08 12. " [108] ,IRQ (base timer ch.12/20/21/22/23) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 11. " [107] ,IRQ (base timer ch.7) hold status bits" "Not applied,Applied" bitfld.long 0x08 10. " [106] ,IRQ (base timer ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x08 09. " [105] ,IRQ (base timer ch.5) hold status bits" "Not applied,Applied" bitfld.long 0x08 08. " [104] ,IRQ (base timer ch.4) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 07. " [103] ,IRQ (base timer ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x08 06. " [102] ,IRQ (base timer ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x08 05. " [101] ,IRQ (base timer ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x08 04. " [100] ,IRQ (base timer ch.0/8/9/10/11) hold status bits" "Not applied,Applied" newline bitfld.long 0x08 03. " [99] ,IRQ (CR calibration) hold status bits" "Not applied,Applied" bitfld.long 0x08 02. " [98] ,IRQ (RTC) hold status bits" "Not applied,Applied" bitfld.long 0x08 01. " [97] ,IRQ (global timer (compare clear interrupt) hold status bits" "Not applied,Applied" line.long 0x0C "IRQHS4,Hold Status Register 4" bitfld.long 0x0C 30. " IRQHS[158] ,IRQ (FRT ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x0C 29. " [157] ,IRQ (FRT ch.9) hold status bits" "Not applied,Applied" bitfld.long 0x0C 28. " [156] ,IRQ (FRT ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x0C 26. " [154] ,IRQ (FRT ch.4) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 25. " [153] ,IRQ (FRT ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x0C 24. " [152] ,IRQ (FRT ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x0C 23. " [151] ,IRQ (FRT ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x0C 22. " [150] ,IRQ (FRT ch.0) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 21. " [149] ,IRQ (reload timer ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x0C 20. " [148] ,IRQ (reload timer ch.16) hold status bits" "Not applied,Applied" bitfld.long 0x0C 19. " [147] ,IRQ (reload timer ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x0C 18. " [146] ,IRQ (reload timer ch.2) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 17. " [145] ,IRQ (reload timer ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x0C 16. " [144] ,IRQ (reload timer ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x0C 15. " [159] ,IRQ (base timer ch.63) hold status bits" "Not applied,Applied" bitfld.long 0x0C 14. " [159] ,IRQ (base timer ch.62) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 13. " [158] ,IRQ (base timer ch.61) hold status bits" "Not applied,Applied" bitfld.long 0x0C 12. " [157] ,IRQ (base timer ch.60) hold status bits" "Not applied,Applied" bitfld.long 0x0C 11. " [156] ,IRQ (base timer ch.55) hold status bits" "Not applied,Applied" bitfld.long 0x0C 10. " [154] ,IRQ (base timer ch.54) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 09. " [153] ,IRQ (base timer ch.53) hold status bits" "Not applied,Applied" bitfld.long 0x0C 08. " [152] ,IRQ (base timer ch.52) hold status bits" "Not applied,Applied" bitfld.long 0x0C 07. " [151] ,IRQ (base timer ch.51) hold status bits" "Not applied,Applied" bitfld.long 0x0C 06. " [150] ,IRQ (base timer ch.50) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 05. " [149] ,IRQ (base timer ch.49) hold status bits" "Not applied,Applied" bitfld.long 0x0C 04. " [148] ,IRQ (base timer ch.48/56/57/58/59) hold status bits" "Not applied,Applied" bitfld.long 0x0C 03. " [147] ,IRQ (base timer ch.43) hold status bits" "Not applied,Applied" bitfld.long 0x0C 02. " [146] ,IRQ (base timer ch.42) hold status bits" "Not applied,Applied" newline bitfld.long 0x0C 01. " [145] ,IRQ (base timer ch.41) hold status bits" "Not applied,Applied" bitfld.long 0x0C 00. " [144] ,IRQ (base timer ch.40) hold status bits" "Not applied,Applied" line.long 0x10 "IRQHS5,Hold Status Register 5" bitfld.long 0x10 31. " IRQHS[191] ,IRQ (ADC12B0 conversion done) hold status bits" "Not applied,Applied" bitfld.long 0x10 30. " [190] ,IRQ (ADC12B0 group interrupt) hold status bits" "Not applied,Applied" bitfld.long 0x10 29. " [189] ,IRQ (QPRC ch.9) hold status bits" "Not applied,Applied" bitfld.long 0x10 28. " [188] ,IRQ (QPRC ch.8) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 27. " [187] ,IRQ (IRQ1 of output compare 10 (ch.21) hold status bits" "Not applied,Applied" bitfld.long 0x10 26. " [186] ,IRQ1 of output compare 9 (ch.19) hold status bits" "Not applied,Applied" bitfld.long 0x10 25. " [185] ,IRQ (IRQ1 of output compare 8 (ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x10 23. " [183] ,IRQ (IRQ1 of output compare 2 (ch.5) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 22. " [182] ,IRQ (IRQ1 of output compare 1 (ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x10 21. " [181] ,IRQ (IRQ1 of output compare 0 (ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x10 20. " [180] ,IRQ (IRQ0 of output compare 10 (ch.20) hold status bits" "Not applied,Applied" bitfld.long 0x10 19. " [179] ,IRQ (IRQ0 of output compare 9 (ch.18) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 18. " [178] ,IRQ (IRQ0 of output compare 8 (ch.16) hold status bits" "Not applied,Applied" bitfld.long 0x10 16. " [176] ,IRQ (IRQ0 of output compare 2 (ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x10 15. " [175] ,IRQ (IRQ0 of output compare 1 (ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x10 14. " [174] ,IRQ (IRQ0 of output compare 0 (ch.0) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 13. " [173] ,IRQ (IRQ1 of input capture 10 (ch.21) hold status bits" "Not applied,Applied" bitfld.long 0x10 12. " [172] ,IRQ (IRQ1 of input capture 9 (ch.19) hold status bits" "Not applied,Applied" bitfld.long 0x10 11. " [171] ,IRQ (IRQ1 of input capture 8 (ch.17) hold status bits" "Not applied,Applied" bitfld.long 0x10 10. " [170] ,IRQ (IRQ1 of input capture 2 (ch.5) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 09. " [169] ,IRQ (IRQ1 of input capture 1 (ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x10 08. " [168] ,IRQ (IRQ1 of input capture 0 (ch.1) hold status bits" "Not applied,Applied" bitfld.long 0x10 07. " [167] ,IRQ (IRQ0 of input capture 10 (ch.20) hold status bits" "Not applied,Applied" bitfld.long 0x10 06. " [166] ,IRQ (IRQ0 of input capture 9 (ch.18) hold status bits" "Not applied,Applied" newline bitfld.long 0x10 05. " [165] ,IRQ (IRQ0 of input capture 8 (ch.16) hold status bits" "Not applied,Applied" bitfld.long 0x10 04. " [164] ,IRQ (IRQ0 of input capture 2 (ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x10 03. " [163] ,IRQ (RQ0 of input capture 1 (ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x10 02. " [162] ,IRQ (IRQ0 of input capture 0 (ch.0) hold status bits" "Not applied,Applied" line.long 0x14 "IRQHS6,Hold Status Register 6" bitfld.long 0x14 31. " IRQHS[223] ,IRQ (MFS ch.1 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x14 30. " [222] ,IRQ (MFS ch.0 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x14 29. " [221] ,IRQ (PRGCRC) hold status bits" "Not applied,Applied" bitfld.long 0x14 28. " [220] ,IRQ (CR5 performance monitor unit IRQ) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 27. " [219] ,IRQ (SCT sub OSC IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x14 26. " [218] ,IRQ (SCT main OSC IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x14 25. " [217] ,IRQ (SCT SRC IRQ) hold status bits" "Not applied,Applied" bitfld.long 0x14 24. " [216] ,IRQ (SCT RC IRQ) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 23. " [215] ,IRQ (DMAC RLT (ch.0/1/2/3 OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x14 22. " [214] ,IRQ (DMAC completion ch.15) hold status bits" "Not applied,Applied" bitfld.long 0x14 21. " [213] ,IRQ (DMAC completion ch.14) hold status bits" "Not applied,Applied" bitfld.long 0x14 20. " [212] ,IRQ (DMAC completion ch.13) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 19. " [211] ,IRQ (DMAC completion ch.12) hold status bits" "Not applied,Applied" bitfld.long 0x14 18. " [210] ,IRQ (DMAC completion ch.11) hold status bits" "Not applied,Applied" bitfld.long 0x14 17. " [209] ,IRQ (DMAC completion ch.10) hold status bits" "Not applied,Applied" bitfld.long 0x14 16. " [208] ,IRQ (DMAC completion ch.9) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 15. " [207] ,IRQ (DMAC completion ch.8) hold status bits" "Not applied,Applied" bitfld.long 0x14 14. " [206] ,IRQ (DMAC completion ch.7) hold status bits" "Not applied,Applied" bitfld.long 0x14 13. " [205] ,IRQ (DMAC completion ch.6) hold status bits" "Not applied,Applied" bitfld.long 0x14 12. " [204] ,IRQ (DMAC completion ch.5) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 11. " [203] ,IRQ (DMAC completion ch.4) hold status bits" "Not applied,Applied" bitfld.long 0x14 10. " [202] ,IRQ (DMAC completion ch.3) hold status bits" "Not applied,Applied" bitfld.long 0x14 09. " [201] ,IRQ (DMAC completion ch.2) hold status bits" "Not applied,Applied" bitfld.long 0x14 08. " [200] ,IRQ (DMAC completion ch.1) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 07. " [199] ,IRQ (DMAC completion ch.0) hold status bits" "Not applied,Applied" bitfld.long 0x14 06. " [198] ,IRQ (DMA error) hold status bits" "Not applied,Applied" bitfld.long 0x14 05. " [197] ,IRQ (ADC12B1 RCO) hold status bits" "Not applied,Applied" bitfld.long 0x14 04. " [196] ,IRQ (ADC12B1 pulse detection function) hold status bits" "Not applied,Applied" newline bitfld.long 0x14 03. " [195] ,IRQ (ADC12B1 group interrupt) hold status bits" "Not applied,Applied" bitfld.long 0x14 02. " [194] ,IRQ (ADC12B1 conversion done) hold status bits" "Not applied,Applied" bitfld.long 0x14 01. " [193] ,IRQ (ADC12B0 RCO) hold status bits" "Not applied,Applied" bitfld.long 0x14 00. " [192] ,IRQ (ADC12B0 pulse detection function) hold status bits" "Not applied,Applied" line.long 0x18 "IRQHS7,Hold Status Register 7" bitfld.long 0x18 11. " IRQHS[235] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 10. " [234] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 09. " [233] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 08. " [232] ,IRQ (MFS ch.10 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 07. " [231] ,IRQ (MFS ch.9 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 06. " [230] ,IRQ (MFS ch.8 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 05. " [229] ,IRQ (MFS ch.7 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 04. " [228] ,IRQ (MFS ch.6 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" newline bitfld.long 0x18 03. " [227] ,IRQ (MFS ch.5 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 02. " [226] ,IRQ (MFS ch.4 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 01. " [225] ,IRQ (MFS ch.3 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" bitfld.long 0x18 00. " [224] ,IRQ (MFS ch.2 error (Tx/Rx error/status OR-ed) hold status bits" "Not applied,Applied" endif tree.end newline group.long 0xC90++0x03 line.long 0x00 "IRQPLM,Priority Level Mask Register" bitfld.long 0x00 0.--5. " IRQPLM ,IRQ priority level mask bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC98++0x03 line.long 0x00 "CSR,Control/Status Register" rbitfld.long 0x00 16. " LST ,Interrupt controller lock status" "Unlocked,Locked" bitfld.long 0x00 0. " IRQEN ,IRQ processing block enable/disable setting bit" "Disabled,Enabled" sif cpuis("S6J351*") rgroup.long 0xCA8++0x07 line.long 0x00 "NMIRS,NMI RAW Status Register" bitfld.long 0x00 18. " NMIRS[18] ,RAW status bit for NMI (TPU protection violation)" "No interrupt,Interrupt" bitfld.long 0x00 15. " [15] ,RAW status bit for NMI (SHE MPU)" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,RAW status bit for NMI (DMAC MPU #0 protection violation)" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " [12] ,RAW status bit for NMI (CAN-FD RAMs 2-bit ECC error detection)" "No interrupt,Interrupt" bitfld.long 0x00 09. " [9] ,RAW status bit for NMI (expand PLL CSV(OR-ed of all factors)" "No interrupt,Interrupt" bitfld.long 0x00 08. " [8] ,RAW status bit for NMI (IRC 2-bit ECC err detection)" "No interrupt,Interrupt" bitfld.long 0x00 07. " [7] ,RAW status bit for NMI (SW-WDT)" "No interrupt,Interrupt" newline bitfld.long 0x00 06. " [6] ,RAW status bit for NMI (HW-WDT)" "No interrupt,Interrupt" bitfld.long 0x00 05. " [5] ,RAW status bit for NMI (CSV/profile)" "No interrupt,Interrupt" bitfld.long 0x00 04. " [4] ,RAW status bit for NMI (LVDs IRQ)" "No interrupt,Interrupt" bitfld.long 0x00 00. " [0] ,RAW status bit for NMI (NMIX pin(Ext-IRC)" "No interrupt,Interrupt" line.long 0x04 "NIMPS,NMI Preprocessed Status Register" bitfld.long 0x04 18. " NMIPS[18] ,Preprocessed status bits for (TPU protection violation)" "No interrupt,Interrupt" bitfld.long 0x04 15. " [15] ,Preprocessed status bits for (SHE MPU)" "No interrupt,Interrupt" bitfld.long 0x04 13. " [13] ,Preprocessed status bits for (DMAC MPU #0 protection violation)" "No interrupt,Interrupt" newline bitfld.long 0x04 12. " [12] ,Preprocessed status bits for (CAN-FD RAMs 2-bit ECC error detection)" "No interrupt,Interrupt" bitfld.long 0x04 09. " [9] ,Preprocessed status bits for (expand PLL CSV(OR-ed of all factors)" "No interrupt,Interrupt" bitfld.long 0x04 08. " [8] ,Preprocessed status bits for (IRC 2-bit ECC err detection)" "No interrupt,Interrupt" bitfld.long 0x04 07. " [7] ,Preprocessed status bits for (SW-WDT)" "No interrupt,Interrupt" newline bitfld.long 0x04 06. " [6] ,Preprocessed status bits for (HW-WDT)" "No interrupt,Interrupt" bitfld.long 0x04 05. " [5] ,Preprocessed status bits for (CSV/profile)" "No interrupt,Interrupt" bitfld.long 0x04 04. " [4] ,Preprocessed status bits for (LVDs IRQ)" "No interrupt,Interrupt" bitfld.long 0x04 00. " [0] ,Preprocessed status bits for (NMIX pin(Ext-IRC)" "No interrupt,Interrupt" else rgroup.long 0xCA8++0x07 line.long 0x00 "NMIRS,NMI RAW Status Register" bitfld.long 0x00 24. " NMIRS[24] ,RAW status bit for NMI (bus diagnosis error detection)" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,RAW status bit for NMI (TPU protection violation)" "No interrupt,Interrupt" bitfld.long 0x00 15. " [15] ,RAW status bit for NMI (SHE MPU)" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,RAW status bit for NMI (DMAC MPU #0 protection violation)" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " [12] ,RAW status bit for NMI (CAN-FD RAMs 2-bit ECC error detection)" "No interrupt,Interrupt" bitfld.long 0x00 09. " [9] ,RAW status bit for NMI (expand PLL CSV(OR-ed of all factors)" "No interrupt,Interrupt" bitfld.long 0x00 08. " [8] ,RAW status bit for NMI (IRC 2-bit ECC err detection)" "No interrupt,Interrupt" bitfld.long 0x00 07. " [7] ,RAW status bit for NMI (SW-WDT)" "No interrupt,Interrupt" newline bitfld.long 0x00 06. " [6] ,RAW status bit for NMI (HW-WDT)" "No interrupt,Interrupt" bitfld.long 0x00 05. " [5] ,RAW status bit for NMI (CSV/profile)" "No interrupt,Interrupt" bitfld.long 0x00 04. " [4] ,RAW status bit for NMI (LVDs IRQ)" "No interrupt,Interrupt" bitfld.long 0x00 00. " [0] ,RAW status bit for NMI (NMIX pin(Ext-IRC)" "No interrupt,Interrupt" line.long 0x04 "NIMPS,NMI Preprocessed Status Register" bitfld.long 0x04 24. " NMIPS[24] ,Preprocessed status bits for (bus diagnosis error detection)" "No interrupt,Interrupt" bitfld.long 0x04 18. " [18] ,Preprocessed status bits for (TPU protection violation)" "No interrupt,Interrupt" bitfld.long 0x04 15. " [15] ,Preprocessed status bits for (SHE MPU)" "No interrupt,Interrupt" bitfld.long 0x04 13. " [13] ,Preprocessed status bits for (DMAC MPU #0 protection violation)" "No interrupt,Interrupt" newline bitfld.long 0x04 12. " [12] ,Preprocessed status bits for (CAN-FD RAMs 2-bit ECC error detection)" "No interrupt,Interrupt" bitfld.long 0x04 09. " [9] ,Preprocessed status bits for (expand PLL CSV(OR-ed of all factors)" "No interrupt,Interrupt" bitfld.long 0x04 08. " [8] ,Preprocessed status bits for (IRC 2-bit ECC err detection)" "No interrupt,Interrupt" bitfld.long 0x04 07. " [7] ,Preprocessed status bits for (SW-WDT)" "No interrupt,Interrupt" newline bitfld.long 0x04 06. " [6] ,Preprocessed status bits for (HW-WDT)" "No interrupt,Interrupt" bitfld.long 0x04 05. " [5] ,Preprocessed status bits for (CSV/profile)" "No interrupt,Interrupt" bitfld.long 0x04 04. " [4] ,Preprocessed status bits for (LVDs IRQ)" "No interrupt,Interrupt" bitfld.long 0x04 00. " [0] ,Preprocessed status bits for (NMIX pin(Ext-IRC)" "No interrupt,Interrupt" endif width 8. tree "IRQRS IRC IRQ RWA Status Register" rgroup.long 0xCB0++0x03 line.long 0x00 "IRQRS0,RAW Status Register 0" bitfld.long 0x00 31. " IRQRS[31] ,IRQ (external interrupt request ch.7/ch.23) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,IRQ (external interrupt request ch.6/ch.22) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,IRQ (external interrupt request ch.5/ch.21) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,IRQ (external interrupt request ch.4/ch.20) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,IRQ (external interrupt request ch.3/ch.19) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,IRQ (external interrupt request ch.2/ch.18) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,IRQ (external interrupt request ch.1/ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,IRQ (external interrupt request ch.0/ch.16) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 20. " [20] ,IRQ (work FLASH RDY/rite enable release/single bit error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,IRQ (IRC vector address RAM single bit error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 15. " [15] ,IRQ (CAN FD RAM(ch.0 to 4/ch.8) single bit error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,IRQ (system SRAM single bit error) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 10. " [10] ,IRQ (work FLASH hang up) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 08. " [8] ,IRQ (TCFLASH RDY/hang up/single bit error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 03. " [3] ,IRQ (SW-WDT pre-warning) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 02. " [2] ,IRQ (HW-WDT pre-warning) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 01. " [1] ,IRQ (system control status) RAW status bits" "No interrupt,Interrupt" sif cpuis("S6J351*") rgroup.long 0xCB4++0x1B line.long 0x00 "IRQRS1,RAW Status Register 1" bitfld.long 0x00 31. " IRQRS[63] ,IRQ (MFS TX ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 30. " [62] ,IRQ (MFS RX ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 29. " [61] ,IRQ (MFS TX ch.7) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 28. " [60] ,IRQ (MFS RX ch.7) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [59] ,IRQ (MFS TX ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 26. " [58] ,IRQ (MFS RX ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 25. " [57] ,IRQ (MFS TX ch.5) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 24. " [56] ,IRQ (MFS RX ch.5) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [55] ,IRQ (MFS TX ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 22. " [54] ,IRQ (MFS RX ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 21. " [53] ,IRQ (MFS TX ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 20. " [52] ,IRQ (MFS RX ch.3) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [51] ,IRQ (MFS TX ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 18. " [50] ,IRQ (MFS RX ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 17. " [49] ,IRQ (MFS TX ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 16. " [48] ,IRQ (MFS RX ch.1) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [47] ,IRQ (MFS TX ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 14. " [46] ,IRQ (MFS RX ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 11. " [43] ,IRQ (CAN FD ch.3 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 10. " [42] ,IRQ (CAN FD ch.2 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 09. " [41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 08. " [40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 07. " [39] ,IRQ (external interrupt request ch.15/ch.31) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 06. " [38] ,IRQ (external interrupt request ch.14/ch.30) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 05. " [37] ,IRQ (external interrupt request ch.13/ch.29) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 04. " [36] ,IRQ (external interrupt request ch.12/ch.28) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 03. " [35] ,IRQ (external interrupt request ch.11/ch.27) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 02. " [34] ,IRQ (external interrupt request ch.10/ch.26) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 01. " [33] ,IRQ (external interrupt request ch.9/ch.25) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 00. " [32] ,IRQ (external interrupt request ch.8/ch.24) RAW status bits" "No interrupt,Interrupt" line.long 0x04 "IRQRS2,RAW Status Register 2" bitfld.long 0x04 31. " IRQRS[95] ,IRQ (TCRAM diag) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 30. " [94] ,IRQ (DDR HSSPI TX) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 29. " [93] ,IRQ (DDR HSSPI RX) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 28. " [92] ,IRQ (SHE) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 27. " [91] ,IRQ (SHE error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 05. " [69] ,IRQ (MFS TX ch.11) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 04. " [68] ,IRQ (MFS RX ch.11) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 03. " [67] ,IRQ (MFS TX ch.10) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 02. " [66] ,IRQ (MFS RX ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 01. " [65] ,IRQ (MFS TX ch.9) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 00. " [64] ,IRQ (MFS RX ch.9) RAW status bits" "No interrupt,Interrupt" line.long 0x08 "IRQRS3,RAW Status Register 3" bitfld.long 0x08 27. " IRQRS[123] ,IRQ (base timer ch.31) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 26. " [122] ,IRQ (base timer ch.30) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 25. " [121] ,IRQ (base timer ch.29) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 24. " [120] ,IRQ (base timer ch.28) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 23. " [119] ,IRQ (base timer ch.27) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 22. " [118] ,IRQ (base timer ch.26) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 21. " [117] ,IRQ (base timer ch.25) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 20. " [116] ,IRQ (base timer ch.24/32/33/34/35) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 19. " [115] ,IRQ (base timer ch.19) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 18. " [114] ,IRQ (base timer ch.18) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 17. " [113] ,IRQ (base timer ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 16. " [112] ,IRQ (base timer ch.16) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 15. " [111] ,IRQ (base timer ch.15) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 14. " [110] ,IRQ (base timer ch.14) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 13. " [109] ,IRQ (base timer ch.13) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 12. " [108] ,IRQ (base timer ch.12/20/21/22/23) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 11. " [107] ,IRQ (base timer ch.7) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 10. " [106] ,IRQ (base timer ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 09. " [105] ,IRQ (base timer ch.5) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 08. " [104] ,IRQ (base timer ch.4) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 07. " [103] ,IRQ (base timer ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 06. " [102] ,IRQ (base timer ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 05. " [101] ,IRQ (base timer ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 04. " [100] ,IRQ (base timer ch.0/8/9/10/11) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 03. " [99] ,IRQ (CR calibration) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 02. " [98] ,IRQ (RTC) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 01. " [97] ,IRQ (global timer (compare clear interrupt) RAW status bits" "No interrupt,Interrupt" line.long 0x0C "IRQRS4,RAW Status Register 4" bitfld.long 0x0C 30. " IRQRS[158] ,IRQ (FRT ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 29. " [157] ,IRQ (FRT ch.9) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 28. " [156] ,IRQ (FRT ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 26. " [154] ,IRQ (FRT ch.4) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 25. " [153] ,IRQ (FRT ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 24. " [152] ,IRQ (FRT ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 23. " [151] ,IRQ (FRT ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 22. " [150] ,IRQ (FRT ch.0) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 21. " [149] ,IRQ (reload timer ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 20. " [148] ,IRQ (reload timer ch.16) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 19. " [147] ,IRQ (reload timer ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 18. " [146] ,IRQ (reload timer ch.2) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 17. " [145] ,IRQ (reload timer ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 16. " [144] ,IRQ (reload timer ch.0) RAW status bits" "No interrupt,Interrupt" line.long 0x10 "IRQRS5,RAW Status Register 5" bitfld.long 0x10 29. " IRQRS[189] ,IRQ (QPRC ch.9) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 28. " [188] ,IRQ (QPRC ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 27. " [187] ,IRQ (IRQ1 of output compare 10 (ch.21) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 26. " [186] ,IRQ (IRQ1 of output compare 9 (ch.19) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 25. " [185] ,IRQ (IRQ1 of output compare 8 (ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 23. " [183] ,IRQ (IRQ1 of output compare 2 (ch.5) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 22. " [182] ,IRQ (IRQ1 of output compare 1 (ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 21. " [181] ,IRQ (IRQ1 of output compare 0 (ch.1) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 20. " [180] ,IRQ (IRQ0 of output compare 10 (ch.20) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 19. " [179] ,IRQ (IRQ0 of output compare 9 (ch.18) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 18. " [178] ,IRQ (IRQ0 of output compare 8 (ch.16) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 16. " [176] ,IRQ (IRQ0 of output compare 2 (ch.4) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 15. " [175] ,IRQ (IRQ0 of output compare 1 (ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 14. " [174] ,IRQ (IRQ0 of output compare 0 (ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 13. " [173] ,IRQ (IRQ1 of input capture 10 (ch.21) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 12. " [172] ,IRQ (IRQ1 of input capture 9 (ch.19) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 11. " [171] ,IRQ (IRQ1 of input capture 8 (ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 10. " [170] ,IRQ (IRQ1 of input capture 2 (ch.5) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 09. " [169] ,IRQ (IRQ1 of input capture 1 (ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 08. " [168] ,IRQ (IRQ1 of input capture 0 (ch.1) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 07. " [167] ,IRQ (IRQ0 of input capture 10 (ch.20) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 06. " [166] ,IRQ (IRQ0 of input capture 9 (ch.18) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 05. " [165] ,IRQ (IRQ0 of input capture 8 (ch.16) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 04. " [164] ,IRQ (IRQ0 of input capture 2 (ch.4) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 03. " [163] ,IRQ (RQ0 of input capture 1 (ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 02. " [162] ,IRQ (IRQ0 of input capture 0 (ch.0) RAW status bits" "No interrupt,Interrupt" line.long 0x14 "IRQRS6,RAW Status Register 6" bitfld.long 0x14 31. " IRQRS[223] ,IRQ (MFS ch.1 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 30. " [222] ,IRQ (MFS ch.0 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 29. " [221] ,IRQ (PRGCRC) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 28. " [220] ,IRQ (CR5 performance monitor unit IRQ) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 27. " [219] ,IRQ (SCT sub OSC IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 26. " [218] ,IRQ (SCT main OSC IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 25. " [217] ,IRQ (SCT SRC IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 24. " [216] ,IRQ (SCT RC IRQ) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 23. " [215] ,IRQ (DMAC RLT (ch.0/1/2/3 OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 22. " [214] ,IRQ (DMAC completion ch.15) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 21. " [213] ,IRQ (DMAC completion ch.14) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 20. " [212] ,IRQ (DMAC completion ch.13) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 19. " [211] ,IRQ (DMAC completion ch.12) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 18. " [210] ,IRQ (DMAC completion ch.11) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 17. " [209] ,IRQ (DMAC completion ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 16. " [208] ,IRQ (DMAC completion ch.9) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 15. " [207] ,IRQ (DMAC completion ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 14. " [206] ,IRQ (DMAC completion ch.7) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 13. " [205] ,IRQ (DMAC completion ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 12. " [204] ,IRQ (DMAC completion ch.5) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 11. " [203] ,IRQ (DMAC completion ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 10. " [202] ,IRQ (DMAC completion ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 09. " [201] ,IRQ (DMAC completion ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 08. " [200] ,IRQ (DMAC completion ch.1) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 07. " [199] ,IRQ (DMAC completion ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 06. " [198] ,IRQ (DMA error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 05. " [197] ,IRQ (ADC12B1 RCO) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 04. " [196] ,IRQ (ADC12B1 pulse detection function) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 03. " [195] ,IRQ (ADC12B1 group interrupt) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 02. " [194] ,IRQ (ADC12B1 conversion done) RAW status bits" "No interrupt,Interrupt" line.long 0x18 "IRQRS7,RAW Status Register 7" bitfld.long 0x18 09. " IRQRS[233] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 08. " [232] ,IRQ (MFS ch.10 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 07. " [231] ,IRQ (MFS ch.9 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 06. " [230] ,IRQ (MFS ch.8 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 05. " [229] ,IRQ (MFS ch.7 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 04. " [228] ,IRQ (MFS ch.6 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 03. " [227] ,IRQ (MFS ch.5 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 02. " [226] ,IRQ (MFS ch.4 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 01. " [225] ,IRQ (MFS ch.3 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 00. " [224] ,IRQ (MFS ch.2 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" else rgroup.long 0xCB4++0x1B line.long 0x00 "IRQRS1,RAW Status Register 1" bitfld.long 0x00 31. " IRQRS[63] ,IRQ (MFS TX ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 30. " [62] ,IRQ (MFS RX ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 29. " [61] ,IRQ (MFS TX ch.7) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 28. " [60] ,IRQ (MFS RX ch.7) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [59] ,IRQ (MFS TX ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 26. " [58] ,IRQ (MFS RX ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 25. " [57] ,IRQ (MFS TX ch.5) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 24. " [56] ,IRQ (MFS RX ch.5) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [55] ,IRQ (MFS TX ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 22. " [54] ,IRQ (MFS RX ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 21. " [53] ,IRQ (MFS TX ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 20. " [52] ,IRQ (MFS RX ch.3) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [51] ,IRQ (MFS TX ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 18. " [50] ,IRQ (MFS RX ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 17. " [49] ,IRQ (MFS TX ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 16. " [48] ,IRQ (MFS RX ch.1) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [47] ,IRQ (MFS TX ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 14. " [46] ,IRQ (MFS RX ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 13. " [45] ,IRQ (CAN FD ch.8 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 12. " [44] ,IRQ (CAN FD ch.4 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [43] ,IRQ (CAN FD ch.3 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 10. " [42] ,IRQ (CAN FD ch.2 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 09. " [41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 08. " [40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 07. " [39] ,IRQ (external interrupt request ch.15/ch.31) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 06. " [38] ,IRQ (external interrupt request ch.14/ch.30) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 05. " [37] ,IRQ (external interrupt request ch.13/ch.29) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 04. " [36] ,IRQ (external interrupt request ch.12/ch.28) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x00 03. " [35] ,IRQ (external interrupt request ch.11/ch.27) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 02. " [34] ,IRQ (external interrupt request ch.10/ch.26) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 01. " [33] ,IRQ (external interrupt request ch.9/ch.25) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x00 00. " [32] ,IRQ (external interrupt request ch.8/ch.24) RAW status bits" "No interrupt,Interrupt" line.long 0x04 "IRQRS2,RAW Status Register 2" bitfld.long 0x04 31. " IRQRS[95] ,IRQ (TCRAM diag) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 28. " [92] ,IRQ (SHE) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 27. " [91] ,IRQ (SHE error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 09. " [73] ,IRQ (MFS TX ch.13) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 08. " [72] ,IRQ (MFS RX ch.13) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 07. " [71] ,IRQ (MFS TX ch.12) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 06. " [70] ,IRQ (MFS RX ch.12) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 05. " [69] ,IRQ (MFS TX ch.11) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 04. " [68] ,IRQ (MFS RX ch.11) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 03. " [67] ,IRQ (MFS TX ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 02. " [66] ,IRQ (MFS RX ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x04 01. " [65] ,IRQ (MFS TX ch.9) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x04 00. " [64] ,IRQ (MFS RX ch.9) RAW status bits" "No interrupt,Interrupt" line.long 0x08 "IRQRS3,RAW Status Register 3" bitfld.long 0x08 31. " IRQRS[127] ,IRQ (base timer ch.39) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 30. " [126] ,IRQ (base timer ch.38) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 29. " [125] ,IRQ (base timer ch.37) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 28. " [124] ,IRQ (base timer ch.36/44/45/46/47) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 27. " [123] ,IRQ (base timer ch.31) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 26. " [122] ,IRQ (base timer ch.30) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 25. " [121] ,IRQ (base timer ch.29) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 24. " [120] ,IRQ (base timer ch.28) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 23. " [119] ,IRQ (base timer ch.27) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 22. " [118] ,IRQ (base timer ch.26) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 21. " [117] ,IRQ (base timer ch.25) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 20. " [116] ,IRQ (base timer ch.24/32/33/34/35) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 19. " [115] ,IRQ (base timer ch.19) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 18. " [114] ,IRQ (base timer ch.18) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 17. " [113] ,IRQ (base timer ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 16. " [112] ,IRQ (base timer ch.16) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 15. " [111] ,IRQ (base timer ch.15) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 14. " [110] ,IRQ (base timer ch.14) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 13. " [109] ,IRQ (base timer ch.13) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 12. " [108] ,IRQ (base timer ch.12/20/21/22/23) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 11. " [107] ,IRQ (base timer ch.7) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 10. " [106] ,IRQ (base timer ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 09. " [105] ,IRQ (base timer ch.5) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 08. " [104] ,IRQ (base timer ch.4) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 07. " [103] ,IRQ (base timer ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 06. " [102] ,IRQ (base timer ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 05. " [101] ,IRQ (base timer ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 04. " [100] ,IRQ (base timer ch.0/8/9/10/11) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x08 03. " [99] ,IRQ (CR calibration) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 02. " [98] ,IRQ (RTC) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x08 01. " [97] ,IRQ (global timer (compare clear interrupt) RAW status bits" "No interrupt,Interrupt" line.long 0x0C "IRQRS4,RAW Status Register 4" bitfld.long 0x0C 30. " IRQRS[158] ,IRQ (FRT ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 29. " [157] ,IRQ (FRT ch.9) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 28. " [156] ,IRQ (FRT ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 26. " [154] ,IRQ (FRT ch.4) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 25. " [153] ,IRQ (FRT ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 24. " [152] ,IRQ (FRT ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 23. " [151] ,IRQ (FRT ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 22. " [150] ,IRQ (FRT ch.0) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 21. " [149] ,IRQ (reload timer ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 20. " [148] ,IRQ (reload timer ch.16) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 19. " [147] ,IRQ (reload timer ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 18. " [146] ,IRQ (reload timer ch.2) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 17. " [145] ,IRQ (reload timer ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 16. " [144] ,IRQ (reload timer ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 15. " [143] ,IRQ (base timer ch.63) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 14. " [142] ,IRQ (base timer ch.62) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 13. " [141] ,IRQ (base timer ch.61) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 12. " [140] ,IRQ (base timer ch.60) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 11. " [139] ,IRQ (base timer ch.55) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 10. " [138] ,IRQ (base timer ch.54) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 09. " [137] ,IRQ (base timer ch.53) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 08. " [136] ,IRQ (base timer ch.52) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 07. " [135] ,IRQ (base timer ch.51) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 06. " [134] ,IRQ (base timer ch.50) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 05. " [133] ,IRQ (base timer ch.49) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 04. " [132] ,IRQ (base timer ch.48/56/57/58/59) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 03. " [131] ,IRQ (base timer ch.43) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 02. " [130] ,IRQ (base timer ch.42) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x0C 01. " [129] ,IRQ (base timer ch.41) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x0C 00. " [128] ,IRQ (base timer ch.40) RAW status bits" "No interrupt,Interrupt" line.long 0x10 "IRQRS5,RAW Status Register 5" bitfld.long 0x10 31. " IRQRS[191] ,IRQ (ADC12B0 group interrupt) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 30. " [190] ,IRQ (ADC12B0 conversion done) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 29. " [189] ,IRQ (QPRC ch.9) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 28. " [188] ,IRQ (QPRC ch.8) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 27. " [187] ,IRQ (IRQ1 of output compare 10 (ch.21) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 26. " [186] ,IRQ (IRQ1 of output compare 9 (ch.19) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 25. " [185] ,IRQ (IRQ1 of output compare 8 (ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 23. " [183] ,IRQ (IRQ1 of output compare 2 (ch.5) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 22. " [182] ,IRQ (IRQ1 of output compare 1 (ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 21. " [181] ,IRQ (IRQ1 of output compare 0 (ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 20. " [180] ,IRQ (IRQ0 of output compare 10 (ch.20) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 19. " [179] ,IRQ (IRQ0 of output compare 9 (ch.18) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 18. " [178] ,IRQ (IRQ0 of output compare 8 (ch.16) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 16. " [176] ,IRQ (IRQ0 of output compare 2 (ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 15. " [175] ,IRQ (IRQ0 of output compare 1 (ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 14. " [174] ,IRQ (IRQ0 of output compare 0 (ch.0) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 13. " [173] ,IRQ (IRQ1 of input capture 10 (ch.21) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 12. " [172] ,IRQ (IRQ1 of input capture 9 (ch.19) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 11. " [171] ,IRQ (IRQ1 of input capture 8 (ch.17) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 10. " [170] ,IRQ (IRQ1 of input capture 2 (ch.5) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 09. " [169] ,IRQ (IRQ1 of input capture 1 (ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 08. " [168] ,IRQ (IRQ1 of input capture 0 (ch.1) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 07. " [167] ,IRQ (IRQ0 of input capture 10 (ch.20) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 06. " [166] ,IRQ (IRQ0 of input capture 9 (ch.18) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x10 05. " [165] ,IRQ (IRQ0 of input capture 8 (ch.16) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 04. " [164] ,IRQ (IRQ0 of input capture 2 (ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 03. " [163] ,IRQ (RQ0 of input capture 1 (ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x10 02. " [162] ,IRQ (IRQ0 of input capture 0 (ch.0) RAW status bits" "No interrupt,Interrupt" line.long 0x14 "IRQRS6,RAW Status Register 6" bitfld.long 0x14 31. " IRQRS[223] ,IRQ (MFS ch.1 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 30. " [222] ,IRQ (MFS ch.0 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 29. " [221] ,IRQ (PRGCRC) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 28. " [220] ,IRQ (CR5 performance monitor unit IRQ) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 27. " [219] ,IRQ (SCT sub OSC IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 26. " [218] ,IRQ (SCT main OSC IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 25. " [217] ,IRQ (SCT SRC IRQ) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 24. " [216] ,IRQ (SCT RC IRQ) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 23. " [215] ,IRQ (DMAC RLT (ch.0/1/2/3 OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 22. " [214] ,IRQ (DMAC completion ch.15) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 21. " [213] ,IRQ (DMAC completion ch.14) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 20. " [212] ,IRQ (DMAC completion ch.13) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 19. " [211] ,IRQ (DMAC completion ch.12) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 18. " [210] ,IRQ (DMAC completion ch.11) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 17. " [209] ,IRQ (DMAC completion ch.10) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 16. " [208] ,IRQ (DMAC completion ch.9) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 15. " [207] ,IRQ (DMAC completion ch.8) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 14. " [206] ,IRQ (DMAC completion ch.7) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 13. " [205] ,IRQ (DMAC completion ch.6) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 12. " [204] ,IRQ (DMAC completion ch.5) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 11. " [203] ,IRQ (DMAC completion ch.4) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 10. " [202] ,IRQ (DMAC completion ch.3) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 09. " [201] ,IRQ (DMAC completion ch.2) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 08. " [200] ,IRQ (DMAC completion ch.1) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 07. " [199] ,IRQ (DMAC completion ch.0) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 06. " [198] ,IRQ (DMA error) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 05. " [197] ,IRQ (ADC12B1 RCO) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 04. " [196] ,IRQ (ADC12B1 pulse detection function) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x14 03. " [195] ,IRQ (ADC12B1 group interrupt) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 02. " [194] ,IRQ (ADC12B1 conversion done) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 01. " [195] ,IRQ (ADC12B0 RCO) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x14 00. " [194] ,IRQ (ADC12B0 pulse detection function) RAW status bits" "No interrupt,Interrupt" line.long 0x18 "IRQRS7,RAW Status Register 7" bitfld.long 0x18 11. " IRQRS[235] ,IRQ (MFS ch.13 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 10. " [234] ,IRQ (MFS ch.12 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 09. " [233] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 08. " [232] ,IRQ (MFS ch.10 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 07. " [231] ,IRQ (MFS ch.9 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 06. " [230] ,IRQ (MFS ch.8 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 05. " [229] ,IRQ (MFS ch.7 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 04. " [228] ,IRQ (MFS ch.6 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" newline bitfld.long 0x18 03. " [227] ,IRQ (MFS ch.5 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 02. " [226] ,IRQ (MFS ch.4 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 01. " [225] ,IRQ (MFS ch.3 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" bitfld.long 0x18 00. " [224] ,IRQ (MFS ch.2 error (Tx/Rx error/status OR-ed) RAW status bits" "No interrupt,Interrupt" endif tree.end width 8. tree "IRQPS IRC IRQ Preprocessed Status Register" rgroup.long 0xCF0++0x03 line.long 0x00 "IRQPS0,Preprocessed Status Register 0" bitfld.long 0x00 31. " IRQPS[31] ,IRQ (external interrupt request ch.7/ch.23) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,IRQ (external interrupt request ch.6/ch.22) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,IRQ (external interrupt request ch.5/ch.21) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,IRQ (external interrupt request ch.4/ch.20) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,IRQ (external interrupt request ch.3/ch.19) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,IRQ (external interrupt request ch.2/ch.18) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,IRQ (external interrupt request ch.1/ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,IRQ (external interrupt request ch.0/ch.16) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 20. " [20] ,IRQ (work FLASH RDY/write enable release/single bit error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,IRQ (IRC vector address RAM single bit error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 15. " [15] ,IRQ (CAN FD RAM(ch.0 to 4/ch.8) single bit error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,IRQ (system SRAM single bit error) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 10. " [10] ,IRQ (work FLASH hang up) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 08. " [8] ,IRQ (TCFLASH RDY/hang up/single bit error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 03. " [3] ,IRQ (SW-WDT pre-warning) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 02. " [2] ,IRQ (HW-WDT pre-warning) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 01. " [1] ,IRQ (system control status) preprocessed status bit" "No interrupt,Interrupt" sif cpuis("S6J351*") rgroup.long 0xCF4++0x1B line.long 0x00 "IRQPS1,Preprocessed Status Register 1" bitfld.long 0x00 31. " IRQPS[63] ,IRQ (MFS TX ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 30. " [62] ,IRQ (MFS RX ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 29. " [61] ,IRQ (MFS TX ch.7) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 28. " [60] ,IRQ (MFS RX ch.7) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [59] ,IRQ (MFS TX ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 26. " [58] ,IRQ (MFS RX ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 25. " [57] ,IRQ (MFS TX ch.5) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 24. " [56] ,IRQ (MFS RX ch.5) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [55] ,IRQ (MFS TX ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 22. " [54] ,IRQ (MFS RX ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 21. " [53] ,IRQ (MFS TX ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 20. " [52] ,IRQ (MFS RX ch.3) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [51] ,IRQ (MFS TX ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 18. " [50] ,IRQ (MFS RX ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 17. " [49] ,IRQ (MFS TX ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 16. " [48] ,IRQ (MFS RX ch.1) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [47] ,IRQ (MFS TX ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 14. " [46] ,IRQ (MFS RX ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 11. " [43] ,IRQ (CAN FD ch.3 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 10. " [42] ,IRQ (CAN FD ch.2 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 09. " [41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 08. " [40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 07. " [39] ,IRQ (external interrupt request ch.15/ch.31) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 06. " [38] ,IRQ (external interrupt request ch.14/ch.30) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 05. " [37] ,IRQ (external interrupt request ch.13/ch.29) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 04. " [36] ,IRQ (external interrupt request ch.12/ch.28) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 03. " [35] ,IRQ (external interrupt request ch.11/ch.27) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 02. " [34] ,IRQ (external interrupt request ch.10/ch.26) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 01. " [33] ,IRQ (external interrupt request ch.9/ch.25) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 00. " [32] ,IRQ (external interrupt request ch.8/ch.24) preprocessed status bit" "No interrupt,Interrupt" line.long 0x04 "IRQPS2,Preprocessed Status Register 2" bitfld.long 0x04 31. " IRQPS[95] ,IRQ (TCRAM diag) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 30. " [94] ,IRQ (DDR HSSPI TX) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 29. " [93] ,IRQ (DDR HSSPI RX) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 28. " [92] ,IRQ (SHE) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 27. " [91] ,IRQ (SHE error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 05. " [69] ,IRQ (MFS TX ch.11) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 04. " [68] ,IRQ (MFS RX ch.11) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 03. " [67] ,IRQ (MFS TX ch.10) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 02. " [66] ,IRQ (MFS RX ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 01. " [65] ,IRQ (MFS TX ch.9) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 00. " [64] ,IRQ (MFS RX ch.9) preprocessed status bit" "No interrupt,Interrupt" line.long 0x08 "IRQPS3,Preprocessed Status Register 3" bitfld.long 0x08 27. " IRQPS[123] ,IRQ (base timer ch.31) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 26. " [122] ,IRQ (base timer ch.30) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 25. " [121] ,IRQ (base timer ch.29) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 24. " [120] ,IRQ (base timer ch.28) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 23. " [119] ,IRQ (base timer ch.27) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 22. " [118] ,IRQ (base timer ch.26) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 21. " [117] ,IRQ (base timer ch.25) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 20. " [116] ,IRQ (base timer ch.24/32/33/34/35) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 19. " [115] ,IRQ (base timer ch.19) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 18. " [114] ,IRQ (base timer ch.18) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 17. " [113] ,IRQ (base timer ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 16. " [112] ,IRQ (base timer ch.16) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 15. " [111] ,IRQ (base timer ch.15) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 14. " [110] ,IRQ (base timer ch.14) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 13. " [109] ,IRQ (base timer ch.13) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 12. " [108] ,IRQ (base timer ch.12/20/21/22/23) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 11. " [107] ,IRQ (base timer ch.7) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 10. " [106] ,IRQ (base timer ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 09. " [105] ,IRQ (base timer ch.5) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 08. " [104] ,IRQ (base timer ch.4) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 07. " [103] ,IRQ (base timer ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 06. " [102] ,IRQ (base timer ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 05. " [101] ,IRQ (base timer ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 04. " [100] ,IRQ (base timer ch.0/8/9/10/11) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 03. " [99] ,IRQ (CR calibration) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 02. " [98] ,IRQ (RTC) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 01. " [97] ,IRQ(global timer(compare clear interrupt)) preprocessed status bit" "No interrupt,Interrupt" line.long 0x0C "IRQPS4,Preprocessed Status Register 4" bitfld.long 0x0C 30. " IRQPS[158] ,IRQ (FRT ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 29. " [157] ,IRQ (FRT ch.9) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 28. " [156] ,IRQ (FRT ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 26. " [154] ,IRQ (FRT ch.4) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 25. " [153] ,IRQ (FRT ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 24. " [152] ,IRQ (FRT ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 23. " [151] ,IRQ (FRT ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 22. " [150] ,IRQ (FRT ch.0) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 21. " [149] ,IRQ (reload timer ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 20. " [148] ,IRQ (reload timer ch.16) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 19. " [147] ,IRQ (reload timer ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 18. " [146] ,IRQ (reload timer ch.2) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 17. " [145] ,IRQ (reload timer ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 16. " [144] ,IRQ (reload timer ch.0) preprocessed status bit" "No interrupt,Interrupt" line.long 0x10 "IRQPS5,Preprocessed Status Register 5" bitfld.long 0x10 29. " IRQPS[189] ,IRQ (QPRC ch.9) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 28. " [188] ,IRQ (QPRC ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 27. " [187] ,IRQ (IRQ1 of output compare 10 (ch.21) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 26. " [186] ,IRQ1 of output compare 9 (ch.19) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 25. " [185] ,IRQ (IRQ1 of output compare 8 (ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 23. " [183] ,IRQ (IRQ1 of output compare 2 (ch.5) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 22. " [182] ,IRQ (IRQ1 of output compare 1 (ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 21. " [181] ,IRQ (IRQ1 of output compare 0 (ch.1) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 20. " [180] ,IRQ (IRQ0 of output compare 10 (ch.20) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 19. " [179] ,IRQ (IRQ0 of output compare 9 (ch.18) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 18. " [178] ,IRQ (IRQ0 of output compare 8 (ch.16) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 16. " [176] ,IRQ (IRQ0 of output compare 2 (ch.4) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 15. " [175] ,IRQ (IRQ0 of output compare 1 (ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 14. " [174] ,IRQ (IRQ0 of output compare 0 (ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 13. " [173] ,IRQ (IRQ1 of input capture 10 (ch.21) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 12. " [172] ,IRQ (IRQ1 of input capture 9 (ch.19) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 11. " [171] ,IRQ (IRQ1 of input capture 8 (ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 10. " [170] ,IRQ (IRQ1 of input capture 2 (ch.5) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 09. " [169] ,IRQ (IRQ1 of input capture 1 (ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 08. " [168] ,IRQ (IRQ1 of input capture 0 (ch.1) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 07. " [167] ,IRQ (IRQ0 of input capture 10 (ch.20) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 06. " [166] ,IRQ (IRQ0 of input capture 9 (ch.18) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 05. " [165] ,IRQ (IRQ0 of input capture 8 (ch.16) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 04. " [164] ,IRQ (IRQ0 of input capture 2 (ch.4) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 03. " [163] ,IRQ (RQ0 of input capture 1 (ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 02. " [162] ,IRQ (IRQ0 of input capture 0 (ch.0) preprocessed status bit" "No interrupt,Interrupt" line.long 0x14 "IRQPS6,Preprocessed Status Register 6" bitfld.long 0x14 31. " IRQPS[223] ,IRQ (MFS ch.1 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 30. " [222] ,IRQ (MFS ch.0 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 29. " [221] ,IRQ (PRGCRC) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 28. " [220] ,IRQ (CR5performanceemonitorrunitt IRQ) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 27. " [219] ,IRQ (SCTsubb OSC IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 26. " [218] ,IRQ (SCT main OSC IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 25. " [217] ,IRQ (SCT SRC IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 24. " [216] ,IRQ (SCT RC IRQ) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 23. " [215] ,IRQ (DMAC RLT (ch.0/1/2/3 OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 22. " [214] ,IRQ (DMAC completion ch.15) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 21. " [213] ,IRQ (DMAC completion ch.14) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 20. " [212] ,IRQ (DMAC completion ch.13) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 19. " [211] ,IRQ (DMAC completion ch.12) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 18. " [210] ,IRQ (DMAC completion ch.11) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 17. " [209] ,IRQ (DMAC completion ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 16. " [208] ,IRQ (DMAC completion ch.9) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 15. " [207] ,IRQ (DMAC completion ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 14. " [206] ,IRQ (DMAC completion ch.7) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 13. " [205] ,IRQ (DMAC completion ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 12. " [204] ,IRQ (DMAC completion ch.5) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 11. " [203] ,IRQ (DMAC completion ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 10. " [202] ,IRQ (DMAC completion ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 09. " [201] ,IRQ (DMAC completion ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 08. " [200] ,IRQ (DMAC completion ch.1) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 07. " [199] ,IRQ (DMAC completion ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 06. " [198] ,IRQ (DMA error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 05. " [197] ,IRQ (ADC12B1 RCO) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 04. " [196] ,IRQ (ADC12B1 pulse detection function) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 03. " [195] ,IRQ (ADC12B1 group interrupt) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 02. " [194] ,IRQ (ADC12B1 conversion done) preprocessed status bit" "No interrupt,Interrupt" line.long 0x18 "IRQPS7,Preprocessed Status Register 7" bitfld.long 0x18 09. " IRQPS[233] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 08. " [232] ,IRQ (MFS ch.10 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 07. " [231] ,IRQ (MFS ch.9 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 06. " [230] ,IRQ (MFS ch.8 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 05. " [229] ,IRQ (MFS ch.7 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 04. " [228] ,IRQ (MFS ch.6 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 03. " [227] ,IRQ (MFS ch.5 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 02. " [226] ,IRQ (MFS ch.4 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 01. " [225] ,IRQ (MFS ch.3 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 00. " [224] ,IRQ (MFS ch.2 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" else rgroup.long 0xCF4++0x1B line.long 0x00 "IRQPS1,Preprocessed Status Register 1" bitfld.long 0x00 31. " IRQPS[63] ,IRQ (MFS TX ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 30. " [62] ,IRQ (MFS RX ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 29. " [61] ,IRQ (MFS TX ch.7) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 28. " [60] ,IRQ (MFS RX ch.7) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [59] ,IRQ (MFS TX ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 26. " [58] ,IRQ (MFS RX ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 25. " [57] ,IRQ (MFS TX ch.5) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 24. " [56] ,IRQ (MFS RX ch.5) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [55] ,IRQ (MFS TX ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 22. " [54] ,IRQ (MFS RX ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 21. " [53] ,IRQ (MFS TX ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 20. " [52] ,IRQ (MFS RX ch.3) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [51] ,IRQ (MFS TX ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 18. " [50] ,IRQ (MFS RX ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 17. " [49] ,IRQ (MFS TX ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 16. " [48] ,IRQ (MFS RX ch.1) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [47] ,IRQ (MFS TX ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 14. " [46] ,IRQ (MFS RX ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 13. " [45] ,IRQ (CAN FD ch.8 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 12. " [44] ,IRQ (CAN FD ch.4 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [43] ,IRQ (CAN FD ch.3 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 10. " [42] ,IRQ (CAN FD ch.2 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 09. " [41] ,IRQ (CAN FD ch.1 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 08. " [40] ,IRQ (CAN FD ch.0 (OR-ed of all factors) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 07. " [39] ,IRQ (external interrupt request ch.15/ch.31) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 06. " [38] ,IRQ (external interrupt request ch.14/ch.30) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 05. " [37] ,IRQ (external interrupt request ch.13/ch.29) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 04. " [36] ,IRQ (external interrupt request ch.12/ch.28) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x00 03. " [35] ,IRQ (external interrupt request ch.11/ch.27) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 02. " [34] ,IRQ (external interrupt request ch.10/ch.26) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 01. " [33] ,IRQ (external interrupt request ch.9/ch.25) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x00 00. " [32] ,IRQ (external interrupt request ch.8/ch.24) preprocessed status bit" "No interrupt,Interrupt" line.long 0x04 "IRQPS2,Preprocessed Status Register 2" bitfld.long 0x04 31. " IRQPS[95] ,IRQ (TCRAM diag) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 28. " [92] ,IRQ (SHE) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 27. " [91] ,IRQ (SHE error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 09. " [73] ,IRQ (MFS TX ch.13) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 08. " [72] ,IRQ (MFS RX ch.13) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 07. " [71] ,IRQ (MFS TX ch.12) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 06. " [70] ,IRQ (MFS RX ch.12) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 05. " [69] ,IRQ (MFS TX ch.11) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 04. " [68] ,IRQ (MFS RX ch.11) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 03. " [67] ,IRQ (MFS TX ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 02. " [66] ,IRQ (MFS RX ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x04 01. " [65] ,IRQ (MFS TX ch.9) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x04 00. " [64] ,IRQ (MFS RX ch.9) preprocessed status bit" "No interrupt,Interrupt" line.long 0x08 "IRQPS3,Preprocessed Status Register 3" bitfld.long 0x08 31. " IRQPS[127] ,IRQ (base timer ch.39) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 30. " [126] ,IRQ (base timer ch.38) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 29. " [125] ,IRQ (base timer ch.37) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 28. " [124] ,IRQ (base timer ch.36/44/45/46/47) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 27. " [123] ,IRQ (base timer ch.31) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 26. " [122] ,IRQ (base timer ch.30) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 25. " [121] ,IRQ (base timer ch.29) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 24. " [120] ,IRQ (base timer ch.28) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 23. " [119] ,IRQ (base timer ch.27) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 22. " [118] ,IRQ (base timer ch.26) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 21. " [117] ,IRQ (base timer ch.25) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 20. " [116] ,IRQ (base timer ch.24/32/33/34/35) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 19. " [115] ,IRQ (base timer ch.19) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 18. " [114] ,IRQ (base timer ch.18) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 17. " [113] ,IRQ (base timer ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 16. " [112] ,IRQ (base timer ch.16) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 15. " [111] ,IRQ (base timer ch.15) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 14. " [110] ,IRQ (base timer ch.14) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 13. " [109] ,IRQ (base timer ch.13) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 12. " [108] ,IRQ (base timer ch.12/20/21/22/23) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 11. " [107] ,IRQ (base timer ch.7) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 10. " [106] ,IRQ (base timer ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 09. " [105] ,IRQ (base timer ch.5) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 08. " [104] ,IRQ (base timer ch.4) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 07. " [103] ,IRQ (base timer ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 06. " [102] ,IRQ (base timer ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 05. " [101] ,IRQ (base timer ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 04. " [100] ,IRQ (base timer ch.0/8/9/10/11) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x08 03. " [99] ,IRQ (CR calibration) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 02. " [98] ,IRQ (RTC) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x08 01. " [97] ,IRQ(global timer(compare clear interrupt) preprocessed status bit" "No interrupt,Interrupt" line.long 0x0C "IRQPS4,Preprocessed Status Register 4" bitfld.long 0x0C 30. " IRQPS[158] ,IRQ (FRT ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 29. " [157] ,IRQ (FRT ch.9) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 28. " [156] ,IRQ (FRT ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 26. " [154] ,IRQ (FRT ch.4) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 25. " [153] ,IRQ (FRT ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 24. " [152] ,IRQ (FRT ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 23. " [151] ,IRQ (FRT ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 22. " [150] ,IRQ (FRT ch.0) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 21. " [149] ,IRQ (reload timer ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 20. " [148] ,IRQ (reload timer ch.16) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 19. " [147] ,IRQ (reload timer ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 18. " [146] ,IRQ (reload timer ch.2) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 17. " [145] ,IRQ (reload timer ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 16. " [144] ,IRQ (reload timer ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 15. " [143] ,IRQ (base timer ch.63) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 14. " [142] ,IRQ (base timer ch.62) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 13. " [141] ,IRQ (base timer ch.61) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 12. " [140] ,IRQ (base timer ch.60) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 11. " [139] ,IRQ (base timer ch.55) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 10. " [138] ,IRQ (base timer ch.54) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 09. " [137] ,IRQ (base timer ch.53) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 08. " [136] ,IRQ (base timer ch.52) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 07. " [135] ,IRQ (base timer ch.51) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 06. " [134] ,IRQ (base timer ch.50) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 05. " [133] ,IRQ (base timer ch.49) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 04. " [132] ,IRQ (base timer ch.48/56/57/58/59) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 03. " [131] ,IRQ (base timer ch.43) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 02. " [130] ,IRQ (base timer ch.42) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x0C 01. " [129] ,IRQ (base timer ch.41) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x0C 00. " [128] ,IRQ (base timer ch.40) preprocessed status bit" "No interrupt,Interrupt" line.long 0x10 "IRQPS5,Preprocessed Status Register 5" bitfld.long 0x10 31. " IRQPS[191] ,IRQ (ADC12B0groupp interrupt) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 30. " [190] ,IRQ (ADC12B0 conversion done) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 29. " [189] ,IRQ (QPRC ch.9) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 28. " [188] ,IRQ (QPRC ch.8) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 27. " [187] ,IRQ (IRQ1 of output compare 10 (ch.21) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 26. " [186] ,IRQ1 of output compare 9 (ch.19) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 25. " [185] ,IRQ (IRQ1 of output compare 8 (ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 23. " [183] ,IRQ (IRQ1 of output compare 2 (ch.5) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 22. " [182] ,IRQ (IRQ1 of output compare 1 (ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 21. " [181] ,IRQ (IRQ1 of output compare 0 (ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 20. " [180] ,IRQ (IRQ0 of output compare 10 (ch.20) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 19. " [179] ,IRQ (IRQ0 of output compare 9 (ch.18) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 18. " [178] ,IRQ (IRQ0 of output compare 8 (ch.16) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 16. " [176] ,IRQ (IRQ0 of output compare 2 (ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 15. " [175] ,IRQ (IRQ0 of output compare 1 (ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 14. " [174] ,IRQ (IRQ0 of output compare 0 (ch.0) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 13. " [173] ,IRQ (IRQ1 of input capture 10 (ch.21) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 12. " [172] ,IRQ (IRQ1 of input capture 9 (ch.19) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 11. " [171] ,IRQ (IRQ1 of input capture 8 (ch.17) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 10. " [170] ,IRQ (IRQ1 of input capture 2 (ch.5) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 09. " [169] ,IRQ (IRQ1 of input capture 1 (ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 08. " [168] ,IRQ (IRQ1 of input capture 0 (ch.1) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 07. " [167] ,IRQ (IRQ0 of input capture 10 (ch.20) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 06. " [166] ,IRQ (IRQ0 of input capture 9 (ch.18) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x10 05. " [165] ,IRQ (IRQ0 of input capture 8 (ch.16) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 04. " [164] ,IRQ (IRQ0 of input capture 2 (ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 03. " [163] ,IRQ (RQ0 of input capture 1 (ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x10 02. " [162] ,IRQ (IRQ0 of input capture 0 (ch.0) preprocessed status bit" "No interrupt,Interrupt" line.long 0x14 "IRQPS6,Preprocessed Status Register 6" bitfld.long 0x14 31. " IRQPS[223] ,IRQ (MFS ch.1 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 30. " [222] ,IRQ (MFS ch.0 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 29. " [221] ,IRQ (PRGCRC) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 28. " [220] ,IRQ (CR5performanceemonitorrunitt IRQ) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 27. " [219] ,IRQ (SCTsubb OSC IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 26. " [218] ,IRQ (SCT main OSC IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 25. " [217] ,IRQ (SCT SRC IRQ) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 24. " [216] ,IRQ (SCT RC IRQ) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 23. " [215] ,IRQ (DMAC RLT (ch.0/1/2/3 OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 22. " [214] ,IRQ (DMAC completion ch.15) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 21. " [213] ,IRQ (DMAC completion ch.14) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 20. " [212] ,IRQ (DMAC completion ch.13) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 19. " [211] ,IRQ (DMAC completion ch.12) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 18. " [210] ,IRQ (DMAC completion ch.11) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 17. " [209] ,IRQ (DMAC completion ch.10) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 16. " [208] ,IRQ (DMAC completion ch.9) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 15. " [207] ,IRQ (DMAC completion ch.8) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 14. " [206] ,IRQ (DMAC completion ch.7) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 13. " [205] ,IRQ (DMAC completion ch.6) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 12. " [204] ,IRQ (DMAC completion ch.5) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 11. " [203] ,IRQ (DMAC completion ch.4) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 10. " [202] ,IRQ (DMAC completion ch.3) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 09. " [201] ,IRQ (DMAC completion ch.2) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 08. " [200] ,IRQ (DMAC completion ch.1) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 07. " [199] ,IRQ (DMAC completion ch.0) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 06. " [198] ,IRQ (DMA error) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 05. " [197] ,IRQ (ADC12B1 RCO) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 04. " [196] ,IRQ (ADC12B1 pulse detection function) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x14 03. " [195] ,IRQ (ADC12B1 group interrupt) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 02. " [194] ,IRQ (ADC12B1 conversion done) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 01. " [193] ,IRQ (ADC12B0 RCO) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x14 00. " [192] ,IRQ (ADC12B0 pulse detection function) preprocessed status bit" "No interrupt,Interrupt" line.long 0x18 "IRQPS7,Preprocessed Status Register 7" bitfld.long 0x18 11. " IRQPS[235] ,IRQ (MFS ch.13 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 10. " [234] ,IRQ (MFS ch.12 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 09. " [233] ,IRQ (MFS ch.11 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 08. " [232] ,IRQ (MFS ch.10 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 07. " [231] ,IRQ (MFS ch.9 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 06. " [230] ,IRQ (MFS ch.8 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 05. " [229] ,IRQ (MFS ch.7 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 04. " [228] ,IRQ (MFS ch.6 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" newline bitfld.long 0x18 03. " [227] ,IRQ (MFS ch.5 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 02. " [226] ,IRQ (MFS ch.4 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 01. " [225] ,IRQ (MFS ch.3 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" bitfld.long 0x18 00. " [224] ,IRQ (MFS ch.2 error (Tx/Rx error/status OR-ed) preprocessed status bit" "No interrupt,Interrupt" endif tree.end newline group.long 0xD30++0x03 line.long 0x00 "UNLOCK,Unlock Register" group.long 0xD40++0x03 line.long 0x00 "EEI,ECC Error Interrupt Register" rbitfld.long 0x00 24. " EEIS ,ECC error IRQ status bit" "Not occurred,Occurred" bitfld.long 0x00 16. " EEIC ,ECC error IRQ clear bit" "No effect,Clear" rbitfld.long 0x00 8. " EENS ,ECC error NMI status bit" "Not occurred,Occurred" bitfld.long 0x00 0. " EENC ,ECC error NMI clear bit" "No effect,Clear" rgroup.long 0xD44++0x03 line.long 0x00 "EAN,ECC Address Number Register" hexmask.long.byte 0x00 0.--7. 0x01 " EAN ,ECC error occurrence address bits" group.long 0xD48++0x0F line.long 0x00 "ET,ECC Test Register" bitfld.long 0x00 0. " ET ,ECC test enable/disable setting bit" "Disabled,Enabled" line.long 0x04 "EEB0,ECC Bit Register" hexmask.long 0x04 2.--31. 1. " EEB ,ECC error occurrence bits" line.long 0x08 "EEB1,ECC Bit Register" hexmask.long 0x08 2.--31. 1. " EEB ,ECC error occurrence bits" line.long 0x0C "EEB2,ECC Bit Register" hexmask.long.byte 0x0C 8.--14. 1. " EEBO ,ECC error occurrence bits" hexmask.long.byte 0x0C 0.--6. 1. " EEBE ,ECC error occurrence bits" group.long 0xD3C++0x03 line.long 0x00 "IRQEEVA,ECC Error Vector Address Register" width 15. base ad:0xFFFEE3FC rgroup.long 0x00++0x03 "Register Memory Layout of Interrupt Controler (HSEL3)" line.long 0x00 "IRC0_NMIVASBR,NMI Vector Address Status Mirror Register" rgroup.long 0x1800++0x03 "Register Memory Layout of Interrupt Controler (HSEL2)" line.long 0x00 "IRC_NMIVASBR,NMI Vector Address Status Register" width 0x0B tree.end tree "TPU (Time Protection Unit)" base ad:0xB0408000 width 8. group.long 0x00++0x03 line.long 0x00 "UNLOCK,TPU Lock Release Register" rgroup.long 0x04++0x03 line.long 0x00 "LST,TPU Lock Status Register" bitfld.long 0x00 0. " LST ,Lock status of the timing protection unit" "Unlocked,Locked" if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "CFG,TPU Configuration Register" bitfld.long 0x00 24. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " GLBPSE ,Global prescaler enable" "Disabled,Enabled" bitfld.long 0x00 16.--21. " GLBPS ,Global prescaler division" "1/1,1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16,1/17,1/18,1/19,1/20,1/21,1/22,1/23,1/24,1/25,1/26,1/27,1/28,1/29,1/30,1/31,1/32,31/3,1/34,1/35,1/36,1/37,1/38,1/39,1/40,1/41,1/42,1/43,1/44,1/45,1/46,1/47,1/48,1/49,1/50,1/51,1/52,1/53,1/54,1/55,1/56,1/57,1/58,1/59,1/60,1/61,1/62,1/63,1/64" bitfld.long 0x00 0. " INTE ,Timing protection unit interrupt enable" "Disabled,Enabled" else rgroup.long 0x08++0x03 line.long 0x00 "CFG,TPU Configuration Register" bitfld.long 0x00 24. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 23. " GLBPSE ,Global prescaler enable" "Disabled,Enabled" bitfld.long 0x00 16.--21. " GLBPS ,Global prescaler division" "1/1,1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16,1/17,1/18,1/19,1/20,1/21,1/22,1/23,1/24,1/25,1/26,1/27,1/28,1/29,1/30,1/31,1/32,31/3,1/34,1/35,1/36,1/37,1/38,1/39,1/40,1/41,1/42,1/43,1/44,1/45,1/46,1/47,1/48,1/49,1/50,1/51,1/52,1/53,1/54,1/55,1/56,1/57,1/58,1/59,1/60,1/61,1/62,1/63,1/64" bitfld.long 0x00 0. " INTE ,Timing protection unit interrupt enable" "Disabled,Enabled" endif rgroup.long 0x0C++0x07 line.long 0x00 "TIR,TPU Timer Interrupt Request Register" bitfld.long 0x00 7. " IR7 ,Timer 7 interrupt request" "No interrupt,Interrupt" bitfld.long 0x00 6. " IR6 ,Timer 6 interrupt request" "No interrupt,Interrupt" bitfld.long 0x00 5. " IR5 ,Timer 5 interrupt request" "No interrupt,Interrupt" bitfld.long 0x00 4. " IR4 ,Timer 4 interrupt request" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " IR3 ,Timer 3 interrupt request" "No interrupt,Interrupt" bitfld.long 0x00 2. " IR2 ,Timer 2 interrupt request" "No interrupt,Interrupt" bitfld.long 0x00 1. " IR1 ,Timer 1 interrupt request" "No interrupt,Interrupt" bitfld.long 0x00 0. " IR0 ,Timer 0 interrupt request" "No interrupt,Interrupt" line.long 0x04 "TST,TPU Timer Status Register" bitfld.long 0x04 7. " ST7 ,Timer 7 status" "Stopped,Running" bitfld.long 0x04 6. " ST6 ,Timer 6 status" "Stopped,Running" bitfld.long 0x04 5. " ST5 ,Timer 5 status" "Stopped,Running" bitfld.long 0x04 4. " ST4 ,Timer 4 status" "Stopped,Running" newline bitfld.long 0x04 3. " ST3 ,Timer 3 status" "Stopped,Running" bitfld.long 0x04 2. " ST2 ,Timer 2 status" "Stopped,Running" bitfld.long 0x04 1. " ST1 ,Timer 1 status" "Stopped,Running" bitfld.long 0x04 0. " ST0 ,Timer 0 status" "Stopped,Running" if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "TIE,TPU Timer Interrupt Enable Register" bitfld.long 0x00 7. " IE7 ,Timer 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " IE6 ,Timer 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IE5 ,Timer 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IE4 ,Timer 4 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " IE3 ,Timer 3 Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " IE2 ,Timer 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE1 ,Timer 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " IE0 ,Timer 0 interrupt enable" "Disabled,Enabled" else rgroup.long 0x14++0x03 line.long 0x00 "TIE,TPU Timer Interrupt Enable Register" bitfld.long 0x00 7. " IE7 ,Timer 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " IE6 ,Timer 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " IE5 ,Timer 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IE4 ,Timer 4 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " IE3 ,Timer 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " IE2 ,Timer 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE1 ,Timer 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " IE0 ,Timer 0 interrupt enable" "Disabled,Enabled" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x30++0x03 line.long 0x00 "TCN00,TPU Timer 0 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" else rgroup.long 0x30++0x03 line.long 0x00 "TCN00,TPU Timer 0 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x34++0x03 line.long 0x00 "TCN01,TPU Timer 1 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" else rgroup.long 0x34++0x03 line.long 0x00 "TCN01,TPU Timer 1 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x38++0x03 line.long 0x00 "TCN02,TPU Timer 2 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" else rgroup.long 0x38++0x03 line.long 0x00 "TCN02,TPU Timer 2 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x3C++0x03 line.long 0x00 "TCN03,TPU Timer 3 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" else rgroup.long 0x3C++0x03 line.long 0x00 "TCN03,TPU Timer 3 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x40++0x03 line.long 0x00 "TCN04,TPU Timer 4 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" else rgroup.long 0x40++0x03 line.long 0x00 "TCN04,TPU Timer 4 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x44++0x03 line.long 0x00 "TCN05,TPU Timer 5 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" else rgroup.long 0x44++0x03 line.long 0x00 "TCN05,TPU Timer 5 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x48++0x03 line.long 0x00 "TCN06,TPU Timer 6 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" else rgroup.long 0x48++0x03 line.long 0x00 "TCN06,TPU Timer 6 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x4C++0x03 line.long 0x00 "TCN07,TPU Timer 7 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" else rgroup.long 0x4C++0x03 line.long 0x00 "TCN07,TPU Timer 7 Control Register 0" bitfld.long 0x00 31. " START ,Timer operation start" "No effect,Start" bitfld.long 0x00 30. " STOP ,Timer operation stop" "No effect,Stop" bitfld.long 0x00 29. " CONT ,Timer operation restart" "No effect,Restart" bitfld.long 0x00 28. " IES ,Timer interrupt enable set" "No effect,Enable" newline bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear" "No effect,Disable" bitfld.long 0x00 26. " IRC ,Timer interrupt request clear" "No effect,Clear" hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x50++0x03 line.long 0x00 "TCN10,TPU Timer 0 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" else rgroup.long 0x50++0x03 line.long 0x00 "TCN10,TPU Timer 0 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x54++0x03 line.long 0x00 "TCN11,TPU Timer 1 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" else rgroup.long 0x54++0x03 line.long 0x00 "TCN11,TPU Timer 1 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x58++0x03 line.long 0x00 "TCN12,TPU Timer 2 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" else rgroup.long 0x58++0x03 line.long 0x00 "TCN12,TPU Timer 2 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x5C++0x03 line.long 0x00 "TCN13,TPU Timer 3 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" else rgroup.long 0x5C++0x03 line.long 0x00 "TCN13,TPU Timer 3 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x60++0x03 line.long 0x00 "TCN14,TPU Timer 4 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" else rgroup.long 0x60++0x03 line.long 0x00 "TCN14,TPU Timer 4 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x64++0x03 line.long 0x00 "TCN15,TPU Timer 5 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" else rgroup.long 0x64++0x03 line.long 0x00 "TCN15,TPU Timer 5 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x68++0x03 line.long 0x00 "TCN16,TPU Timer 6 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" else rgroup.long 0x68++0x03 line.long 0x00 "TCN16,TPU Timer 6 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" endif if (((per.l(ad:0xB0408000+0x04))&0x01)==0x00) group.long 0x6C++0x03 line.long 0x00 "TCN17,TPU Timer 7 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" else rgroup.long 0x6C++0x03 line.long 0x00 "TCN17,TPU Timer 7 Control Register 1" bitfld.long 0x00 4. " PL ,Preload function enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRT ,Free-run function enable" "Disabled,Enabled" bitfld.long 0x00 2. " TMOD ,Timer operation mode" "Normal,Overflow" bitfld.long 0x00 0.--1. " PS ,Individual prescaler division" "/1,/2,/4,/16" endif rgroup.long 0x70++0x03 line.long 0x00 "TCC0,TPU Timer 0 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value" rgroup.long 0x74++0x03 line.long 0x00 "TCC1,TPU Timer 1 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value" rgroup.long 0x78++0x03 line.long 0x00 "TCC2,TPU Timer 2 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value" rgroup.long 0x7C++0x03 line.long 0x00 "TCC3,TPU Timer 3 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value" rgroup.long 0x80++0x03 line.long 0x00 "TCC4,TPU Timer 4 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value" rgroup.long 0x84++0x03 line.long 0x00 "TCC5,TPU Timer 5 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value" rgroup.long 0x88++0x03 line.long 0x00 "TCC6,TPU Timer 6 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value" rgroup.long 0x8C++0x03 line.long 0x00 "TCC7,TPU Timer 7 Current Count Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value" width 0x0B tree.end tree "SEC (Security)" base ad:0xB0411300 width 9. if (((per.l(ad:0xB0411300+0xC0))&0x01)==0x00) rgroup.long 0xC0++0x03 line.long 0x00 "SECSTAT,Security Status Register" bitfld.long 0x00 19. " TBOSEC ,ECC single error correction in TBO data" "No error,Error" bitfld.long 0x00 18. " TBODED ,ECC double error detection in TBO data" "No error,Error" bitfld.long 0x00 17. " ECCSEC ,ECC single error correction when fetching security marker" "No error,Error" bitfld.long 0x00 16. " ECCDED ,ECC double error detection when fetching security marker" "No error,Error" newline bitfld.long 0x00 8. " UMV ,Specification of the unlock marker value" "Non-trivial,Trivial" bitfld.long 0x00 5. " SFDONE ,Security fetch done register" "Ongoing,Finished" bitfld.long 0x00 4. " SWPOE ,Sector write permission overwrite enable register" "Disabled,Enabled" bitfld.long 0x00 3. " SECOE ,Security overwrite enable register" "Disabled,Enabled" newline bitfld.long 0x00 2. " CEEN ,Chip erase enable register" "Disabled,Enabled" textfld " " bitfld.long 0x00 0. " SECEN ,Security enable register" "Disabled,Enabled" else rgroup.long 0xC0++0x03 line.long 0x00 "SECSTAT,Security Status Register" bitfld.long 0x00 19. " TBOSEC ,ECC single error correction in TBO data" "No error,Error" bitfld.long 0x00 18. " TBODED ,ECC double error detection in TBO data" "No error,Error" bitfld.long 0x00 17. " ECCSEC ,ECC single Error correction when fetching security marker" "No error,Error" bitfld.long 0x00 16. " ECCDED ,ECC double error detection when fetching security marker" "No error,Error" newline bitfld.long 0x00 8. " UMV ,Specification of the unlock marker value" "Non-trivial,Trivial" bitfld.long 0x00 5. " SFDONE ,Security fetch done register" "Ongoing,Finished" bitfld.long 0x00 4. " SWPOE ,Sector write permission overwrite enable register" "Disabled,Enabled" bitfld.long 0x00 3. " SECOE ,Security overwrite enable register" "Disabled,Enabled" newline bitfld.long 0x00 2. " CEEN ,Chip erase enable register" "Disabled,Enabled" bitfld.long 0x00 1. " SECSC ,Security scope register" "Flash,Device" bitfld.long 0x00 0. " SECEN ,Security enable register" "Disabled,Enabled" endif group.long 0xC4++0x13 line.long 0x00 "SER,Security Enable Register" line.long 0x04 "SSR,Security Scope Register" line.long 0x08 "CEER,Chip Erase Enable Register" line.long 0x0C "SOER,Security Overwrite Enable Register" line.long 0x10 "SWPOER,Sector Write Permission Overwrite Enable Register" group.long 0x40++0x07 line.long 0x00 "WSWP0,Work Flash Sector Write Permissions Register 0" bitfld.long 0x00 31. " WSWP_[31] ,Work flash sector write permission SA31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Work flash sector write permission SA30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Work flash sector write permission SA29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Work flash sector write permission SA28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Work flash sector write permission SA27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Work flash sector write permission SA26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Work flash sector write permission SA25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Work flash sector write permission SA24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Work flash sector write permission SA23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Work flash sector write permission SA22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Work flash sector write permission SA21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Work flash sector write permission SA20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Work flash sector write permission SA19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Work flash sector write permission SA18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Work flash sector write permission SA17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Work flash sector write permission SA16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Work flash sector write permission SA15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Work flash sector write permission SA14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Work flash sector write permission SA13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Work flash sector write permission SA12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Work flash sector write permission SA11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Work flash sector write permission SA10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Work flash sector write permission SA9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Work flash sector write permission SA8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Work flash sector write permission SA7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Work flash sector write permission SA6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Work flash sector write permission SA5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Work flash sector write permission SA4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Work flash sector write permission SA3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Work flash sector write permission SA2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Work flash sector write permission SA1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Work flash sector write permission SA0" "Disabled,Enabled" line.long 0x04 "WSWP1,Work Flash Sector Write Permissions Register 1" bitfld.long 0x04 31. " WSWP_[63] ,Work flash sector write permission SA63" "Disabled,Enabled" bitfld.long 0x04 30. " [62] ,Work flash sector write permission SA62" "Disabled,Enabled" bitfld.long 0x04 29. " [61] ,Work flash sector write permission SA61" "Disabled,Enabled" bitfld.long 0x04 28. " [60] ,Work flash sector write permission SA60" "Disabled,Enabled" newline bitfld.long 0x04 27. " [59] ,Work flash sector write permission SA59" "Disabled,Enabled" bitfld.long 0x04 26. " [58] ,Work flash sector write permission SA58" "Disabled,Enabled" bitfld.long 0x04 25. " [57] ,Work flash sector write permission SA57" "Disabled,Enabled" bitfld.long 0x04 24. " [56] ,Work flash sector write permission SA56" "Disabled,Enabled" newline bitfld.long 0x04 23. " [55] ,Work flash sector write permission SA55" "Disabled,Enabled" bitfld.long 0x04 22. " [54] ,Work flash sector write permission SA54" "Disabled,Enabled" bitfld.long 0x04 21. " [53] ,Work flash sector write permission SA53" "Disabled,Enabled" bitfld.long 0x04 20. " [52] ,Work flash sector write permission SA52" "Disabled,Enabled" newline bitfld.long 0x04 19. " [51] ,Work flash sector write permission SA51" "Disabled,Enabled" bitfld.long 0x04 18. " [50] ,Work flash sector write permission SA50" "Disabled,Enabled" bitfld.long 0x04 17. " [49] ,Work flash sector write permission SA49" "Disabled,Enabled" bitfld.long 0x04 16. " [48] ,Work flash sector write permission SA48" "Disabled,Enabled" newline bitfld.long 0x04 15. " [47] ,Work flash sector write permission SA47" "Disabled,Enabled" bitfld.long 0x04 14. " [46] ,Work flash sector write permission SA46" "Disabled,Enabled" bitfld.long 0x04 13. " [45] ,Work flash sector write permission SA45" "Disabled,Enabled" bitfld.long 0x04 12. " [44] ,Work flash sector write permission SA44" "Disabled,Enabled" newline bitfld.long 0x04 11. " [43] ,Work flash sector write permission SA43" "Disabled,Enabled" bitfld.long 0x04 10. " [42] ,Work flash sector write permission SA42" "Disabled,Enabled" bitfld.long 0x04 9. " [41] ,Work flash sector write permission SA41" "Disabled,Enabled" bitfld.long 0x04 8. " [40] ,Work flash sector write permission SA40" "Disabled,Enabled" newline bitfld.long 0x04 7. " [39] ,Work flash sector write permission SA39" "Disabled,Enabled" bitfld.long 0x04 6. " [38] ,Work flash sector write permission SA38" "Disabled,Enabled" bitfld.long 0x04 5. " [37] ,Work flash sector write permission SA37" "Disabled,Enabled" bitfld.long 0x04 4. " [36] ,Work flash sector write permission SA36" "Disabled,Enabled" newline bitfld.long 0x04 3. " [35] ,Work flash sector write permission SA35" "Disabled,Enabled" bitfld.long 0x04 2. " [34] ,Work flash sector write permission SA34" "Disabled,Enabled" bitfld.long 0x04 1. " [33] ,Work flash sector write permission SA33" "Disabled,Enabled" bitfld.long 0x04 0. " [32] ,Work flash sector write permission SA32" "Disabled,Enabled" group.long 0xDC++0x03 line.long 0x00 "CSWP0,Code Flash Small Sector Write Permissions Register 0" bitfld.long 0x00 31. " F3SWP_[7] ,Code flash small sector write permission SA7" "Disabled,Enabled" bitfld.long 0x00 30. " [6] ,Code flash small sector write permission SA6" "Disabled,Enabled" bitfld.long 0x00 29. " [5] ,Code flash small sector write permission SA5" "Disabled,Enabled" bitfld.long 0x00 28. " [4] ,Code flash small sector write permission SA4" "Disabled,Enabled" newline bitfld.long 0x00 27. " [3] ,Code flash small sector write permission SA3" "Disabled,Enabled" bitfld.long 0x00 26. " [2] ,Code flash small sector write permission SA2" "Disabled,Enabled" bitfld.long 0x00 25. " [1] ,Code flash small sector write permission SA1" "Disabled,Enabled" bitfld.long 0x00 24. " [0] ,Code flash small sector write permission SA0" "Disabled,Enabled" newline bitfld.long 0x00 23. " F2SWP_[7] ,Code flash small sector write permission SA7" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,Code flash small sector write permission SA6" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,Code flash small sector write permission SA5" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,Code flash small sector write permission SA4" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,Code flash small sector write permission SA3" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,Code flash small sector write permission SA2" "Disabled,Enabled" bitfld.long 0x00 17. " [1] ,Code flash small sector write permission SA1" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,Code flash small sector write permission SA0" "Disabled,Enabled" newline bitfld.long 0x00 15. " F1SWP_[7] ,Code flash small sector write permission SA7" "Disabled,Enabled" bitfld.long 0x00 14. " [6] ,Code flash small sector write permission SA6" "Disabled,Enabled" bitfld.long 0x00 13. " [5] ,Code flash small sector write permission SA5" "Disabled,Enabled" bitfld.long 0x00 12. " [4] ,Code flash small sector write permission SA4" "Disabled,Enabled" newline bitfld.long 0x00 11. " [3] ,Code flash small sector write permission SA3" "Disabled,Enabled" bitfld.long 0x00 10. " [2] ,Code flash small sector write permission SA2" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Code flash small sector write permission SA1" "Disabled,Enabled" bitfld.long 0x00 8. " [0] ,Code flash small sector write permission SA0" "Disabled,Enabled" newline bitfld.long 0x00 7. " F0SWP_[7] ,Code flash small sector write permission SA7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Code flash small sector write permission SA6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Code flash small sector write permission SA5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Code flash small sector write permission SA4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Code flash small sector write permission SA3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Code flash small sector write permission SA2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Code flash small sector write permission SA1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Code flash small sector write permission SA0" "Disabled,Enabled" group.long 0x80++0x1F line.long 0x00 "CSWP1,Code Flash Large Sector Write Permissions Register 1" bitfld.long 0x00 31. " SWP_[39] ,Work flash large sector write permission SA39" "Disabled,Enabled" bitfld.long 0x00 30. " [38] ,Work flash large sector write permission SA38" "Disabled,Enabled" bitfld.long 0x00 29. " [37] ,Work flash large sector write permission SA37" "Disabled,Enabled" bitfld.long 0x00 28. " [36] ,Work flash large sector write permission SA36" "Disabled,Enabled" newline bitfld.long 0x00 27. " [35] ,Work flash large sector write permission SA35" "Disabled,Enabled" bitfld.long 0x00 26. " [34] ,Work flash large sector write permission SA34" "Disabled,Enabled" bitfld.long 0x00 25. " [33] ,Work flash large sector write permission SA33" "Disabled,Enabled" bitfld.long 0x00 24. " [32] ,Work flash large sector write permission SA32" "Disabled,Enabled" newline bitfld.long 0x00 23. " [31] ,Work flash large sector write permission SA31" "Disabled,Enabled" bitfld.long 0x00 22. " [30] ,Work flash large sector write permission SA30" "Disabled,Enabled" bitfld.long 0x00 21. " [29] ,Work flash large sector write permission SA29" "Disabled,Enabled" bitfld.long 0x00 20. " [28] ,Work flash large sector write permission SA28" "Disabled,Enabled" newline bitfld.long 0x00 19. " [27] ,Work flash large sector write permission SA27" "Disabled,Enabled" bitfld.long 0x00 18. " [26] ,Work flash large sector write permission SA26" "Disabled,Enabled" bitfld.long 0x00 17. " [25] ,Work flash large sector write permission SA25" "Disabled,Enabled" bitfld.long 0x00 16. " [24] ,Work flash large sector write permission SA24" "Disabled,Enabled" newline bitfld.long 0x00 15. " [23] ,Work flash large sector write permission SA23" "Disabled,Enabled" bitfld.long 0x00 14. " [22] ,Work flash large sector write permission SA22" "Disabled,Enabled" bitfld.long 0x00 13. " [21] ,Work flash large sector write permission SA21" "Disabled,Enabled" bitfld.long 0x00 12. " [20] ,Work flash large sector write permission SA20" "Disabled,Enabled" newline bitfld.long 0x00 11. " [19] ,Work flash large sector write permission SA19" "Disabled,Enabled" bitfld.long 0x00 10. " [18] ,Work flash large sector write permission SA18" "Disabled,Enabled" bitfld.long 0x00 9. " [17] ,Work flash large sector write permission SA17" "Disabled,Enabled" bitfld.long 0x00 8. " [16] ,Work flash large sector write permission SA16" "Disabled,Enabled" newline bitfld.long 0x00 7. " [15] ,Work flash large sector write permission SA15" "Disabled,Enabled" bitfld.long 0x00 6. " [14] ,Work flash large sector write permission SA14" "Disabled,Enabled" bitfld.long 0x00 5. " [13] ,Work flash large sector write permission SA13" "Disabled,Enabled" bitfld.long 0x00 4. " [12] ,Work flash large sector write permission SA12" "Disabled,Enabled" newline bitfld.long 0x00 3. " [11] ,Work flash large sector write permission SA11" "Disabled,Enabled" bitfld.long 0x00 2. " [10] ,Work flash large sector write permission SA10" "Disabled,Enabled" bitfld.long 0x00 1. " [9] ,Work flash large sector write permission SA9" "Disabled,Enabled" bitfld.long 0x00 0. " [8] ,Work flash large sector write permission SA8" "Disabled,Enabled" line.long 0x04 "CSWP2,Code Flash Large Sector Write Permissions Register 2" bitfld.long 0x04 31. " SWP_[71] ,Work flash large sector write permission SA71" "Disabled,Enabled" bitfld.long 0x04 30. " [70] ,Work flash large sector write permission SA70" "Disabled,Enabled" bitfld.long 0x04 29. " [69] ,Work flash large sector write permission SA69" "Disabled,Enabled" bitfld.long 0x04 28. " [68] ,Work flash large sector write permission SA68" "Disabled,Enabled" newline bitfld.long 0x04 27. " [67] ,Work flash large sector write permission SA67" "Disabled,Enabled" bitfld.long 0x04 26. " [66] ,Work flash large sector write permission SA66" "Disabled,Enabled" bitfld.long 0x04 25. " [65] ,Work flash large sector write permission SA65" "Disabled,Enabled" bitfld.long 0x04 24. " [64] ,Work flash large sector write permission SA64" "Disabled,Enabled" newline bitfld.long 0x04 23. " [63] ,Work flash large sector write permission SA63" "Disabled,Enabled" bitfld.long 0x04 22. " [62] ,Work flash large sector write permission SA62" "Disabled,Enabled" bitfld.long 0x04 21. " [61] ,Work flash large sector write permission SA61" "Disabled,Enabled" bitfld.long 0x04 20. " [60] ,Work flash large sector write permission SA60" "Disabled,Enabled" newline bitfld.long 0x04 19. " [59] ,Work flash large sector write permission SA59" "Disabled,Enabled" bitfld.long 0x04 18. " [58] ,Work flash large sector write permission SA58" "Disabled,Enabled" bitfld.long 0x04 17. " [57] ,Work flash large sector write permission SA57" "Disabled,Enabled" bitfld.long 0x04 16. " [56] ,Work flash large sector write permission SA56" "Disabled,Enabled" newline bitfld.long 0x04 15. " [55] ,Work flash large sector write permission SA55" "Disabled,Enabled" bitfld.long 0x04 14. " [54] ,Work flash large sector write permission SA54" "Disabled,Enabled" bitfld.long 0x04 13. " [53] ,Work flash large sector write permission SA53" "Disabled,Enabled" bitfld.long 0x04 12. " [52] ,Work flash large sector write permission SA52" "Disabled,Enabled" newline bitfld.long 0x04 11. " [51] ,Work flash large sector write permission SA51" "Disabled,Enabled" bitfld.long 0x04 10. " [50] ,Work flash large sector write permission SA50" "Disabled,Enabled" bitfld.long 0x04 9. " [49] ,Work flash large sector write permission SA49" "Disabled,Enabled" bitfld.long 0x04 8. " [48] ,Work flash large sector write permission SA48" "Disabled,Enabled" newline bitfld.long 0x04 7. " [47] ,Work flash large sector write permission SA47" "Disabled,Enabled" bitfld.long 0x04 6. " [46] ,Work flash large sector write permission SA46" "Disabled,Enabled" bitfld.long 0x04 5. " [45] ,Work flash large sector write permission SA45" "Disabled,Enabled" bitfld.long 0x04 4. " [44] ,Work flash large sector write permission SA44" "Disabled,Enabled" newline bitfld.long 0x04 3. " [43] ,Work flash large sector write permission SA43" "Disabled,Enabled" bitfld.long 0x04 2. " [42] ,Work flash large sector write permission SA42" "Disabled,Enabled" bitfld.long 0x04 1. " [41] ,Work flash large sector write permission SA41" "Disabled,Enabled" bitfld.long 0x04 0. " [40] ,Work flash large sector write permission SA40" "Disabled,Enabled" line.long 0x08 "CSWP3,Code Flash Large Sector Write Permissions Register 3" bitfld.long 0x08 31. " SWP_[103] ,Work flash large sector write permission SA103" "Disabled,Enabled" bitfld.long 0x08 30. " [102] ,Work flash large sector write permission SA102" "Disabled,Enabled" bitfld.long 0x08 29. " [101] ,Work flash large sector write permission SA101" "Disabled,Enabled" bitfld.long 0x08 28. " [100] ,Work flash large sector write permission SA100" "Disabled,Enabled" newline bitfld.long 0x08 27. " [99] ,Work flash large sector write permission SA99" "Disabled,Enabled" bitfld.long 0x08 26. " [98] ,Work flash large sector write permission SA98" "Disabled,Enabled" bitfld.long 0x08 25. " [97] ,Work flash large sector write permission SA97" "Disabled,Enabled" bitfld.long 0x08 24. " [96] ,Work flash large sector write permission SA96" "Disabled,Enabled" newline bitfld.long 0x08 23. " [95] ,Work flash large sector write permission SA95" "Disabled,Enabled" bitfld.long 0x08 22. " [94] ,Work flash large sector write permission SA94" "Disabled,Enabled" bitfld.long 0x08 21. " [93] ,Work flash large sector write permission SA93" "Disabled,Enabled" bitfld.long 0x08 20. " [92] ,Work flash large sector write permission SA92" "Disabled,Enabled" newline bitfld.long 0x08 19. " [91] ,Work flash large sector write permission SA91" "Disabled,Enabled" bitfld.long 0x08 18. " [90] ,Work flash large sector write permission SA90" "Disabled,Enabled" bitfld.long 0x08 17. " [89] ,Work flash large sector write permission SA89" "Disabled,Enabled" bitfld.long 0x08 16. " [88] ,Work flash large sector write permission SA88" "Disabled,Enabled" newline bitfld.long 0x08 15. " [87] ,Work flash large sector write permission SA87" "Disabled,Enabled" bitfld.long 0x08 14. " [86] ,Work flash large sector write permission SA86" "Disabled,Enabled" bitfld.long 0x08 13. " [85] ,Work flash large sector write permission SA85" "Disabled,Enabled" bitfld.long 0x08 12. " [84] ,Work flash large sector write permission SA84" "Disabled,Enabled" newline bitfld.long 0x08 11. " [83] ,Work flash large sector write permission SA83" "Disabled,Enabled" bitfld.long 0x08 10. " [82] ,Work flash large sector write permission SA82" "Disabled,Enabled" bitfld.long 0x08 9. " [81] ,Work flash large sector write permission SA81" "Disabled,Enabled" bitfld.long 0x08 8. " [80] ,Work flash large sector write permission SA80" "Disabled,Enabled" newline bitfld.long 0x08 7. " [79] ,Work flash large sector write permission SA79" "Disabled,Enabled" bitfld.long 0x08 6. " [78] ,Work flash large sector write permission SA78" "Disabled,Enabled" bitfld.long 0x08 5. " [77] ,Work flash large sector write permission SA77" "Disabled,Enabled" bitfld.long 0x08 4. " [76] ,Work flash large sector write permission SA76" "Disabled,Enabled" newline bitfld.long 0x08 3. " [75] ,Work flash large sector write permission SA75" "Disabled,Enabled" bitfld.long 0x08 2. " [74] ,Work flash large sector write permission SA74" "Disabled,Enabled" bitfld.long 0x08 1. " [73] ,Work flash large sector write permission SA73" "Disabled,Enabled" bitfld.long 0x08 0. " [72] ,Work flash large sector write permission SA72" "Disabled,Enabled" line.long 0x0C "CSWP4,Code Flash Large Sector Write Permissions Register 4" bitfld.long 0x0C 31. " SWP_[135] ,Work flash large sector write permission SA135" "Disabled,Enabled" bitfld.long 0x0C 30. " [134] ,Work flash large sector write permission SA134" "Disabled,Enabled" bitfld.long 0x0C 29. " [133] ,Work flash large sector write permission SA133" "Disabled,Enabled" bitfld.long 0x0C 28. " [132] ,Work flash large sector write permission SA132" "Disabled,Enabled" newline bitfld.long 0x0C 27. " [131] ,Work flash large sector write permission SA131" "Disabled,Enabled" bitfld.long 0x0C 26. " [130] ,Work flash large sector write permission SA130" "Disabled,Enabled" bitfld.long 0x0C 25. " [129] ,Work flash large sector write permission SA129" "Disabled,Enabled" bitfld.long 0x0C 24. " [128] ,Work flash large sector write permission SA128" "Disabled,Enabled" newline bitfld.long 0x0C 23. " [127] ,Work flash large sector write permission SA127" "Disabled,Enabled" bitfld.long 0x0C 22. " [126] ,Work flash large sector write permission SA126" "Disabled,Enabled" bitfld.long 0x0C 21. " [125] ,Work flash large sector write permission SA125" "Disabled,Enabled" bitfld.long 0x0C 20. " [124] ,Work flash large sector write permission SA124" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [123] ,Work flash large sector write permission SA123" "Disabled,Enabled" bitfld.long 0x0C 18. " [122] ,Work flash large sector write permission SA122" "Disabled,Enabled" bitfld.long 0x0C 17. " [121] ,Work flash large sector write permission SA121" "Disabled,Enabled" bitfld.long 0x0C 16. " [120] ,Work flash large sector write permission SA120" "Disabled,Enabled" newline bitfld.long 0x0C 15. " [119] ,Work flash large sector write permission SA119" "Disabled,Enabled" bitfld.long 0x0C 14. " [118] ,Work flash large sector write permission SA118" "Disabled,Enabled" bitfld.long 0x0C 13. " [117] ,Work flash large sector write permission SA117" "Disabled,Enabled" bitfld.long 0x0C 12. " [116] ,Work flash large sector write permission SA116" "Disabled,Enabled" newline bitfld.long 0x0C 11. " [115] ,Work flash large sector write permission SA115" "Disabled,Enabled" bitfld.long 0x0C 10. " [114] ,Work flash large sector write permission SA114" "Disabled,Enabled" bitfld.long 0x0C 9. " [113] ,Work flash large sector write permission SA113" "Disabled,Enabled" bitfld.long 0x0C 8. " [112] ,Work flash large sector write permission SA112" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [111] ,Work flash large sector write permission SA111" "Disabled,Enabled" bitfld.long 0x0C 6. " [110] ,Work flash large sector write permission SA110" "Disabled,Enabled" bitfld.long 0x0C 5. " [109] ,Work flash large sector write permission SA109" "Disabled,Enabled" bitfld.long 0x0C 4. " [108] ,Work flash large sector write permission SA108" "Disabled,Enabled" newline bitfld.long 0x0C 3. " [107] ,Work flash large sector write permission SA107" "Disabled,Enabled" bitfld.long 0x0C 2. " [106] ,Work flash large sector write permission SA106" "Disabled,Enabled" bitfld.long 0x0C 1. " [105] ,Work flash large sector write permission SA105" "Disabled,Enabled" bitfld.long 0x0C 0. " [104] ,Work flash large sector write permission SA104" "Disabled,Enabled" line.long 0x10 "CSWP5,Code Flash Large Sector Write Permissions Register 5" bitfld.long 0x10 31. " SWP_[39] ,Work flash large sector write permission SA39" "Disabled,Enabled" bitfld.long 0x10 30. " [38] ,Work flash large sector write permission SA38" "Disabled,Enabled" bitfld.long 0x10 29. " [37] ,Work flash large sector write permission SA37" "Disabled,Enabled" bitfld.long 0x10 28. " [36] ,Work flash large sector write permission SA36" "Disabled,Enabled" newline bitfld.long 0x10 27. " [35] ,Work flash large sector write permission SA35" "Disabled,Enabled" bitfld.long 0x10 26. " [34] ,Work flash large sector write permission SA34" "Disabled,Enabled" bitfld.long 0x10 25. " [33] ,Work flash large sector write permission SA33" "Disabled,Enabled" bitfld.long 0x10 24. " [32] ,Work flash large sector write permission SA32" "Disabled,Enabled" newline bitfld.long 0x10 23. " [31] ,Work flash large sector write permission SA31" "Disabled,Enabled" bitfld.long 0x10 22. " [30] ,Work flash large sector write permission SA30" "Disabled,Enabled" bitfld.long 0x10 21. " [29] ,Work flash large sector write permission SA29" "Disabled,Enabled" bitfld.long 0x10 20. " [28] ,Work flash large sector write permission SA28" "Disabled,Enabled" newline bitfld.long 0x10 19. " [27] ,Work flash large sector write permission SA27" "Disabled,Enabled" bitfld.long 0x10 18. " [26] ,Work flash large sector write permission SA26" "Disabled,Enabled" bitfld.long 0x10 17. " [25] ,Work flash large sector write permission SA25" "Disabled,Enabled" bitfld.long 0x10 16. " [24] ,Work flash large sector write permission SA24" "Disabled,Enabled" newline bitfld.long 0x10 15. " [23] ,Work flash large sector write permission SA23" "Disabled,Enabled" bitfld.long 0x10 14. " [22] ,Work flash large sector write permission SA22" "Disabled,Enabled" bitfld.long 0x10 13. " [21] ,Work flash large sector write permission SA21" "Disabled,Enabled" bitfld.long 0x10 12. " [20] ,Work flash large sector write permission SA20" "Disabled,Enabled" newline bitfld.long 0x10 11. " [19] ,Work flash large sector write permission SA19" "Disabled,Enabled" bitfld.long 0x10 10. " [18] ,Work flash large sector write permission SA18" "Disabled,Enabled" bitfld.long 0x10 9. " [17] ,Work flash large sector write permission SA17" "Disabled,Enabled" bitfld.long 0x10 8. " [16] ,Work flash large sector write permission SA16" "Disabled,Enabled" newline bitfld.long 0x10 7. " [15] ,Work flash large sector write permission SA15" "Disabled,Enabled" bitfld.long 0x10 6. " [14] ,Work flash large sector write permission SA14" "Disabled,Enabled" bitfld.long 0x10 5. " [13] ,Work flash large sector write permission SA13" "Disabled,Enabled" bitfld.long 0x10 4. " [12] ,Work flash large sector write permission SA12" "Disabled,Enabled" newline bitfld.long 0x10 3. " [11] ,Work flash large sector write permission SA11" "Disabled,Enabled" bitfld.long 0x10 2. " [10] ,Work flash large sector write permission SA10" "Disabled,Enabled" bitfld.long 0x10 1. " [9] ,Work flash large sector write permission SA9" "Disabled,Enabled" bitfld.long 0x10 0. " [8] ,Work flash large sector write permission SA8" "Disabled,Enabled" line.long 0x14 "CSWP6,Code Flash Large Sector Write Permissions Register 6" bitfld.long 0x14 31. " SWP_[71] ,Work flash large sector write permission SA71" "Disabled,Enabled" bitfld.long 0x14 30. " [70] ,Work flash large sector write permission SA70" "Disabled,Enabled" bitfld.long 0x14 29. " [69] ,Work flash large sector write permission SA69" "Disabled,Enabled" bitfld.long 0x14 28. " [68] ,Work flash large sector write permission SA68" "Disabled,Enabled" newline bitfld.long 0x14 27. " [67] ,Work flash large sector write permission SA67" "Disabled,Enabled" bitfld.long 0x14 26. " [66] ,Work flash large sector write permission SA66" "Disabled,Enabled" bitfld.long 0x14 25. " [65] ,Work flash large sector write permission SA65" "Disabled,Enabled" bitfld.long 0x14 24. " [64] ,Work flash large sector write permission SA64" "Disabled,Enabled" newline bitfld.long 0x14 23. " [63] ,Work flash large sector write permission SA63" "Disabled,Enabled" bitfld.long 0x14 22. " [62] ,Work flash large sector write permission SA62" "Disabled,Enabled" bitfld.long 0x14 21. " [61] ,Work flash large sector write permission SA61" "Disabled,Enabled" bitfld.long 0x14 20. " [60] ,Work flash large sector write permission SA60" "Disabled,Enabled" newline bitfld.long 0x14 19. " [59] ,Work flash large sector write permission SA59" "Disabled,Enabled" bitfld.long 0x14 18. " [58] ,Work flash large sector write permission SA58" "Disabled,Enabled" bitfld.long 0x14 17. " [57] ,Work flash large sector write permission SA57" "Disabled,Enabled" bitfld.long 0x14 16. " [56] ,Work flash large sector write permission SA56" "Disabled,Enabled" newline bitfld.long 0x14 15. " [55] ,Work flash large sector write permission SA55" "Disabled,Enabled" bitfld.long 0x14 14. " [54] ,Work flash large sector write permission SA54" "Disabled,Enabled" bitfld.long 0x14 13. " [53] ,Work flash large sector write permission SA53" "Disabled,Enabled" bitfld.long 0x14 12. " [52] ,Work flash large sector write permission SA52" "Disabled,Enabled" newline bitfld.long 0x14 11. " [51] ,Work flash large sector write permission SA51" "Disabled,Enabled" bitfld.long 0x14 10. " [50] ,Work flash large sector write permission SA50" "Disabled,Enabled" bitfld.long 0x14 9. " [49] ,Work flash large sector write permission SA49" "Disabled,Enabled" bitfld.long 0x14 8. " [48] ,Work flash large sector write permission SA48" "Disabled,Enabled" newline bitfld.long 0x14 7. " [47] ,Work flash large sector write permission SA47" "Disabled,Enabled" bitfld.long 0x14 6. " [46] ,Work flash large sector write permission SA46" "Disabled,Enabled" bitfld.long 0x14 5. " [45] ,Work flash large sector write permission SA45" "Disabled,Enabled" bitfld.long 0x14 4. " [44] ,Work flash large sector write permission SA44" "Disabled,Enabled" newline bitfld.long 0x14 3. " [43] ,Work flash large sector write permission SA43" "Disabled,Enabled" bitfld.long 0x14 2. " [42] ,Work flash large sector write permission SA42" "Disabled,Enabled" bitfld.long 0x14 1. " [41] ,Work flash large sector write permission SA41" "Disabled,Enabled" bitfld.long 0x14 0. " [40] ,Work flash large sector write permission SA40" "Disabled,Enabled" line.long 0x18 "CSWP7,Code Flash Large Sector Write Permissions Register 7" bitfld.long 0x18 31. " SWP_[103] ,Work flash large sector write permission SA103" "Disabled,Enabled" bitfld.long 0x18 30. " [102] ,Work flash large sector write permission SA102" "Disabled,Enabled" bitfld.long 0x18 29. " [101] ,Work flash large sector write permission SA101" "Disabled,Enabled" bitfld.long 0x18 28. " [100] ,Work flash large sector write permission SA100" "Disabled,Enabled" newline bitfld.long 0x18 27. " [99] ,Work flash large sector write permission SA99" "Disabled,Enabled" bitfld.long 0x18 26. " [98] ,Work flash large sector write permission SA98" "Disabled,Enabled" bitfld.long 0x18 25. " [97] ,Work flash large sector write permission SA97" "Disabled,Enabled" bitfld.long 0x18 24. " [96] ,Work flash large sector write permission SA96" "Disabled,Enabled" newline bitfld.long 0x18 23. " [95] ,Work flash large sector write permission SA95" "Disabled,Enabled" bitfld.long 0x18 22. " [94] ,Work flash large sector write permission SA94" "Disabled,Enabled" bitfld.long 0x18 21. " [93] ,Work flash large sector write permission SA93" "Disabled,Enabled" bitfld.long 0x18 20. " [92] ,Work flash large sector write permission SA92" "Disabled,Enabled" newline bitfld.long 0x18 19. " [91] ,Work flash large sector write permission SA91" "Disabled,Enabled" bitfld.long 0x18 18. " [90] ,Work flash large sector write permission SA90" "Disabled,Enabled" bitfld.long 0x18 17. " [89] ,Work flash large sector write permission SA89" "Disabled,Enabled" bitfld.long 0x18 16. " [88] ,Work flash large sector write permission SA88" "Disabled,Enabled" newline bitfld.long 0x18 15. " [87] ,Work flash large sector write permission SA87" "Disabled,Enabled" bitfld.long 0x18 14. " [86] ,Work flash large sector write permission SA86" "Disabled,Enabled" bitfld.long 0x18 13. " [85] ,Work flash large sector write permission SA85" "Disabled,Enabled" bitfld.long 0x18 12. " [84] ,Work flash large sector write permission SA84" "Disabled,Enabled" newline bitfld.long 0x18 11. " [83] ,Work flash large sector write permission SA83" "Disabled,Enabled" bitfld.long 0x18 10. " [82] ,Work flash large sector write permission SA82" "Disabled,Enabled" bitfld.long 0x18 9. " [81] ,Work flash large sector write permission SA81" "Disabled,Enabled" bitfld.long 0x18 8. " [80] ,Work flash large sector write permission SA80" "Disabled,Enabled" newline bitfld.long 0x18 7. " [79] ,Work flash large sector write permission SA79" "Disabled,Enabled" bitfld.long 0x18 6. " [78] ,Work flash large sector write permission SA78" "Disabled,Enabled" bitfld.long 0x18 5. " [77] ,Work flash large sector write permission SA77" "Disabled,Enabled" bitfld.long 0x18 4. " [76] ,Work flash large sector write permission SA76" "Disabled,Enabled" newline bitfld.long 0x18 3. " [75] ,Work flash large sector write permission SA75" "Disabled,Enabled" bitfld.long 0x18 2. " [74] ,Work flash large sector write permission SA74" "Disabled,Enabled" bitfld.long 0x18 1. " [73] ,Work flash large sector write permission SA73" "Disabled,Enabled" bitfld.long 0x18 0. " [72] ,Work flash large sector write permission SA72" "Disabled,Enabled" line.long 0x1C "CSWP8,Code Flash Large Sector Write Permissions Register 8" bitfld.long 0x1C 31. " SWP_[135] ,Work flash large sector write permission SA135" "Disabled,Enabled" bitfld.long 0x1C 30. " [134] ,Work flash large sector write permission SA134" "Disabled,Enabled" bitfld.long 0x1C 29. " [133] ,Work flash large sector write permission SA133" "Disabled,Enabled" bitfld.long 0x1C 28. " [132] ,Work flash large sector write permission SA132" "Disabled,Enabled" newline bitfld.long 0x1C 27. " [131] ,Work flash large sector write permission SA131" "Disabled,Enabled" bitfld.long 0x1C 26. " [130] ,Work flash large sector write permission SA130" "Disabled,Enabled" bitfld.long 0x1C 25. " [129] ,Work flash large sector write permission SA129" "Disabled,Enabled" bitfld.long 0x1C 24. " [128] ,Work flash large sector write permission SA128" "Disabled,Enabled" newline bitfld.long 0x1C 23. " [127] ,Work flash large sector write permission SA127" "Disabled,Enabled" bitfld.long 0x1C 22. " [126] ,Work flash large sector write permission SA126" "Disabled,Enabled" bitfld.long 0x1C 21. " [125] ,Work flash large sector write permission SA125" "Disabled,Enabled" bitfld.long 0x1C 20. " [124] ,Work flash large sector write permission SA124" "Disabled,Enabled" newline bitfld.long 0x1C 19. " [123] ,Work flash large sector write permission SA123" "Disabled,Enabled" bitfld.long 0x1C 18. " [122] ,Work flash large sector write permission SA122" "Disabled,Enabled" bitfld.long 0x1C 17. " [121] ,Work flash large sector write permission SA121" "Disabled,Enabled" bitfld.long 0x1C 16. " [120] ,Work flash large sector write permission SA120" "Disabled,Enabled" newline bitfld.long 0x1C 15. " [119] ,Work flash large sector write permission SA119" "Disabled,Enabled" bitfld.long 0x1C 14. " [118] ,Work flash large sector write permission SA118" "Disabled,Enabled" bitfld.long 0x1C 13. " [117] ,Work flash large sector write permission SA117" "Disabled,Enabled" bitfld.long 0x1C 12. " [116] ,Work flash large sector write permission SA116" "Disabled,Enabled" newline bitfld.long 0x1C 11. " [115] ,Work flash large sector write permission SA115" "Disabled,Enabled" bitfld.long 0x1C 10. " [114] ,Work flash large sector write permission SA114" "Disabled,Enabled" bitfld.long 0x1C 9. " [113] ,Work flash large sector write permission SA113" "Disabled,Enabled" bitfld.long 0x1C 8. " [112] ,Work flash large sector write permission SA112" "Disabled,Enabled" newline bitfld.long 0x1C 7. " [111] ,Work flash large sector write permission SA111" "Disabled,Enabled" bitfld.long 0x1C 6. " [110] ,Work flash large sector write permission SA110" "Disabled,Enabled" bitfld.long 0x1C 5. " [109] ,Work flash large sector write permission SA109" "Disabled,Enabled" bitfld.long 0x1C 4. " [108] ,Work flash large sector write permission SA108" "Disabled,Enabled" newline bitfld.long 0x1C 3. " [107] ,Work flash large sector write permission SA107" "Disabled,Enabled" bitfld.long 0x1C 2. " [106] ,Work flash large sector write permission SA106" "Disabled,Enabled" bitfld.long 0x1C 1. " [105] ,Work flash large sector write permission SA105" "Disabled,Enabled" bitfld.long 0x1C 0. " [104] ,Work flash large sector write permission SA104" "Disabled,Enabled" width 0x0B tree.end tree "MPU (Memory Protection Unit)" base ad:0xB4710000 width 8. if (((per.l(ad:0xB4710000))&0x10000)==0x10000) group.long 0x00++0x03 line.long 0x00 "CTRL0,MPU AXI Control Register" rbitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AHB enable status" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged,Privileged" rbitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled" rbitfld.long 0x00 10. " MPUSTOPEN ,MPU STOP feature enable" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU STOP status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" eventfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" else group.long 0x00++0x03 line.long 0x00 "CTRL0,AXI Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU AHB enable status" "Disabled,Enabled" newline bitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged,Privileged" bitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled" bitfld.long 0x00 10. " MPUSTOPEN ,MPU STOP feature enable" "Disabled,Enabled" newline rbitfld.long 0x00 9. " MPUSTOP ,MPU STOP status" "Not stopped,Stopped" rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" eventfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "No interrupt,Interrupt" endif group.long 0x04++0x03 line.long 0x00 "NMIEN,MPU AXI NMI Enable Register" bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled" rgroup.long 0x08++0x0F line.long 0x00 "WERRC,MPU AXI Write Error Control Register" bitfld.long 0x00 8.--10. " AWSIZE ,AXI transaction burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " AWBURST ,AXI transaction burst type" "0,1,2,3" bitfld.long 0x00 2.--5. " AWLEN ,AXI transaction burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " AWPROTPRIV ,AXI transaction privileged mode" "0,1" bitfld.long 0x00 0. " AWMPV ,AXI Write Memory Protection Violation" "0,1" line.long 0x04 "WERRA,MPU AXI Write Error Address Register" line.long 0x08 "RERRC,MPU AXI Read Error Control Register" bitfld.long 0x08 8.--10. " ARSIZE ,AXI transaction burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 6.--7. " ARBURST ,AXI transaction burst type" "0,1,2,3" bitfld.long 0x08 2.--5. " ARLEN ,AXI transaction burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 1. " ARPROTPRIV ,AXI transaction privileged mode" "0,1" bitfld.long 0x08 0. " ARMPV ,AXI Read Memory Protection Violation" "0,1" line.long 0x0C "RERRA,MPU AXI Read Error Address Register" sif (cpuis("S6J336*")||cpuis("S6J337*")||cpuis("S6J342*")||cpuis("S6J351*")) if (((per.l(ad:0xB4710000+0x18))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x18++0x03 line.long 0x00 "CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x24))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x24++0x03 line.long 0x00 "CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x30))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x30++0x03 line.long 0x00 "CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x30++0x03 line.long 0x00 "CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x3C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x3C++0x03 line.long 0x00 "CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x48))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x48++0x03 line.long 0x00 "CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x48++0x03 line.long 0x00 "CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x54))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x54++0x03 line.long 0x00 "CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x60))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x60++0x03 line.long 0x00 "CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x60++0x03 line.long 0x00 "CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x6C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x6C++0x03 line.long 0x00 "CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x6C++0x03 line.long 0x00 "CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif if (((per.l(ad:0xB4710000+0x18))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x1C++0x03 line.long 0x00 "SADDR1,MPU AXI Start Address Register 1" else group.long 0x1C++0x03 line.long 0x00 "SADDR1,MPU AXI Start Address Register 1" endif if (((per.l(ad:0xB4710000+0x24))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x28++0x03 line.long 0x00 "SADDR2,MPU AXI Start Address Register 2" else group.long 0x28++0x03 line.long 0x00 "SADDR2,MPU AXI Start Address Register 2" endif if (((per.l(ad:0xB4710000+0x30))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x34++0x03 line.long 0x00 "SADDR3,MPU AXI Start Address Register 3" else group.long 0x34++0x03 line.long 0x00 "SADDR3,MPU AXI Start Address Register 3" endif if (((per.l(ad:0xB4710000+0x3C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x40++0x03 line.long 0x00 "SADDR4,MPU AXI Start Address Register 4" else group.long 0x40++0x03 line.long 0x00 "SADDR4,MPU AXI Start Address Register 4" endif if (((per.l(ad:0xB4710000+0x48))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x4C++0x03 line.long 0x00 "SADDR5,MPU AXI Start Address Register 5" else group.long 0x4C++0x03 line.long 0x00 "SADDR5,MPU AXI Start Address Register 5" endif if (((per.l(ad:0xB4710000+0x54))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x58++0x03 line.long 0x00 "SADDR6,MPU AXI Start Address Register 6" else group.long 0x58++0x03 line.long 0x00 "SADDR6,MPU AXI Start Address Register 6" endif if (((per.l(ad:0xB4710000+0x60))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x64++0x03 line.long 0x00 "SADDR7,MPU AXI Start Address Register 7" else group.long 0x64++0x03 line.long 0x00 "SADDR7,MPU AXI Start Address Register 7" endif if (((per.l(ad:0xB4710000+0x6C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x70++0x03 line.long 0x00 "SADDR8,MPU AXI Start Address Register 8" else group.long 0x70++0x03 line.long 0x00 "SADDR8,MPU AXI Start Address Register 8" endif if (((per.l(ad:0xB4710000+0x18))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x20++0x03 line.long 0x00 "EADDR1,MPU AXI End Address Register 1" else group.long 0x20++0x03 line.long 0x00 "EADDR1,MPU AXI End Address Register 1" endif if (((per.l(ad:0xB4710000+0x24))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x2C++0x03 line.long 0x00 "EADDR2,MPU AXI End Address Register 2" else group.long 0x2C++0x03 line.long 0x00 "EADDR2,MPU AXI End Address Register 2" endif if (((per.l(ad:0xB4710000+0x30))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x38++0x03 line.long 0x00 "EADDR3,MPU AXI End Address Register 3" else group.long 0x38++0x03 line.long 0x00 "EADDR3,MPU AXI End Address Register 3" endif if (((per.l(ad:0xB4710000+0x3C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x44++0x03 line.long 0x00 "EADDR4,MPU AXI End Address Register 4" else group.long 0x44++0x03 line.long 0x00 "EADDR4,MPU AXI End Address Register 4" endif if (((per.l(ad:0xB4710000+0x48))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x50++0x03 line.long 0x00 "EADDR5,MPU AXI End Address Register 5" else group.long 0x50++0x03 line.long 0x00 "EADDR5,MPU AXI End Address Register 5" endif if (((per.l(ad:0xB4710000+0x54))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x5C++0x03 line.long 0x00 "EADDR6,MPU AXI End Address Register 6" else group.long 0x5C++0x03 line.long 0x00 "EADDR6,MPU AXI End Address Register 6" endif if (((per.l(ad:0xB4710000+0x60))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x68++0x03 line.long 0x00 "EADDR7,MPU AXI End Address Register 7" else group.long 0x68++0x03 line.long 0x00 "EADDR7,MPU AXI End Address Register 7" endif if (((per.l(ad:0xB4710000+0x6C))&0x01)==0x01)||(((per.l(ad:0xB4710000))&0x10000)==0x10000) rgroup.long 0x74++0x03 line.long 0x00 "EADDR8,MPU AXI End Address Register 8" else group.long 0x74++0x03 line.long 0x00 "EADDR8,MPU AXI End Address Register 8" endif else group.long 0x18++0x03 line.long 0x00 "CTRL1,MPU AXI Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "CTRL2,MPU AXI Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "CTRL3,MPU AXI Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x3C++0x03 line.long 0x00 "CTRL4,MPU AXI Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x48++0x03 line.long 0x00 "CTRL5,MPU AXI Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "CTRL6,MPU AXI Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x60++0x03 line.long 0x00 "CTRL7,MPU AXI Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x6C++0x03 line.long 0x00 "CTRL8,MPU AXI Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "SADDR1,MPU AXI Start Address Register 1" group.long 0x28++0x03 line.long 0x00 "SADDR2,MPU AXI Start Address Register 2" group.long 0x34++0x03 line.long 0x00 "SADDR3,MPU AXI Start Address Register 3" group.long 0x40++0x03 line.long 0x00 "SADDR4,MPU AXI Start Address Register 4" group.long 0x4C++0x03 line.long 0x00 "SADDR5,MPU AXI Start Address Register 5" group.long 0x58++0x03 line.long 0x00 "SADDR6,MPU AXI Start Address Register 6" group.long 0x64++0x03 line.long 0x00 "SADDR7,MPU AXI Start Address Register 7" group.long 0x70++0x03 line.long 0x00 "SADDR8,MPU AXI Start Address Register 8" group.long 0x20++0x03 line.long 0x00 "EADDR1,MPU AXI End Address Register 1" group.long 0x2C++0x03 line.long 0x00 "EADDR2,MPU AXI End Address Register 2" group.long 0x38++0x03 line.long 0x00 "EADDR3,MPU AXI End Address Register 3" group.long 0x44++0x03 line.long 0x00 "EADDR4,MPU AXI End Address Register 4" group.long 0x50++0x03 line.long 0x00 "EADDR5,MPU AXI End Address Register 5" group.long 0x5C++0x03 line.long 0x00 "EADDR6,MPU AXI End Address Register 6" group.long 0x68++0x03 line.long 0x00 "EADDR7,MPU AXI End Address Register 7" group.long 0x74++0x03 line.long 0x00 "EADDR8,MPU AXI End Address Register 8" endif group.long 0x78++0x03 line.long 0x00 "UNLOCK,MPU AXI Unlock Register" rgroup.long 0x7C++0x03 line.long 0x00 "MID,MPU AXI Module ID Register" width 0x0B tree.end tree "SHE (SECURE HARDWARE EXTENSION)" base ad:0xB2000000 width 13. if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x00++0x03 "Configuration Registers For The Command Interface" hide.long 0x00 "CMD,Command Register" elif (((per.l(ad:0xB2000000+0x0C))&0x01)==0x01)||(((per.l(ad:0xB2000000+0x04))&0x01)==0x01) rgroup.long 0x00++0x03 "Configuration Registers For The Command Interface" line.long 0x00 "CMD,Command Register" hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command opcode" else group.long 0x00++0x03 "Configuration Registers For The Command Interface" line.long 0x00 "CMD,Command Register" hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command opcode" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x04++0x03 hide.long 0x00 "CMDCANCEL,Command Cancel Register" else group.long 0x04++0x03 line.long 0x00 "CMDCANCEL,Command Cancel Register" bitfld.long 0x00 0. " CANCELREQ ,Cancel request bit" "Not canceled,Canceled" endif group.long 0x08++0x03 line.long 0x00 "CLKCTRL,Clock Control Register" bitfld.long 0x00 16. " DISREQ ,Clock disable request bit" "No,Yes" bitfld.long 0x00 0. " ENREQ ,Clock enable request bit" "Disabled,Enabled" if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x0C++0x03 "Status registers for the command interface" hide.long 0x00 "STATUS,Status Register" else rgroup.long 0x0C++0x03 "Status Registers For The Command Interface" line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 24. " FATALERR ,Fatal error flag" "No error,Error" bitfld.long 0x00 19. " FLASHDED ,Flash double bit ECC error flag" "No error,Error" bitfld.long 0x00 18. " FLASHSEC ,Flash single bit ECC warning flag" "Not occurred,Occurred" bitfld.long 0x00 17. " RAMDED ,RAM double bit ECC error flag" "No error,Error" newline bitfld.long 0x00 16. " RAMSEC ,RAM single bit ECC warning flag" "Not occurred,Occurred" bitfld.long 0x00 9. " INITDONE ,SHE initialization status flag" "Not finished,Finished" bitfld.long 0x00 8. " DONE ,Done status flag" "No error,Error" bitfld.long 0x00 7. " INTDEBUGGER ,Internal debugger status flag" "Not activated,Activated" newline bitfld.long 0x00 6. " EXTDEBUGGER ,External debugger status flag" "Not connected,Connected" bitfld.long 0x00 5. " RNDINIT ,Random seed initialization status flag" "Not initialized,Initialized" bitfld.long 0x00 4. " BOOTOK ,Boot OK status flag" "Failed,Succeed" bitfld.long 0x00 3. " BOOTFINISHED ,Boot finished status flag" "Not completed,Completed" newline bitfld.long 0x00 2. " BOOTINIT ,Boot initialization status flag" "Not personalized,Personalized" bitfld.long 0x00 1. " SECUREBOOT ,Secure boot activated status flag" "Not activated,Activated" bitfld.long 0x00 0. " BUSY ,Busy status flag" "Not busy,Busy" endif newline hgroup.long 0x10++0x03 hide.long 0x00 "ERC,Error Code Register" in newline rgroup.long 0x14++0x07 line.long 0x00 "CLKSTAT,Clock Status Register" bitfld.long 0x00 0. " CLKOFF ,Clock disabled flag" "No,Yes" line.long 0x04 "MID,Module ID Register" sif cpuis("S6J35*") rgroup.long 0x1C++0x03 "Interrupt Registers For Command Interface" line.long 0x00 "IRQ,Interrupt Request Register" bitfld.long 0x00 23. " FATALERR ,Fatal error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 22. " IFIFOLOCKERR ,Write to locked input FIFO interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 21. " OMSTIFSELERR ,Output data channel interface selection error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 20. " IMSTIFSELERR ,Input data channel interface selection error interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " OMSTERR ,Output channel master error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 18. " IMSTERR ,Input channel master error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 17. " OFIFORDERR ,Read from empty output FIFO error interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 16. " IFIFOWRERR ,Write to full input FIFO error interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " OFIFORDTH ,Output FIFO above threshold interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 4. " IFIFOWRTH ,Input FIFO below threshold interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 3. " OMSTIDLE ,Output channel master idle interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " IMSTIDLE ,Input channel master idle interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " DONE ,Command execution done interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 0. " COMPAREMATCH ,Compare match interrupt flag" "No interrupt,Interrupt" group.long 0x20++0x03 line.long 0x00 "IRQEN,Interrupt Request Enable Register" bitfld.long 0x00 23. " FATALERR ,Fatal error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " IFIFOLOCKERR ,Write to locked input FIFO interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " OMSTIFSELERR ,Output data channel interface selection error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " IMSTIFSELERR ,Input data channel interface selection error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " OMSTERR ,Output channel master error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " IMSTERR ,Input channel master error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " OFIFORDERR ,Read from empty output FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " IFIFOWRERR ,Write to full input FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " OFIFORDTH ,Output FIFO above threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IFIFOWRTH ,Input FIFO below threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " OMSTIDLE ,Output channel master idle interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " IMSTIDLE ,Input channel master idle interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " DONE ,Command execution done interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " COMPAREMATCH ,Compare match interrupt enable" "Disabled,Enabled" wgroup.long 0x24++0x03 line.long 0x00 "IRQEN,Interrupt Request Enable Register" bitfld.long 0x00 23. " FATALERR ,Fatal error interrupt clear" "No effect,Clear" bitfld.long 0x00 22. " IFIFOLOCKERR ,Write to locked input FIFO interrupt clear" "No effect,Clear" bitfld.long 0x00 21. " OMSTIFSELERR ,Output data channel interface selection error interrupt clear" "No effect,Clear" bitfld.long 0x00 20. " IMSTIFSELERR ,Input data channel interface selection error interrupt clear" "No effect,Clear" newline bitfld.long 0x00 19. " OMSTERR ,Output channel master error interrupt clear" "No effect,Clear" bitfld.long 0x00 18. " IMSTERR ,Input channel master error interrupt clear" "No effect,Clear" bitfld.long 0x00 17. " OFIFORDERR ,Read from empty output FIFO error interrupt clear" "No effect,Clear" bitfld.long 0x00 16. " IFIFOWRERR ,Write to full input FIFO error interrupt clear" "No effect,Clear" newline bitfld.long 0x00 5. " OFIFORDTH ,Output FIFO above threshold interrupt clear" "No effect,Clear" bitfld.long 0x00 4. " IFIFOWRTH ,Input FIFO below threshold interrupt clear" "No effect,Clear" bitfld.long 0x00 3. " OMSTIDLE ,Output channel master idle interrupt clear" "No effect,Clear" bitfld.long 0x00 2. " IMSTIDLE ,Input channel master idle interrupt clear" "No effect,Clear" newline bitfld.long 0x00 1. " DONE ,Command execution done interrupt clear" "No effect,Clear" bitfld.long 0x00 0. " COMPAREMATCH ,Compare match interrupt clear" "No effect,Clear" else group.long 0x1C++0x03 "Interrupt Registers For Command Interface" line.long 0x00 "IRQ_SET/CLR,Interrupt Request Register" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " FATALERR ,Fatal error interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " IFIFOLOCKERR ,Write to locked input FIFO interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " OMSTIFSELERR ,Output data channel interface selection error interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " IMSTIFSELERR ,Input data channel interface selection error interrupt flag" "Not occurred,Occurred" newline setclrfld.long 0x00 19. 0x04 19. 0x08 19. " OMSTERR ,Output channel master error interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " IMSTERR ,Input channel master error interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " OFIFORDERR ,Read from empty output FIFO error interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " IFIFOWRERR ,Write to full input FIFO error interrupt flag" "Not occurred,Occurred" newline setclrfld.long 0x00 05. 0x04 05. 0x08 05. " OFIFORDTH ,Output FIFO above threshold interrupt flag" "Not greater,Greater" setclrfld.long 0x00 04. 0x04 04. 0x08 04. " IFIFOWRTH ,Input FIFO below threshold interrupt flag" "Not less,Less" setclrfld.long 0x00 03. 0x04 03. 0x08 03. " OMSTIDLE ,Output channel master idle interrupt flag" "Not idle,Idle" setclrfld.long 0x00 02. 0x04 02. 0x08 02. " IMSTIDLE ,Input channel master idle interrupt" "Not idle,Idle" newline setclrfld.long 0x00 01. 0x04 01. 0x08 01. " DONE ,Command execution done interrupt flag" "Not finished,Finished" setclrfld.long 0x00 00. 0x04 00. 0x08 00. " COMPAREMATCH ,Compare match interrupt flag" "Not transferred,Transferred" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x28++0x03 "Configuration Registers For The Data Interface" hide.long 0x00 "IMSTADDR,Input Channel Master Start Address Register" else group.long 0x28++0x03 "Configuration Registers For The Data Interface" line.long 0x00 "IMSTADDR,Input Channel Master Start Address Register" sif cpuis("S6J35*") hexmask.long 0x00 3.--31. 0x08 " IMSTADDR ,Input channel master start address" endif endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x2C++0x03 hide.long 0x00 "OMSTADDR,Output Channel Master Start Address Register" else group.long 0x2C++0x03 line.long 0x00 "OMSTADDR,Output Channel Master Start Address Register" sif cpuis("S6J35*") hexmask.long 0x00 3.--31. 0x08 " OMSTADDR ,Output channel master start address" endif endif group.long 0x30++0x0F line.long 0x00 "IMSTCNT,Input Channel Master Data Transfer Counter" hexmask.long 0x00 0.--28. 1. " IMSTCNT ,Input channel master data transfer counter" line.long 0x04 "OMSTCNT,Out Channel Master Data Transfer Counter" hexmask.long 0x04 0.--28. 1. " OMSTCNT ,Output channel master data transfer counter" line.long 0x08 "IMSTSTART,Input Channel Master Start Trigger" bitfld.long 0x08 0. " IMSTSTART ,Input channel master start trigger" "Not started,Started" line.long 0x0C "OMSTSTART,Output Channel Master Start Trigger" bitfld.long 0x0C 0. " OMSTSTART ,Output channel master start trigger" "Not started,Started" if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x40++0x03 hide.long 0x00 "IFIFOCFG,Input FIFO Configuration Register" else group.long 0x40++0x03 line.long 0x00 "IFIFOCFG,Input FIFO Configuration Register" bitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command" bitfld.long 0x00 0.--5. " WRTHRESHOLD ,Programmable write threshold of input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x44++0x03 hide.long 0x00 "OFIFOCFG,Output FIFO Configuration Register" else group.long 0x44++0x03 line.long 0x00 "OFIFOCFG,Output FIFO Configuration Register" bitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command" bitfld.long 0x00 0.--5. " RDTHRESHOLD ,Programmable read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x48++0x03 hide.long 0x00 "COMPARE0,Input FIFO Compare Value Register" hgroup.long 0x4C++0x03 hide.long 0x00 "COMPARE1,Input FIFO Compare Value Register" elif (((per.l(ad:0xB2000000+0x50))&0x01)==0x00) rgroup.long 0x48++0x07 line.long 0x00 "COMPARE0,Input FIFO Compare Value Register" line.long 0x04 "COMPARE1,Input FIFO Compare Value Register" hexmask.long 0x04 0.--26. 1. " COMPARE ,Most significant bits of the compare register" else group.long 0x48++0x07 line.long 0x00 "COMPARE0,Input FIFO Compare Value Register" line.long 0x04 "COMPARE1,Input FIFO Compare Value Register" hexmask.long 0x04 0.--26. 1. " COMPARE ,Most significant bits of the compare register" endif if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x50++0x03 "Status Registers For Data Interface" hide.long 0x00 "COMPACC,Access Status register" hgroup.long 0x54++0x03 hide.long 0x00 "MSTSTATUS,Data Master Status Register" hgroup.long 0x58++0x03 hide.long 0x00 "IMSTERRADDR,Input Channel Master Error Response Address Register" hgroup.long 0x5C++0x03 hide.long 0x00 "OMSTERRADDR,Output Channel Master Error Response Address Register" hgroup.long 0x60++0x03 hide.long 0x00 "FIFOSTATUS,FIFO Status Register" hgroup.long 0x64++0x03 hide.long 0x00 "FIFOLOAD,FIFO Load Register" hgroup.long 0x68++0x03 hide.long 0x00 "DATACNT0,Input FIFO Data Counter Register" hgroup.long 0x6C++0x03 hide.long 0x00 "DATACNT1,Input FIFO Data Counter Register" else rgroup.long 0x50++0x1F "Status Registers For Data Interface" line.long 0x00 "COMPACC,Access Status register" bitfld.long 0x00 0. " CPUEN ,CPU write access enabled status flag" "Not allowed,Allowed" line.long 0x04 "MSTSTATUS,Data Master Status Register" bitfld.long 0x04 25.--26. " OMSTERRRESP ,Output data channel master error response code" "OKAY,EXOKAY,SLVERR,DECERR" bitfld.long 0x04 24. " OMSTERR ,Output data channel master error response flag" "No error,Error" bitfld.long 0x04 17. " OMSTLOCK ,Output data channel master lock enabled flag" "Unlocked,Locked" bitfld.long 0x04 16. " OMSTIDLE ,Output data channel master idle flag" "Started,Idle" newline bitfld.long 0x04 9.--10. " IMSTERRRESP ,Input data channel master error response code" "OKAY,EXOKAY,SLVERR,DECERR" bitfld.long 0x04 8. " IMSTERR ,Input data channel master error response flag" "No error,Error" bitfld.long 0x04 1. " IMSTLOCK ,Input data channel master lock enabled flag" "Unlocked,Locked" bitfld.long 0x04 0. " IMSTIDLE ,Input data channel master idle flag" "Started,Idle" line.long 0x08 "IMSTERRADDR,Input Channel Master Error Response Address Register" line.long 0x0C "OMSTERRADDR,Output Channel Master Error Response Address Register" line.long 0x10 "FIFOSTATUS,FIFO Status Register" bitfld.long 0x10 16. " COMPAREMATCH ,Compare match event flag" "Not transferred,Transferred" bitfld.long 0x10 8. " OFIFORDTH ,Output FIFO above threshold flag" "Not greater,Greater" bitfld.long 0x10 0. " IFIFOWRTH ,Input FIFO below threshold flag" "Not less,Less" line.long 0x14 "FIFOLOAD,FIFO Load Register" bitfld.long 0x14 24.--29. " OFIFOLOAD ,Amount of data stored in the output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 16.--21. " OFIFOFREE ,Amount of data which can be written into the output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 8.--13. " IFIFOLOAD ,Amount of data stored in the input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 0.--5. " IFIFOFREE ,Amount of data which can be written into the input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "DATACNT0,Input FIFO Data Counter Register" line.long 0x1C "DATACNT1,Input FIFO Data Counter Register" hexmask.long 0x1C 0.--26. 1. " DATACNT ,Most significant bits of the data counter" endif width 15. tree "Data Transfer Registers" sif cpuis("S6J35*") if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000) hgroup.long 0x100++0x03 hide.long 0x00 "IFIFOWRDATA0,Input FIFO Write Data register" hgroup.long 0x104++0x03 hide.long 0x00 "IFIFOWRDATA1,Input FIFO Write Data register" hgroup.long 0x108++0x03 hide.long 0x00 "IFIFOWRDATA2,Input FIFO Write Data register" hgroup.long 0x10C++0x03 hide.long 0x00 "IFIFOWRDATA3,Input FIFO Write Data register" hgroup.long 0x110++0x03 hide.long 0x00 "IFIFOWRDATA4,Input FIFO Write Data register" hgroup.long 0x114++0x03 hide.long 0x00 "IFIFOWRDATA5,Input FIFO Write Data register" hgroup.long 0x118++0x03 hide.long 0x00 "IFIFOWRDATA6,Input FIFO Write Data register" hgroup.long 0x11C++0x03 hide.long 0x00 "IFIFOWRDATA7,Input FIFO Write Data register" hgroup.long 0x120++0x03 hide.long 0x00 "IFIFOWRDATA8,Input FIFO Write Data register" hgroup.long 0x124++0x03 hide.long 0x00 "IFIFOWRDATA9,Input FIFO Write Data register" hgroup.long 0x128++0x03 hide.long 0x00 "IFIFOWRDATA10,Input FIFO Write Data register" hgroup.long 0x12C++0x03 hide.long 0x00 "IFIFOWRDATA11,Input FIFO Write Data register" hgroup.long 0x130++0x03 hide.long 0x00 "IFIFOWRDATA12,Input FIFO Write Data register" hgroup.long 0x134++0x03 hide.long 0x00 "IFIFOWRDATA13,Input FIFO Write Data register" hgroup.long 0x138++0x03 hide.long 0x00 "IFIFOWRDATA14,Input FIFO Write Data register" hgroup.long 0x13C++0x03 hide.long 0x00 "IFIFOWRDATA15,Input FIFO Write Data register" hgroup.long 0x140++0x03 hide.long 0x00 "IFIFOWRDATA16,Input FIFO Write Data register" hgroup.long 0x144++0x03 hide.long 0x00 "IFIFOWRDATA17,Input FIFO Write Data register" hgroup.long 0x148++0x03 hide.long 0x00 "IFIFOWRDATA18,Input FIFO Write Data register" hgroup.long 0x14C++0x03 hide.long 0x00 "IFIFOWRDATA19,Input FIFO Write Data register" hgroup.long 0x150++0x03 hide.long 0x00 "IFIFOWRDATA20,Input FIFO Write Data register" hgroup.long 0x154++0x03 hide.long 0x00 "IFIFOWRDATA21,Input FIFO Write Data register" hgroup.long 0x158++0x03 hide.long 0x00 "IFIFOWRDATA22,Input FIFO Write Data register" hgroup.long 0x15C++0x03 hide.long 0x00 "IFIFOWRDATA23,Input FIFO Write Data register" hgroup.long 0x160++0x03 hide.long 0x00 "IFIFOWRDATA24,Input FIFO Write Data register" hgroup.long 0x164++0x03 hide.long 0x00 "IFIFOWRDATA25,Input FIFO Write Data register" hgroup.long 0x168++0x03 hide.long 0x00 "IFIFOWRDATA26,Input FIFO Write Data register" hgroup.long 0x16C++0x03 hide.long 0x00 "IFIFOWRDATA27,Input FIFO Write Data register" hgroup.long 0x170++0x03 hide.long 0x00 "IFIFOWRDATA28,Input FIFO Write Data register" hgroup.long 0x174++0x03 hide.long 0x00 "IFIFOWRDATA29,Input FIFO Write Data register" hgroup.long 0x178++0x03 hide.long 0x00 "IFIFOWRDATA30,Input FIFO Write Data register" hgroup.long 0x17C++0x03 hide.long 0x00 "IFIFOWRDATA31,Input FIFO Write Data register" hgroup.long 0x180++0x03 hide.long 0x00 "OFIFORDDATA0,Output FIFO Read Data Register" hgroup.long 0x184++0x03 hide.long 0x00 "OFIFORDDATA1,Output FIFO Read Data Register" hgroup.long 0x188++0x03 hide.long 0x00 "OFIFORDDATA2,Output FIFO Read Data Register" hgroup.long 0x18C++0x03 hide.long 0x00 "OFIFORDDATA3,Output FIFO Read Data Register" hgroup.long 0x190++0x03 hide.long 0x00 "OFIFORDDATA4,Output FIFO Read Data Register" hgroup.long 0x194++0x03 hide.long 0x00 "OFIFORDDATA5,Output FIFO Read Data Register" hgroup.long 0x198++0x03 hide.long 0x00 "OFIFORDDATA6,Output FIFO Read Data Register" hgroup.long 0x19C++0x03 hide.long 0x00 "OFIFORDDATA7,Output FIFO Read Data Register" hgroup.long 0x1A0++0x03 hide.long 0x00 "OFIFORDDATA8,Output FIFO Read Data Register" hgroup.long 0x1A4++0x03 hide.long 0x00 "OFIFORDDATA9,Output FIFO Read Data Register" hgroup.long 0x1A8++0x03 hide.long 0x00 "OFIFORDDATA10,Output FIFO Read Data Register" hgroup.long 0x1AC++0x03 hide.long 0x00 "OFIFORDDATA11,Output FIFO Read Data Register" hgroup.long 0x1B0++0x03 hide.long 0x00 "OFIFORDDATA12,Output FIFO Read Data Register" hgroup.long 0x1B4++0x03 hide.long 0x00 "OFIFORDDATA13,Output FIFO Read Data Register" hgroup.long 0x1B8++0x03 hide.long 0x00 "OFIFORDDATA14,Output FIFO Read Data Register" hgroup.long 0x1BC++0x03 hide.long 0x00 "OFIFORDDATA15,Output FIFO Read Data Register" hgroup.long 0x1C0++0x03 hide.long 0x00 "OFIFORDDATA16,Output FIFO Read Data Register" hgroup.long 0x1C4++0x03 hide.long 0x00 "OFIFORDDATA17,Output FIFO Read Data Register" hgroup.long 0x1C8++0x03 hide.long 0x00 "OFIFORDDATA18,Output FIFO Read Data Register" hgroup.long 0x1CC++0x03 hide.long 0x00 "OFIFORDDATA19,Output FIFO Read Data Register" hgroup.long 0x1D0++0x03 hide.long 0x00 "OFIFORDDATA20,Output FIFO Read Data Register" hgroup.long 0x1D4++0x03 hide.long 0x00 "OFIFORDDATA21,Output FIFO Read Data Register" hgroup.long 0x1D8++0x03 hide.long 0x00 "OFIFORDDATA22,Output FIFO Read Data Register" hgroup.long 0x1DC++0x03 hide.long 0x00 "OFIFORDDATA23,Output FIFO Read Data Register" hgroup.long 0x1E0++0x03 hide.long 0x00 "OFIFORDDATA24,Output FIFO Read Data Register" hgroup.long 0x1E4++0x03 hide.long 0x00 "OFIFORDDATA25,Output FIFO Read Data Register" hgroup.long 0x1E8++0x03 hide.long 0x00 "OFIFORDDATA26,Output FIFO Read Data Register" hgroup.long 0x1EC++0x03 hide.long 0x00 "OFIFORDDATA27,Output FIFO Read Data Register" hgroup.long 0x1F0++0x03 hide.long 0x00 "OFIFORDDATA28,Output FIFO Read Data Register" hgroup.long 0x1F4++0x03 hide.long 0x00 "OFIFORDDATA29,Output FIFO Read Data Register" hgroup.long 0x1F8++0x03 hide.long 0x00 "OFIFORDDATA30,Output FIFO Read Data Register" hgroup.long 0x1FC++0x03 hide.long 0x00 "OFIFORDDATA31,Output FIFO Read Data Register" else wgroup.long 0x100++0x03 line.long 0x00 "IFIFOWRDATA0,Input FIFO Write Data register" wgroup.long 0x104++0x03 line.long 0x00 "IFIFOWRDATA1,Input FIFO Write Data register" wgroup.long 0x108++0x03 line.long 0x00 "IFIFOWRDATA2,Input FIFO Write Data register" wgroup.long 0x10C++0x03 line.long 0x00 "IFIFOWRDATA3,Input FIFO Write Data register" wgroup.long 0x110++0x03 line.long 0x00 "IFIFOWRDATA4,Input FIFO Write Data register" wgroup.long 0x114++0x03 line.long 0x00 "IFIFOWRDATA5,Input FIFO Write Data register" wgroup.long 0x118++0x03 line.long 0x00 "IFIFOWRDATA6,Input FIFO Write Data register" wgroup.long 0x11C++0x03 line.long 0x00 "IFIFOWRDATA7,Input FIFO Write Data register" wgroup.long 0x120++0x03 line.long 0x00 "IFIFOWRDATA8,Input FIFO Write Data register" wgroup.long 0x124++0x03 line.long 0x00 "IFIFOWRDATA9,Input FIFO Write Data register" wgroup.long 0x128++0x03 line.long 0x00 "IFIFOWRDATA10,Input FIFO Write Data register" wgroup.long 0x12C++0x03 line.long 0x00 "IFIFOWRDATA11,Input FIFO Write Data register" wgroup.long 0x130++0x03 line.long 0x00 "IFIFOWRDATA12,Input FIFO Write Data register" wgroup.long 0x134++0x03 line.long 0x00 "IFIFOWRDATA13,Input FIFO Write Data register" wgroup.long 0x138++0x03 line.long 0x00 "IFIFOWRDATA14,Input FIFO Write Data register" wgroup.long 0x13C++0x03 line.long 0x00 "IFIFOWRDATA15,Input FIFO Write Data register" wgroup.long 0x140++0x03 line.long 0x00 "IFIFOWRDATA16,Input FIFO Write Data register" wgroup.long 0x144++0x03 line.long 0x00 "IFIFOWRDATA17,Input FIFO Write Data register" wgroup.long 0x148++0x03 line.long 0x00 "IFIFOWRDATA18,Input FIFO Write Data register" wgroup.long 0x14C++0x03 line.long 0x00 "IFIFOWRDATA19,Input FIFO Write Data register" wgroup.long 0x150++0x03 line.long 0x00 "IFIFOWRDATA20,Input FIFO Write Data register" wgroup.long 0x154++0x03 line.long 0x00 "IFIFOWRDATA21,Input FIFO Write Data register" wgroup.long 0x158++0x03 line.long 0x00 "IFIFOWRDATA22,Input FIFO Write Data register" wgroup.long 0x15C++0x03 line.long 0x00 "IFIFOWRDATA23,Input FIFO Write Data register" wgroup.long 0x160++0x03 line.long 0x00 "IFIFOWRDATA24,Input FIFO Write Data register" wgroup.long 0x164++0x03 line.long 0x00 "IFIFOWRDATA25,Input FIFO Write Data register" wgroup.long 0x168++0x03 line.long 0x00 "IFIFOWRDATA26,Input FIFO Write Data register" wgroup.long 0x16C++0x03 line.long 0x00 "IFIFOWRDATA27,Input FIFO Write Data register" wgroup.long 0x170++0x03 line.long 0x00 "IFIFOWRDATA28,Input FIFO Write Data register" wgroup.long 0x174++0x03 line.long 0x00 "IFIFOWRDATA29,Input FIFO Write Data register" wgroup.long 0x178++0x03 line.long 0x00 "IFIFOWRDATA30,Input FIFO Write Data register" wgroup.long 0x17C++0x03 line.long 0x00 "IFIFOWRDATA31,Input FIFO Write Data register" wgroup.long 0x180++0x03 line.long 0x00 "OFIFORDDATA0,Output FIFO Read Data Register" wgroup.long 0x184++0x03 line.long 0x00 "OFIFORDDATA1,Output FIFO Read Data Register" wgroup.long 0x188++0x03 line.long 0x00 "OFIFORDDATA2,Output FIFO Read Data Register" wgroup.long 0x18C++0x03 line.long 0x00 "OFIFORDDATA3,Output FIFO Read Data Register" wgroup.long 0x190++0x03 line.long 0x00 "OFIFORDDATA4,Output FIFO Read Data Register" wgroup.long 0x194++0x03 line.long 0x00 "OFIFORDDATA5,Output FIFO Read Data Register" wgroup.long 0x198++0x03 line.long 0x00 "OFIFORDDATA6,Output FIFO Read Data Register" wgroup.long 0x19C++0x03 line.long 0x00 "OFIFORDDATA7,Output FIFO Read Data Register" wgroup.long 0x1A0++0x03 line.long 0x00 "OFIFORDDATA8,Output FIFO Read Data Register" wgroup.long 0x1A4++0x03 line.long 0x00 "OFIFORDDATA9,Output FIFO Read Data Register" wgroup.long 0x1A8++0x03 line.long 0x00 "OFIFORDDATA10,Output FIFO Read Data Register" wgroup.long 0x1AC++0x03 line.long 0x00 "OFIFORDDATA11,Output FIFO Read Data Register" wgroup.long 0x1B0++0x03 line.long 0x00 "OFIFORDDATA12,Output FIFO Read Data Register" wgroup.long 0x1B4++0x03 line.long 0x00 "OFIFORDDATA13,Output FIFO Read Data Register" wgroup.long 0x1B8++0x03 line.long 0x00 "OFIFORDDATA14,Output FIFO Read Data Register" wgroup.long 0x1BC++0x03 line.long 0x00 "OFIFORDDATA15,Output FIFO Read Data Register" wgroup.long 0x1C0++0x03 line.long 0x00 "OFIFORDDATA16,Output FIFO Read Data Register" wgroup.long 0x1C4++0x03 line.long 0x00 "OFIFORDDATA17,Output FIFO Read Data Register" wgroup.long 0x1C8++0x03 line.long 0x00 "OFIFORDDATA18,Output FIFO Read Data Register" wgroup.long 0x1CC++0x03 line.long 0x00 "OFIFORDDATA19,Output FIFO Read Data Register" wgroup.long 0x1D0++0x03 line.long 0x00 "OFIFORDDATA20,Output FIFO Read Data Register" wgroup.long 0x1D4++0x03 line.long 0x00 "OFIFORDDATA21,Output FIFO Read Data Register" wgroup.long 0x1D8++0x03 line.long 0x00 "OFIFORDDATA22,Output FIFO Read Data Register" wgroup.long 0x1DC++0x03 line.long 0x00 "OFIFORDDATA23,Output FIFO Read Data Register" wgroup.long 0x1E0++0x03 line.long 0x00 "OFIFORDDATA24,Output FIFO Read Data Register" wgroup.long 0x1E4++0x03 line.long 0x00 "OFIFORDDATA25,Output FIFO Read Data Register" wgroup.long 0x1E8++0x03 line.long 0x00 "OFIFORDDATA26,Output FIFO Read Data Register" wgroup.long 0x1EC++0x03 line.long 0x00 "OFIFORDDATA27,Output FIFO Read Data Register" wgroup.long 0x1F0++0x03 line.long 0x00 "OFIFORDDATA28,Output FIFO Read Data Register" wgroup.long 0x1F4++0x03 line.long 0x00 "OFIFORDDATA29,Output FIFO Read Data Register" wgroup.long 0x1F8++0x03 line.long 0x00 "OFIFORDDATA30,Output FIFO Read Data Register" wgroup.long 0x1FC++0x03 line.long 0x00 "OFIFORDDATA31,Output FIFO Read Data Register" endif else hgroup.long 0x100++0x03 hide.long 0x00 "IFIFOWRDATA0,Input FIFO Write Data register" hgroup.long 0x104++0x03 hide.long 0x00 "IFIFOWRDATA1,Input FIFO Write Data register" hgroup.long 0x108++0x03 hide.long 0x00 "IFIFOWRDATA2,Input FIFO Write Data register" hgroup.long 0x10C++0x03 hide.long 0x00 "IFIFOWRDATA3,Input FIFO Write Data register" hgroup.long 0x110++0x03 hide.long 0x00 "IFIFOWRDATA4,Input FIFO Write Data register" hgroup.long 0x114++0x03 hide.long 0x00 "IFIFOWRDATA5,Input FIFO Write Data register" hgroup.long 0x118++0x03 hide.long 0x00 "IFIFOWRDATA6,Input FIFO Write Data register" hgroup.long 0x11C++0x03 hide.long 0x00 "IFIFOWRDATA7,Input FIFO Write Data register" hgroup.long 0x120++0x03 hide.long 0x00 "IFIFOWRDATA8,Input FIFO Write Data register" hgroup.long 0x124++0x03 hide.long 0x00 "IFIFOWRDATA9,Input FIFO Write Data register" hgroup.long 0x128++0x03 hide.long 0x00 "IFIFOWRDATA10,Input FIFO Write Data register" hgroup.long 0x12C++0x03 hide.long 0x00 "IFIFOWRDATA11,Input FIFO Write Data register" hgroup.long 0x130++0x03 hide.long 0x00 "IFIFOWRDATA12,Input FIFO Write Data register" hgroup.long 0x134++0x03 hide.long 0x00 "IFIFOWRDATA13,Input FIFO Write Data register" hgroup.long 0x138++0x03 hide.long 0x00 "IFIFOWRDATA14,Input FIFO Write Data register" hgroup.long 0x13C++0x03 hide.long 0x00 "IFIFOWRDATA15,Input FIFO Write Data register" hgroup.long 0x140++0x03 hide.long 0x00 "IFIFOWRDATA16,Input FIFO Write Data register" hgroup.long 0x144++0x03 hide.long 0x00 "IFIFOWRDATA17,Input FIFO Write Data register" hgroup.long 0x148++0x03 hide.long 0x00 "IFIFOWRDATA18,Input FIFO Write Data register" hgroup.long 0x14C++0x03 hide.long 0x00 "IFIFOWRDATA19,Input FIFO Write Data register" hgroup.long 0x150++0x03 hide.long 0x00 "IFIFOWRDATA20,Input FIFO Write Data register" hgroup.long 0x154++0x03 hide.long 0x00 "IFIFOWRDATA21,Input FIFO Write Data register" hgroup.long 0x158++0x03 hide.long 0x00 "IFIFOWRDATA22,Input FIFO Write Data register" hgroup.long 0x15C++0x03 hide.long 0x00 "IFIFOWRDATA23,Input FIFO Write Data register" hgroup.long 0x160++0x03 hide.long 0x00 "IFIFOWRDATA24,Input FIFO Write Data register" hgroup.long 0x164++0x03 hide.long 0x00 "IFIFOWRDATA25,Input FIFO Write Data register" hgroup.long 0x168++0x03 hide.long 0x00 "IFIFOWRDATA26,Input FIFO Write Data register" hgroup.long 0x16C++0x03 hide.long 0x00 "IFIFOWRDATA27,Input FIFO Write Data register" hgroup.long 0x170++0x03 hide.long 0x00 "IFIFOWRDATA28,Input FIFO Write Data register" hgroup.long 0x174++0x03 hide.long 0x00 "IFIFOWRDATA29,Input FIFO Write Data register" hgroup.long 0x178++0x03 hide.long 0x00 "IFIFOWRDATA30,Input FIFO Write Data register" hgroup.long 0x17C++0x03 hide.long 0x00 "IFIFOWRDATA31,Input FIFO Write Data register" hgroup.long 0x180++0x03 hide.long 0x00 "OFIFORDDATA0,Output FIFO Read Data Register" hgroup.long 0x184++0x03 hide.long 0x00 "OFIFORDDATA1,Output FIFO Read Data Register" hgroup.long 0x188++0x03 hide.long 0x00 "OFIFORDDATA2,Output FIFO Read Data Register" hgroup.long 0x18C++0x03 hide.long 0x00 "OFIFORDDATA3,Output FIFO Read Data Register" hgroup.long 0x190++0x03 hide.long 0x00 "OFIFORDDATA4,Output FIFO Read Data Register" hgroup.long 0x194++0x03 hide.long 0x00 "OFIFORDDATA5,Output FIFO Read Data Register" hgroup.long 0x198++0x03 hide.long 0x00 "OFIFORDDATA6,Output FIFO Read Data Register" hgroup.long 0x19C++0x03 hide.long 0x00 "OFIFORDDATA7,Output FIFO Read Data Register" hgroup.long 0x1A0++0x03 hide.long 0x00 "OFIFORDDATA8,Output FIFO Read Data Register" hgroup.long 0x1A4++0x03 hide.long 0x00 "OFIFORDDATA9,Output FIFO Read Data Register" hgroup.long 0x1A8++0x03 hide.long 0x00 "OFIFORDDATA10,Output FIFO Read Data Register" hgroup.long 0x1AC++0x03 hide.long 0x00 "OFIFORDDATA11,Output FIFO Read Data Register" hgroup.long 0x1B0++0x03 hide.long 0x00 "OFIFORDDATA12,Output FIFO Read Data Register" hgroup.long 0x1B4++0x03 hide.long 0x00 "OFIFORDDATA13,Output FIFO Read Data Register" hgroup.long 0x1B8++0x03 hide.long 0x00 "OFIFORDDATA14,Output FIFO Read Data Register" hgroup.long 0x1BC++0x03 hide.long 0x00 "OFIFORDDATA15,Output FIFO Read Data Register" hgroup.long 0x1C0++0x03 hide.long 0x00 "OFIFORDDATA16,Output FIFO Read Data Register" hgroup.long 0x1C4++0x03 hide.long 0x00 "OFIFORDDATA17,Output FIFO Read Data Register" hgroup.long 0x1C8++0x03 hide.long 0x00 "OFIFORDDATA18,Output FIFO Read Data Register" hgroup.long 0x1CC++0x03 hide.long 0x00 "OFIFORDDATA19,Output FIFO Read Data Register" hgroup.long 0x1D0++0x03 hide.long 0x00 "OFIFORDDATA20,Output FIFO Read Data Register" hgroup.long 0x1D4++0x03 hide.long 0x00 "OFIFORDDATA21,Output FIFO Read Data Register" hgroup.long 0x1D8++0x03 hide.long 0x00 "OFIFORDDATA22,Output FIFO Read Data Register" hgroup.long 0x1DC++0x03 hide.long 0x00 "OFIFORDDATA23,Output FIFO Read Data Register" hgroup.long 0x1E0++0x03 hide.long 0x00 "OFIFORDDATA24,Output FIFO Read Data Register" hgroup.long 0x1E4++0x03 hide.long 0x00 "OFIFORDDATA25,Output FIFO Read Data Register" hgroup.long 0x1E8++0x03 hide.long 0x00 "OFIFORDDATA26,Output FIFO Read Data Register" hgroup.long 0x1EC++0x03 hide.long 0x00 "OFIFORDDATA27,Output FIFO Read Data Register" hgroup.long 0x1F0++0x03 hide.long 0x00 "OFIFORDDATA28,Output FIFO Read Data Register" hgroup.long 0x1F4++0x03 hide.long 0x00 "OFIFORDDATA29,Output FIFO Read Data Register" hgroup.long 0x1F8++0x03 hide.long 0x00 "OFIFORDDATA30,Output FIFO Read Data Register" hgroup.long 0x1FC++0x03 hide.long 0x00 "OFIFORDDATA31,Output FIFO Read Data Register" endif tree.end width 0x0B tree.end tree "DMAC (DMA CONTROLLER)" base ad:0xB4700000 width 8. group.long 0x1000++0x03 line.long 0x00 "R,DMA Controller Global Configuration Register" bitfld.long 0x00 31. " DE ,DMA enable" "Disabled,Enabled" rbitfld.long 0x00 30. " DSHR ,DMA stop/halt request flag" "Not requested,Requested" bitfld.long 0x00 29. " DBE ,Debug enable" "Disabled,Enabled" newline bitfld.long 0x00 27.--28. " PR ,Priority type" "Fixed,Dynamic,Round Robin,?..." bitfld.long 0x00 26. " DH ,DMA halt" "Not halted,Halted" bitfld.long 0x00 24.--25. " DB ,Debug behavior" "Continues,Halted,Stopped,?..." newline rbitfld.long 0x00 0. " DSHS ,DMA stop/halt status flag" "Running,Halted" rgroup.long 0x1004++0x03 line.long 0x00 "DIRQ1,DMA Controller Global Completion Interrupt 1 Register" bitfld.long 0x00 15. " DIRQ_[15] ,Global completion interrupt 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Global completion interrupt 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Global completion interrupt 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Global completion interrupt 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Global completion interrupt 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Global completion interrupt 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Global completion interrupt 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Global completion interrupt 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Global completion interrupt 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Global completion interrupt 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Global completion interrupt 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Global completion interrupt 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Global completion interrupt 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Global completion interrupt 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Global completion interrupt 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Global completion interrupt 0" "No interrupt,Interrupt" rgroup.long 0x100C++0x07 line.long 0x00 "EDIRQ1,DMA Controller Global Error Interrupt 1 Register" bitfld.long 0x00 15. " EDIRQ_[15] ,Global error interrupt 15" "Not occurred,Occurred" bitfld.long 0x00 14. " [14] ,Global error interrupt 14" "Not occurred,Occurred" bitfld.long 0x00 13. " [13] ,Global error interrupt 13" "Not occurred,Occurred" bitfld.long 0x00 12. " [12] ,Global error interrupt 12" "Not occurred,Occurred" newline bitfld.long 0x00 11. " [11] ,Global error interrupt 11" "Not occurred,Occurred" bitfld.long 0x00 10. " [10] ,Global error interrupt 10" "Not occurred,Occurred" bitfld.long 0x00 9. " [9] ,Global error interrupt 9" "Not occurred,Occurred" bitfld.long 0x00 8. " [8] ,Global error interrupt 8" "Not occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Global error interrupt 7" "Not occurred,Occurred" bitfld.long 0x00 6. " [6] ,Global error interrupt 6" "Not occurred,Occurred" bitfld.long 0x00 5. " [5] ,Global error interrupt 5" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Global error interrupt 4" "Not occurred,Occurred" newline bitfld.long 0x00 3. " [3] ,Global error interrupt 3" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Global error interrupt 2" "Not occurred,Occurred" bitfld.long 0x00 1. " [1] ,Global error interrupt 1" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Global error interrupt 0" "Not occurred,Occurred" line.long 0x04 "ID,DMA Controller ID Register" width 7. tree "DMA_A 0--15" group.long 0x0++0x03 line.long 0x00 "A0,DMA Controller Channel Configuration A Register Channel 0" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x40++0x03 line.long 0x00 "A1,DMA Controller Channel Configuration A Register Channel 1" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x80++0x03 line.long 0x00 "A2,DMA Controller Channel Configuration A Register Channel 2" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0xC0++0x03 line.long 0x00 "A3,DMA Controller Channel Configuration A Register Channel 3" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x100++0x03 line.long 0x00 "A4,DMA Controller Channel Configuration A Register Channel 4" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x140++0x03 line.long 0x00 "A5,DMA Controller Channel Configuration A Register Channel 5" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x180++0x03 line.long 0x00 "A6,DMA Controller Channel Configuration A Register Channel 6" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x1C0++0x03 line.long 0x00 "A7,DMA Controller Channel Configuration A Register Channel 7" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x200++0x03 line.long 0x00 "A8,DMA Controller Channel Configuration A Register Channel 8" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x240++0x03 line.long 0x00 "A9,DMA Controller Channel Configuration A Register Channel 9" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x280++0x03 line.long 0x00 "A10,DMA Controller Channel Configuration A Register Channel 10" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x2C0++0x03 line.long 0x00 "A11,DMA Controller Channel Configuration A Register Channel 11" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x300++0x03 line.long 0x00 "A12,DMA Controller Channel Configuration A Register Channel 12" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x340++0x03 line.long 0x00 "A13,DMA Controller Channel Configuration A Register Channel 13" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x380++0x03 line.long 0x00 "A14,DMA Controller Channel Configuration A Register Channel 14" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" group.long 0x3C0++0x03 line.long 0x00 "A15,DMA Controller Channel Configuration A Register Channel 15" bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted" bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested" newline bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..." bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate" bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16" newline bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count" tree.end tree "DMA_B 0--15" group.long 0x4++0x03 line.long 0x00 "B0,DMA Controller Channel Configuration B Register Channel 0" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x44++0x03 line.long 0x00 "B1,DMA Controller Channel Configuration B Register Channel 1" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x84++0x03 line.long 0x00 "B2,DMA Controller Channel Configuration B Register Channel 2" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0xC4++0x03 line.long 0x00 "B3,DMA Controller Channel Configuration B Register Channel 3" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x104++0x03 line.long 0x00 "B4,DMA Controller Channel Configuration B Register Channel 4" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x144++0x03 line.long 0x00 "B5,DMA Controller Channel Configuration B Register Channel 5" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x184++0x03 line.long 0x00 "B6,DMA Controller Channel Configuration B Register Channel 6" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x1C4++0x03 line.long 0x00 "B7,DMA Controller Channel Configuration B Register Channel 7" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x204++0x03 line.long 0x00 "B8,DMA Controller Channel Configuration B Register Channel 8" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x244++0x03 line.long 0x00 "B9,DMA Controller Channel Configuration B Register Channel 9" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x284++0x03 line.long 0x00 "B10,DMA Controller Channel Configuration B Register Channel 10" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x2C4++0x03 line.long 0x00 "B11,DMA Controller Channel Configuration B Register Channel 11" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x304++0x03 line.long 0x00 "B12,DMA Controller Channel Configuration B Register Channel 12" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x344++0x03 line.long 0x00 "B13,DMA Controller Channel Configuration B Register Channel 13" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x384++0x03 line.long 0x00 "B14,DMA Controller Channel Configuration B Register Channel 14" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" group.long 0x3C4++0x03 line.long 0x00 "B15,DMA Controller Channel Configuration B Register Channel 15" rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not Completed,Completed" rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error" bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..." newline bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half Word,Word,Double word" rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready" bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel Disable/DMA Disable/Debug Event,Source Access Error,Destination Access Error,Normal End,?..." newline bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable" bitfld.long 0x00 14. " [2] ,Source protection" "Not bufferable,Bufferable" bitfld.long 0x00 13. " [1] ,Source protection" "User access,Privileged access" rbitfld.long 0x00 12. " [0] ,Source protection" "Instruction access,Data success" newline bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable" bitfld.long 0x00 10. " [2] ,Destination protection" "Not bufferable,Bufferable" bitfld.long 0x00 9. " [1] ,Destination protection" "User access,Privileged access" newline rbitfld.long 0x00 8. " [0] ,Destination protection" "Instruction access,Data success" hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number" tree.end tree "DMA_SA 0--15" group.long 0x8++0x03 line.long 0x00 "SA0,DMA Controller Channel Configuration Source Address Register Channel 0" group.long 0x48++0x03 line.long 0x00 "SA1,DMA Controller Channel Configuration Source Address Register Channel 1" group.long 0x88++0x03 line.long 0x00 "SA2,DMA Controller Channel Configuration Source Address Register Channel 2" group.long 0xC8++0x03 line.long 0x00 "SA3,DMA Controller Channel Configuration Source Address Register Channel 3" group.long 0x108++0x03 line.long 0x00 "SA4,DMA Controller Channel Configuration Source Address Register Channel 4" group.long 0x148++0x03 line.long 0x00 "SA5,DMA Controller Channel Configuration Source Address Register Channel 5" group.long 0x188++0x03 line.long 0x00 "SA6,DMA Controller Channel Configuration Source Address Register Channel 6" group.long 0x1C8++0x03 line.long 0x00 "SA7,DMA Controller Channel Configuration Source Address Register Channel 7" group.long 0x208++0x03 line.long 0x00 "SA8,DMA Controller Channel Configuration Source Address Register Channel 8" group.long 0x248++0x03 line.long 0x00 "SA9,DMA Controller Channel Configuration Source Address Register Channel 9" group.long 0x288++0x03 line.long 0x00 "SA10,DMA Controller Channel Configuration Source Address Register Channel 10" group.long 0x2C8++0x03 line.long 0x00 "SA11,DMA Controller Channel Configuration Source Address Register Channel 11" group.long 0x308++0x03 line.long 0x00 "SA12,DMA Controller Channel Configuration Source Address Register Channel 12" group.long 0x348++0x03 line.long 0x00 "SA13,DMA Controller Channel Configuration Source Address Register Channel 13" group.long 0x388++0x03 line.long 0x00 "SA14,DMA Controller Channel Configuration Source Address Register Channel 14" group.long 0x3C8++0x03 line.long 0x00 "SA15,DMA Controller Channel Configuration Source Address Register Channel 15" tree.end tree "DMA_DA 0--15" group.long 0xC++0x03 line.long 0x00 "DA0,DMA Controller Channel Configuration Destination Address Register Channel 0" group.long 0x4C++0x03 line.long 0x00 "DA1,DMA Controller Channel Configuration Destination Address Register Channel 1" group.long 0x8C++0x03 line.long 0x00 "DA2,DMA Controller Channel Configuration Destination Address Register Channel 2" group.long 0xCC++0x03 line.long 0x00 "DA3,DMA Controller Channel Configuration Destination Address Register Channel 3" group.long 0x10C++0x03 line.long 0x00 "DA4,DMA Controller Channel Configuration Destination Address Register Channel 4" group.long 0x14C++0x03 line.long 0x00 "DA5,DMA Controller Channel Configuration Destination Address Register Channel 5" group.long 0x18C++0x03 line.long 0x00 "DA6,DMA Controller Channel Configuration Destination Address Register Channel 6" group.long 0x1CC++0x03 line.long 0x00 "DA7,DMA Controller Channel Configuration Destination Address Register Channel 7" group.long 0x20C++0x03 line.long 0x00 "DA8,DMA Controller Channel Configuration Destination Address Register Channel 8" group.long 0x24C++0x03 line.long 0x00 "DA9,DMA Controller Channel Configuration Destination Address Register Channel 9" group.long 0x28C++0x03 line.long 0x00 "DA10,DMA Controller Channel Configuration Destination Address Register Channel 10" group.long 0x2CC++0x03 line.long 0x00 "DA11,DMA Controller Channel Configuration Destination Address Register Channel 11" group.long 0x30C++0x03 line.long 0x00 "DA12,DMA Controller Channel Configuration Destination Address Register Channel 12" group.long 0x34C++0x03 line.long 0x00 "DA13,DMA Controller Channel Configuration Destination Address Register Channel 13" group.long 0x38C++0x03 line.long 0x00 "DA14,DMA Controller Channel Configuration Destination Address Register Channel 14" group.long 0x3CC++0x03 line.long 0x00 "DA15,DMA Controller Channel Configuration Destination Address Register Channel 15" tree.end tree "DMA_C 0--15" group.long 0x10++0x03 line.long 0x00 "C0,DMA Controller Channel Configuration C Register Channel 0" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x50++0x03 line.long 0x00 "C1,DMA Controller Channel Configuration C Register Channel 1" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x90++0x03 line.long 0x00 "C2,DMA Controller Channel Configuration C Register Channel 2" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0xD0++0x03 line.long 0x00 "C3,DMA Controller Channel Configuration C Register Channel 3" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x110++0x03 line.long 0x00 "C4,DMA Controller Channel Configuration C Register Channel 4" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x150++0x03 line.long 0x00 "C5,DMA Controller Channel Configuration C Register Channel 5" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x190++0x03 line.long 0x00 "C6,DMA Controller Channel Configuration C Register Channel 6" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x1D0++0x03 line.long 0x00 "C7,DMA Controller Channel Configuration C Register Channel 7" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x210++0x03 line.long 0x00 "C8,DMA Controller Channel Configuration C Register Channel 8" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x250++0x03 line.long 0x00 "C9,DMA Controller Channel Configuration C Register Channel 9" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x290++0x03 line.long 0x00 "C10,DMA Controller Channel Configuration C Register Channel 10" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x2D0++0x03 line.long 0x00 "C11,DMA Controller Channel Configuration C Register Channel 11" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x310++0x03 line.long 0x00 "C12,DMA Controller Channel Configuration C Register Channel 12" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x350++0x03 line.long 0x00 "C13,DMA Controller Channel Configuration C Register Channel 13" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x390++0x03 line.long 0x00 "C14,DMA Controller Channel Configuration C Register Channel 14" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" group.long 0x3D0++0x03 line.long 0x00 "C15,DMA Controller Channel Configuration C Register Channel 15" bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear" bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear" tree.end tree "DMA_D 0--15" group.long 0x14++0x03 line.long 0x00 "D0_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x54++0x03 line.long 0x00 "D1_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x94++0x03 line.long 0x00 "D2_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0xD4++0x03 line.long 0x00 "D3_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x114++0x03 line.long 0x00 "D4_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x154++0x03 line.long 0x00 "D5_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x194++0x03 line.long 0x00 "D6_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x1D4++0x03 line.long 0x00 "D7_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x214++0x03 line.long 0x00 "D8_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x254++0x03 line.long 0x00 "D9_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x294++0x03 line.long 0x00 "D10_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x2D4++0x03 line.long 0x00 "D11_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x314++0x03 line.long 0x00 "D12_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x354++0x03 line.long 0x00 "D13_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x394++0x03 line.long 0x00 "D14_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" group.long 0x3D4++0x03 line.long 0x00 "D15_3,DMA Controller Channel Configuration D Register" bitfld.long 0x00 31. " FS ,Fixed source address" "Incremented,Kept fixed" bitfld.long 0x00 30. " DES ,Decrement source address" "Incremented,Decremented" bitfld.long 0x00 29. " US ,Update source address" "Not updated,Updated" bitfld.long 0x00 28. " FBS ,Fixed block source address" "Not fixed,Fixed" newline bitfld.long 0x00 15. " FD ,Fixed destination address" "Incremented,Kept fixed" bitfld.long 0x00 14. " DED ,Decrement destination address" "Incremented,Decremented" bitfld.long 0x00 13. " UD ,Update destination address" "Not updated,Updated" bitfld.long 0x00 12. " FBD ,Fixed block destination address" "Not fixed,Fixed" tree.end width 10. tree "DMA_SASHDW DMA_DASHDW 0-15" rgroup.long 0x18++0x03 line.long 0x00 "SASHDW0,DMA Controller Channel Configuration Source Address Shadow Register Channel 0" rgroup.long 0x58++0x03 line.long 0x00 "SASHDW1,DMA Controller Channel Configuration Source Address Shadow Register Channel 1" rgroup.long 0x98++0x03 line.long 0x00 "SASHDW2,DMA Controller Channel Configuration Source Address Shadow Register Channel 2" rgroup.long 0xD8++0x03 line.long 0x00 "SASHDW3,DMA Controller Channel Configuration Source Address Shadow Register Channel 3" rgroup.long 0x118++0x03 line.long 0x00 "SASHDW4,DMA Controller Channel Configuration Source Address Shadow Register Channel 4" rgroup.long 0x158++0x03 line.long 0x00 "SASHDW5,DMA Controller Channel Configuration Source Address Shadow Register Channel 5" rgroup.long 0x198++0x03 line.long 0x00 "SASHDW6,DMA Controller Channel Configuration Source Address Shadow Register Channel 6" rgroup.long 0x1D8++0x03 line.long 0x00 "SASHDW7,DMA Controller Channel Configuration Source Address Shadow Register Channel 7" rgroup.long 0x218++0x03 line.long 0x00 "SASHDW8,DMA Controller Channel Configuration Source Address Shadow Register Channel 8" rgroup.long 0x258++0x03 line.long 0x00 "SASHDW9,DMA Controller Channel Configuration Source Address Shadow Register Channel 9" rgroup.long 0x298++0x03 line.long 0x00 "SASHDW10,DMA Controller Channel Configuration Source Address Shadow Register Channel 10" rgroup.long 0x2D8++0x03 line.long 0x00 "SASHDW11,DMA Controller Channel Configuration Source Address Shadow Register Channel 11" rgroup.long 0x318++0x03 line.long 0x00 "SASHDW12,DMA Controller Channel Configuration Source Address Shadow Register Channel 12" rgroup.long 0x358++0x03 line.long 0x00 "SASHDW13,DMA Controller Channel Configuration Source Address Shadow Register Channel 13" rgroup.long 0x398++0x03 line.long 0x00 "SASHDW14,DMA Controller Channel Configuration Source Address Shadow Register Channel 14" rgroup.long 0x3D8++0x03 line.long 0x00 "SASHDW15,DMA Controller Channel Configuration Source Address Shadow Register Channel 15" newline rgroup.long 0x1C++0x03 line.long 0x00 "DASHDW0,DMA Controller Channel Configuration Destination Address Shadow Register Channel 0" rgroup.long 0x5C++0x03 line.long 0x00 "DASHDW1,DMA Controller Channel Configuration Destination Address Shadow Register Channel 1" rgroup.long 0x9C++0x03 line.long 0x00 "DASHDW2,DMA Controller Channel Configuration Destination Address Shadow Register Channel 2" rgroup.long 0xDC++0x03 line.long 0x00 "DASHDW3,DMA Controller Channel Configuration Destination Address Shadow Register Channel 3" rgroup.long 0x11C++0x03 line.long 0x00 "DASHDW4,DMA Controller Channel Configuration Destination Address Shadow Register Channel 4" rgroup.long 0x15C++0x03 line.long 0x00 "DASHDW5,DMA Controller Channel Configuration Destination Address Shadow Register Channel 5" rgroup.long 0x19C++0x03 line.long 0x00 "DASHDW6,DMA Controller Channel Configuration Destination Address Shadow Register Channel 6" rgroup.long 0x1DC++0x03 line.long 0x00 "DASHDW7,DMA Controller Channel Configuration Destination Address Shadow Register Channel 7" rgroup.long 0x21C++0x03 line.long 0x00 "DASHDW8,DMA Controller Channel Configuration Destination Address Shadow Register Channel 8" rgroup.long 0x25C++0x03 line.long 0x00 "DASHDW9,DMA Controller Channel Configuration Destination Address Shadow Register Channel 9" rgroup.long 0x29C++0x03 line.long 0x00 "DASHDW10,DMA Controller Channel Configuration Destination Address Shadow Register Channel 10" rgroup.long 0x2DC++0x03 line.long 0x00 "DASHDW11,DMA Controller Channel Configuration Destination Address Shadow Register Channel 11" rgroup.long 0x31C++0x03 line.long 0x00 "DASHDW12,DMA Controller Channel Configuration Destination Address Shadow Register Channel 12" rgroup.long 0x35C++0x03 line.long 0x00 "DASHDW13,DMA Controller Channel Configuration Destination Address Shadow Register Channel 13" rgroup.long 0x39C++0x03 line.long 0x00 "DASHDW14,DMA Controller Channel Configuration Destination Address Shadow Register Channel 14" rgroup.long 0x3DC++0x03 line.long 0x00 "DASHDW15,DMA Controller Channel Configuration Destination Address Shadow Register Channel 15" tree.end tree "CMICIC" group.long 0x2020++0x03 line.long 0x00 "CMICIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2024++0x03 line.long 0x00 "CMICIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2028++0x03 line.long 0x00 "CMICIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x202C++0x03 line.long 0x00 "CMICIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2030++0x03 line.long 0x00 "CMICIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2034++0x03 line.long 0x00 "CMICIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2038++0x03 line.long 0x00 "CMICIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x203C++0x03 line.long 0x00 "CMICIC16,DMA Controller Client Matrix Internal Client Interface Configuration Register 16" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2040++0x03 line.long 0x00 "CMICIC17,DMA Controller Client Matrix Internal Client Interface Configuration Register 17" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2044++0x03 line.long 0x00 "CMICIC18,DMA Controller Client Matrix Internal Client Interface Configuration Register 18" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2048++0x03 line.long 0x00 "CMICIC19,DMA Controller Client Matrix Internal Client Interface Configuration Register 19" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x204C++0x03 line.long 0x00 "CMICIC20,DMA Controller Client Matrix Internal Client Interface Configuration Register 20" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2050++0x03 line.long 0x00 "CMICIC21,DMA Controller Client Matrix Internal Client Interface Configuration Register 21" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2054++0x03 line.long 0x00 "CMICIC22,DMA Controller Client Matrix Internal Client Interface Configuration Register 22" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2058++0x03 line.long 0x00 "CMICIC23,DMA Controller Client Matrix Internal Client Interface Configuration Register 23" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x205C++0x03 line.long 0x00 "CMICIC24,DMA Controller Client Matrix Internal Client Interface Configuration Register 24" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2060++0x03 line.long 0x00 "CMICIC25,DMA Controller Client Matrix Internal Client Interface Configuration Register 25" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2064++0x03 line.long 0x00 "CMICIC26,DMA Controller Client Matrix Internal Client Interface Configuration Register 26" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2068++0x03 line.long 0x00 "CMICIC27,DMA Controller Client Matrix Internal Client Interface Configuration Register 27" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x206C++0x03 line.long 0x00 "CMICIC28,DMA Controller Client Matrix Internal Client Interface Configuration Register 28" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2070++0x03 line.long 0x00 "CMICIC29,DMA Controller Client Matrix Internal Client Interface Configuration Register 29" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2074++0x03 line.long 0x00 "CMICIC30,DMA Controller Client Matrix Internal Client Interface Configuration Register 30" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2078++0x03 line.long 0x00 "CMICIC31,DMA Controller Client Matrix Internal Client Interface Configuration Register 31" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x207C++0x03 line.long 0x00 "CMICIC32,DMA Controller Client Matrix Internal Client Interface Configuration Register 32" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2080++0x03 line.long 0x00 "CMICIC33,DMA Controller Client Matrix Internal Client Interface Configuration Register 33" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2084++0x03 line.long 0x00 "CMICIC34,DMA Controller Client Matrix Internal Client Interface Configuration Register 34" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2088++0x03 line.long 0x00 "CMICIC35,DMA Controller Client Matrix Internal Client Interface Configuration Register 35" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x208C++0x03 line.long 0x00 "CMICIC36,DMA Controller Client Matrix Internal Client Interface Configuration Register 36" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2090++0x03 line.long 0x00 "CMICIC37,DMA Controller Client Matrix Internal Client Interface Configuration Register 37" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2094++0x03 line.long 0x00 "CMICIC38,DMA Controller Client Matrix Internal Client Interface Configuration Register 38" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2098++0x03 line.long 0x00 "CMICIC39,DMA Controller Client Matrix Internal Client Interface Configuration Register 39" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x209C++0x03 line.long 0x00 "CMICIC40,DMA Controller Client Matrix Internal Client Interface Configuration Register 40" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20A0++0x03 line.long 0x00 "CMICIC41,DMA Controller Client Matrix Internal Client Interface Configuration Register 41" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20A4++0x03 line.long 0x00 "CMICIC42,DMA Controller Client Matrix Internal Client Interface Configuration Register 42" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20A8++0x03 line.long 0x00 "CMICIC43,DMA Controller Client Matrix Internal Client Interface Configuration Register 43" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20AC++0x03 line.long 0x00 "CMICIC44,DMA Controller Client Matrix Internal Client Interface Configuration Register 44" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20B0++0x03 line.long 0x00 "CMICIC45,DMA Controller Client Matrix Internal Client Interface Configuration Register 45" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20DC++0x03 line.long 0x00 "CMICIC56,DMA Controller Client Matrix Internal Client Interface Configuration Register 56" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20E0++0x03 line.long 0x00 "CMICIC57,DMA Controller Client Matrix Internal Client Interface Configuration Register 57" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20E4++0x03 line.long 0x00 "CMICIC58,DMA Controller Client Matrix Internal Client Interface Configuration Register 58" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20E8++0x03 line.long 0x00 "CMICIC59,DMA Controller Client Matrix Internal Client Interface Configuration Register 59" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20EC++0x03 line.long 0x00 "CMICIC60,DMA Controller Client Matrix Internal Client Interface Configuration Register 60" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20F0++0x03 line.long 0x00 "CMICIC61,DMA Controller Client Matrix Internal Client Interface Configuration Register 61" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20F4++0x03 line.long 0x00 "CMICIC62,DMA Controller Client Matrix Internal Client Interface Configuration Register 62" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20F8++0x03 line.long 0x00 "CMICIC63,DMA Controller Client Matrix Internal Client Interface Configuration Register 63" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x20FC++0x03 line.long 0x00 "CMICIC64,DMA Controller Client Matrix Internal Client Interface Configuration Register 64" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2100++0x03 line.long 0x00 "CMICIC65,DMA Controller Client Matrix Internal Client Interface Configuration Register 65" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2104++0x03 line.long 0x00 "CMICIC66,DMA Controller Client Matrix Internal Client Interface Configuration Register 66" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2108++0x03 line.long 0x00 "CMICIC67,DMA Controller Client Matrix Internal Client Interface Configuration Register 67" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x210C++0x03 line.long 0x00 "CMICIC68,DMA Controller Client Matrix Internal Client Interface Configuration Register 68" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2110++0x03 line.long 0x00 "CMICIC69,DMA Controller Client Matrix Internal Client Interface Configuration Register 69" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2114++0x03 line.long 0x00 "CMICIC70,DMA Controller Client Matrix Internal Client Interface Configuration Register 70" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2118++0x03 line.long 0x00 "CMICIC71,DMA Controller Client Matrix Internal Client Interface Configuration Register 71" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x211C++0x03 line.long 0x00 "CMICIC72,DMA Controller Client Matrix Internal Client Interface Configuration Register 72" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2120++0x03 line.long 0x00 "CMICIC73,DMA Controller Client Matrix Internal Client Interface Configuration Register 73" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2124++0x03 line.long 0x00 "CMICIC74,DMA Controller Client Matrix Internal Client Interface Configuration Register 74" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2128++0x03 line.long 0x00 "CMICIC75,DMA Controller Client Matrix Internal Client Interface Configuration Register 75" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x212C++0x03 line.long 0x00 "CMICIC76,DMA Controller Client Matrix Internal Client Interface Configuration Register 76" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2130++0x03 line.long 0x00 "CMICIC77,DMA Controller Client Matrix Internal Client Interface Configuration Register 77" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2134++0x03 line.long 0x00 "CMICIC78,DMA Controller Client Matrix Internal Client Interface Configuration Register 78" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2138++0x03 line.long 0x00 "CMICIC79,DMA Controller Client Matrix Internal Client Interface Configuration Register 79" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x213C++0x03 line.long 0x00 "CMICIC80,DMA Controller Client Matrix Internal Client Interface Configuration Register 80" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2140++0x03 line.long 0x00 "CMICIC81,DMA Controller Client Matrix Internal Client Interface Configuration Register 81" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2144++0x03 line.long 0x00 "CMICIC82,DMA Controller Client Matrix Internal Client Interface Configuration Register 82" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2148++0x03 line.long 0x00 "CMICIC83,DMA Controller Client Matrix Internal Client Interface Configuration Register 83" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x214C++0x03 line.long 0x00 "CMICIC84,DMA Controller Client Matrix Internal Client Interface Configuration Register 84" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2150++0x03 line.long 0x00 "CMICIC85,DMA Controller Client Matrix Internal Client Interface Configuration Register 85" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2154++0x03 line.long 0x00 "CMICIC86,DMA Controller Client Matrix Internal Client Interface Configuration Register 86" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2158++0x03 line.long 0x00 "CMICIC87,DMA Controller Client Matrix Internal Client Interface Configuration Register 87" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x215C++0x03 line.long 0x00 "CMICIC88,DMA Controller Client Matrix Internal Client Interface Configuration Register 88" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2160++0x03 line.long 0x00 "CMICIC89,DMA Controller Client Matrix Internal Client Interface Configuration Register 89" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2164++0x03 line.long 0x00 "CMICIC90,DMA Controller Client Matrix Internal Client Interface Configuration Register 90" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2168++0x03 line.long 0x00 "CMICIC91,DMA Controller Client Matrix Internal Client Interface Configuration Register 91" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x216C++0x03 line.long 0x00 "CMICIC92,DMA Controller Client Matrix Internal Client Interface Configuration Register 92" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2170++0x03 line.long 0x00 "CMICIC93,DMA Controller Client Matrix Internal Client Interface Configuration Register 93" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2174++0x03 line.long 0x00 "CMICIC94,DMA Controller Client Matrix Internal Client Interface Configuration Register 94" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2178++0x03 line.long 0x00 "CMICIC95,DMA Controller Client Matrix Internal Client Interface Configuration Register 95" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x217C++0x03 line.long 0x00 "CMICIC96,DMA Controller Client Matrix Internal Client Interface Configuration Register 96" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2180++0x03 line.long 0x00 "CMICIC97,DMA Controller Client Matrix Internal Client Interface Configuration Register 97" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2184++0x03 line.long 0x00 "CMICIC98,DMA Controller Client Matrix Internal Client Interface Configuration Register 98" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2188++0x03 line.long 0x00 "CMICIC99,DMA Controller Client Matrix Internal Client Interface Configuration Register 99" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x218C++0x03 line.long 0x00 "CMICIC100,DMA Controller Client Matrix Internal Client Interface Configuration Register 100" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2190++0x03 line.long 0x00 "CMICIC101,DMA Controller Client Matrix Internal Client Interface Configuration Register 101" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2194++0x03 line.long 0x00 "CMICIC102,DMA Controller Client Matrix Internal Client Interface Configuration Register 102" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" group.long 0x2198++0x03 line.long 0x00 "CMICIC103,DMA Controller Client Matrix Internal Client Interface Configuration Register 103" bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connected directly" bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "IRQ Disabled,IRQ Enabled" tree.end tree "CMCHIC 0-15" group.long 0x2800++0x03 line.long 0x00 "CMCHIC0,DMA Controller Client Matrix Channel Interface Configuration Register 0" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2804++0x03 line.long 0x00 "CMCHIC1,DMA Controller Client Matrix Channel Interface Configuration Register 1" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2808++0x03 line.long 0x00 "CMCHIC2,DMA Controller Client Matrix Channel Interface Configuration Register 2" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x280C++0x03 line.long 0x00 "CMCHIC3,DMA Controller Client Matrix Channel Interface Configuration Register 3" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2810++0x03 line.long 0x00 "CMCHIC4,DMA Controller Client Matrix Channel Interface Configuration Register 4" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2814++0x03 line.long 0x00 "CMCHIC5,DMA Controller Client Matrix Channel Interface Configuration Register 5" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2818++0x03 line.long 0x00 "CMCHIC6,DMA Controller Client Matrix Channel Interface Configuration Register 6" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x281C++0x03 line.long 0x00 "CMCHIC7,DMA Controller Client Matrix Channel Interface Configuration Register 7" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2820++0x03 line.long 0x00 "CMCHIC8,DMA Controller Client Matrix Channel Interface Configuration Register 8" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2824++0x03 line.long 0x00 "CMCHIC9,DMA Controller Client Matrix Channel Interface Configuration Register 9" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2828++0x03 line.long 0x00 "CMCHIC10,DMA Controller Client Matrix Channel Interface Configuration Register 10" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x282C++0x03 line.long 0x00 "CMCHIC11,DMA Controller Client Matrix Channel Interface Configuration Register 11" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2830++0x03 line.long 0x00 "CMCHIC12,DMA Controller Client Matrix Channel Interface Configuration Register 12" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2834++0x03 line.long 0x00 "CMCHIC13,DMA Controller Client Matrix Channel Interface Configuration Register 13" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x2838++0x03 line.long 0x00 "CMCHIC14,DMA Controller Client Matrix Channel Interface Configuration Register 14" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" group.long 0x283C++0x03 line.long 0x00 "CMCHIC15,DMA Controller Client Matrix Channel Interface Configuration Register 15" bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload CH. 0,Reload CH. 1,Reload CH. 2,Reload CH. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART CH. 0,BSTART CH. 1,BSTART CH. 2,BSTART CH. 3,BSTART CH. 4,BSTART CH. 5,BSTART CH. 6,BSTART CH. 7,BSTART CH. 8,BSTART CH. 9,BSTART CH. 10,BSTART CH. 11,BSTART CH. 12,BSTART CH. 13,BSTART CH. 14,BSTART CH. 15,BDONE CH. 0,BDONE CH. 1,BDONE CH. 2,BDONE CH. 3,BDONE CH. 4,BDONE CH. 5,BDONE CH. 6,BDONE CH.7,BDONE CH.8,BDONE CH.9,BDONE CH. 10,BDONE CH. 11,BDONE CH. 12,BDONE CH. 13,BDONE CH. 14,BDONE CH. 15,?..." bitfld.long 0x00 16.--18. " RLSLOT ,Reload slot replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7" hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface" tree.end width 0x0B tree.end tree "DMA-CS (DMA Complex Subsystem)" base ad:0xB4714000 width 12. rgroup.long 0x00++0x0F line.long 0x00 "ASR0,DMA Additional Control Additional Status Register 0" bitfld.long 0x00 0. " HBUSREQ ,HBUSREQ status" "Completed,Started" line.long 0x04 "ASR1,DMA Additional Control Additional Status Register 1" bitfld.long 0x04 16.--21. " BC_READ ,Block count for reading" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " BC_WRITE ,Block count for writing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "ASR2,DMA Additional Control Additional Status Register 2" bitfld.long 0x08 15. " SELECTED_[15] ,Current selected channel by DMA arbiter 15" "Not selected,Selected" bitfld.long 0x08 14. " [14] ,Current selected channel by DMA arbiter 14" "Not selected,Selected" bitfld.long 0x08 13. " [13] ,Current selected channel by DMA arbiter 13" "Not selected,Selected" bitfld.long 0x08 12. " [12] ,Current selected channel by DMA arbiter 12" "Not selected,Selected" newline bitfld.long 0x08 11. " [11] ,Current selected channel by DMA arbiter 11" "Not selected,Selected" bitfld.long 0x08 10. " [10] ,Current selected channel by DMA arbiter 10" "Not selected,Selected" bitfld.long 0x08 9. " [9] ,Current selected channel by DMA arbiter 9" "Not selected,Selected" bitfld.long 0x08 8. " [8] ,Current selected channel by DMA arbiter 8" "Not selected,Selected" newline bitfld.long 0x08 7. " [7] ,Current selected channel by DMA arbiter 7" "Not selected,Selected" bitfld.long 0x08 6. " [6] ,Current selected channel by DMA arbiter 6" "Not selected,Selected" bitfld.long 0x08 5. " [5] ,Current selected channel by DMA arbiter 5" "Not selected,Selected" bitfld.long 0x08 4. " [4] ,Current selected channel by DMA arbiter 4" "Not selected,Selected" newline bitfld.long 0x08 3. " [3] ,Current selected channel by DMA arbiter 3" "Not selected,Selected" bitfld.long 0x08 2. " [2] ,Current selected channel by DMA arbiter 2" "Not selected,Selected" bitfld.long 0x08 1. " [1] ,Current selected channel by DMA arbiter 1" "Not selected,Selected" bitfld.long 0x08 0. " [0] ,Current selected channel by DMA arbiter 0" "Not selected,Selected" line.long 0x0C "ASR3,DMA Additional Control Additional Status Register 3" bitfld.long 0x0C 15. " REQ_[15] ,Request bit 15" "Not requested,Requested" bitfld.long 0x0C 14. " [14] ,Request bit 14" "Not requested,Requested" bitfld.long 0x0C 13. " [13] ,Request bit 13" "Not requested,Requested" bitfld.long 0x0C 12. " [12] ,Request bit 12" "Not requested,Requested" newline bitfld.long 0x0C 11. " [11] ,Request bit 11" "Not requested,Requested" bitfld.long 0x0C 10. " [10] ,Request bit 10" "Not requested,Requested" bitfld.long 0x0C 9. " [9] ,Request bit 9" "Not requested,Requested" bitfld.long 0x0C 8. " [8] ,Request bit 8" "Not requested,Requested" newline bitfld.long 0x0C 7. " [7] ,Request bit 7" "Not requested,Requested" bitfld.long 0x0C 6. " [6] ,Request bit 6" "Not requested,Requested" bitfld.long 0x0C 5. " [5] ,Request bit 5" "Not requested,Requested" bitfld.long 0x0C 4. " [4] ,Request bit 4" "Not requested,Requested" newline bitfld.long 0x0C 3. " [3] ,Request bit 3" "Not requested,Requested" bitfld.long 0x0C 2. " [2] ,Request bit 2" "Not requested,Requested" bitfld.long 0x0C 1. " [1] ,Request bit 1" "Not requested,Requested" bitfld.long 0x0C 0. " [0] ,Request bit 0" "Not requested,Requested" rgroup.long 0x10++0x03 line.long 0x00 "ASR4,DMA Additional Control Additional Status Register 4" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 0" rgroup.long 0x14++0x03 line.long 0x00 "ASR5,DMA Additional Control Additional Status Register 5" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 1" rgroup.long 0x18++0x03 line.long 0x00 "ASR6,DMA Additional Control Additional Status Register 6" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 2" rgroup.long 0x1C++0x03 line.long 0x00 "ASR7,DMA Additional Control Additional Status Register 7" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 3" rgroup.long 0x20++0x03 line.long 0x00 "ASR8,DMA Additional Control Additional Status Register 8" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 4" rgroup.long 0x24++0x03 line.long 0x00 "ASR9,DMA Additional Control Additional Status Register 9" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 5" rgroup.long 0x28++0x03 line.long 0x00 "ASR10,DMA Additional Control Additional Status Register 10" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 6" rgroup.long 0x2C++0x03 line.long 0x00 "ASR11,DMA Additional Control Additional Status Register 11" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 7" rgroup.long 0x30++0x03 line.long 0x00 "ASR12,DMA Additional Control Additional Status Register 12" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 8" rgroup.long 0x34++0x03 line.long 0x00 "ASR13,DMA Additional Control Additional Status Register 13" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 9" rgroup.long 0x38++0x03 line.long 0x00 "ASR14,DMA Additional Control Additional Status Register 14" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 10" rgroup.long 0x3C++0x03 line.long 0x00 "ASR15,DMA Additional Control Additional Status Register 15" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 11" rgroup.long 0x40++0x03 line.long 0x00 "ASR16,DMA Additional Control Additional Status Register 16" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 12" rgroup.long 0x44++0x03 line.long 0x00 "ASR17,DMA Additional Control Additional Status Register 17" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 13" rgroup.long 0x48++0x03 line.long 0x00 "ASR18,DMA Additional Control Additional Status Register 18" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 14" rgroup.long 0x4C++0x03 line.long 0x00 "ASR19,DMA Additional Control Additional Status Register 19" hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 15" newline group.long 0x80++0x03 line.long 0x00 "CMCHICRDB0,DMA Additional Control CMCHIC Reload Data Bank Register 0" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--8. 1. " CI ,CI" group.long 0x84++0x03 line.long 0x00 "CMCHICRDB1,DMA Additional Control CMCHIC Reload Data Bank Register 1" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--8. 1. " CI ,CI" group.long 0x88++0x03 line.long 0x00 "CMCHICRDB2,DMA Additional Control CMCHIC Reload Data Bank Register 2" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--8. 1. " CI ,CI" group.long 0x8C++0x03 line.long 0x00 "CMCHICRDB3,DMA Additional Control CMCHIC Reload Data Bank Register 3" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--8. 1. " CI ,CI" group.long 0x90++0x03 line.long 0x00 "CMCHICRDB4,DMA Additional Control CMCHIC Reload Data Bank Register 4" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--8. 1. " CI ,CI" group.long 0x94++0x03 line.long 0x00 "CMCHICRDB5,DMA Additional Control CMCHIC Reload Data Bank Register 5" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--8. 1. " CI ,CI" group.long 0x98++0x03 line.long 0x00 "CMCHICRDB6,DMA Additional Control CMCHIC Reload Data Bank Register 6" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--8. 1. " CI ,CI" group.long 0x9C++0x03 line.long 0x00 "CMCHICRDB7,DMA Additional Control CMCHIC Reload Data Bank Register 7" bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--8. 1. " CI ,CI" newline group.long 0x100++0x03 line.long 0x00 "RTTSR,DMA Additional Control Reload Timer Trigger Select Register" hexmask.long.byte 0x00 24.--30. 1. " RLT3TS ,Reload timer 3 trigger select" hexmask.long.byte 0x00 16.--22. 1. " RLT2TS ,Reload timer 2 trigger select" hexmask.long.byte 0x00 8.--14. 1. " RLT1TS ,Reload timer 1 trigger select" hexmask.long.byte 0x00 0.--6. 1. " RLT0TS ,Reload timer 0 trigger select" wgroup.long 0x120++0x03 line.long 0x00 "RTSSSR,DMA Additional Control Reload Timer Synchronous Software Start Register" bitfld.long 0x00 3. " SSSR3 ,Synchronous software start register" "No effect,Give 0->1->0 pulse" bitfld.long 0x00 2. " SSSR2 ,Synchronous software start register" "No effect,Give 0->1->0 pulse" bitfld.long 0x00 1. " SSSR1 ,Synchronous software start register" "No effect,Give 0->1->0 pulse" bitfld.long 0x00 0. " SSSR0 ,Synchronous software start register" "No effect,Give 0->1->0 pulse" width 0x0B tree "RLT0" base ad:0xB4714800 width 8. group.long 0x00++0x03 line.long 0x00 "DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" if (((per.l(ad:0xB4714800+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start low,Start high" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714800+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "TMRLR,32-bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "TMR,32-bit Timer Register" width 0x0B tree.end tree "RLT1" base ad:0xB4714820 width 8. group.long 0x00++0x03 line.long 0x00 "DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" if (((per.l(ad:0xB4714820+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start low,Start high" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714820+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "TMRLR,32-bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "TMR,32-bit Timer Register" width 0x0B tree.end tree "RLT2" base ad:0xB4714840 width 8. group.long 0x00++0x03 line.long 0x00 "DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" if (((per.l(ad:0xB4714840+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start low,Start high" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714840+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "TMRLR,32-bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "TMR,32-bit Timer Register" width 0x0B tree.end tree "RLT3" base ad:0xB4714860 width 8. group.long 0x00++0x03 line.long 0x00 "DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" if (((per.l(ad:0xB4714860+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start low,Start high" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4714860+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "TMRLR,32-bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "TMR,32-bit Timer Register" width 0x0B tree.end tree.end tree "MPUH (Memory Protection Unit for the AMBA Advanced High Speed Bus)" base ad:0xB4710000 width 9. if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x00++0x03 line.long 0x00 "CTRL0,MPU AHB Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled" bitfld.long 0x00 16. " MPUEN ,MPU enable status" "Disabled,Enabled" bitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged,Privileged" newline bitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled" sif (!cpuis("S6J342*")) bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU stop feature" "Disabled,Enabled" bitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" endif newline bitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" bitfld.long 0x00 0. " NMI ,NMI interrupt flag" "Not detected,Detected" else if ((per.l(ad:0xB4710000)&0x10000)==0x00) group.long 0x00++0x03 line.long 0x00 "CTRL0,MPU AHB Control Register" bitfld.long 0x00 24.--26. " AP ,Access permissions for background region (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU enable status" "Disabled,Enabled" bitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged,Privileged" newline bitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled" sif (!cpuis("S6J342*")) bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU stop feature" "Disabled,Enabled" rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" endif newline rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "Not detected,Detected" else group.long 0x00++0x03 line.long 0x00 "CTRL0,MPU AHB Control Register" rbitfld.long 0x00 24.--26. " AP ,Access permissions for background region (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled" rbitfld.long 0x00 16. " MPUEN ,MPU enable status" "Disabled,Enabled" rbitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged,Privileged" newline rbitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled" sif (!cpuis("S6J342*")) bitfld.long 0x00 10. " MPUSTOPEN ,Enable for MPU stop feature" "Disabled,Enabled" rbitfld.long 0x00 9. " MPUSTOP ,MPU stop status" "Not stopped,Stopped" endif newline rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked" bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear" rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "Not detected,Detected" endif endif if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x04++0x03 line.long 0x00 "NMIEN,MPU AHB NMI Enable Register" bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled" else group.long 0x04++0x03 line.long 0x00 "NMIEN,MPU AHB NMI Enable Register" bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled" endif rgroup.long 0x08++0x07 line.long 0x00 "MERRC,MPU AHB Memory Error Control Register" bitfld.long 0x00 1. " HPROT ,AHB transfer privileged mode" "Not detected,Detected" bitfld.long 0x00 0. " HWRITE ,AHB transfer mode" "Not detected,Detected" line.long 0x04 "MERRA,MPU AHB Memory Error Address Register" sif (!cpuis("S6J342*")) tree "Region 1" if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x10++0x0B line.long 0x00 "CTRL1,MPU AHB Region 1 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR1,MPU AHB Start Address Register 1" line.long 0x08 "EADDR1,MPU AHB End Address Register 1" else if ((((per.l(ad:0xB4710000+0x10))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x10++0x0B line.long 0x00 "CTRL1,MPU AHB Region 1 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR1,MPU AHB Start Address Register 1" line.long 0x08 "EADDR1,MPU AHB End Address Register 1" else group.long 0x10++0x03 line.long 0x00 "CTRL1,MPU AHB Region 1 Control Register" rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" rgroup.long (0x10+0x04)++0x07 line.long 0x00 "SADDR1,MPU AHB Start Address Register 1" line.long 0x04 "EADDR1,MPU AHB End Address Register 1" endif endif tree.end tree "Region 2" if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x1C++0x0B line.long 0x00 "CTRL2,MPU AHB Region 2 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR2,MPU AHB Start Address Register 2" line.long 0x08 "EADDR2,MPU AHB End Address Register 2" else if ((((per.l(ad:0xB4710000+0x1C))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x1C++0x0B line.long 0x00 "CTRL2,MPU AHB Region 2 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR2,MPU AHB Start Address Register 2" line.long 0x08 "EADDR2,MPU AHB End Address Register 2" else group.long 0x1C++0x03 line.long 0x00 "CTRL2,MPU AHB Region 2 Control Register" rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" rgroup.long (0x1C+0x04)++0x07 line.long 0x00 "SADDR2,MPU AHB Start Address Register 2" line.long 0x04 "EADDR2,MPU AHB End Address Register 2" endif endif tree.end tree "Region 3" if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x28++0x0B line.long 0x00 "CTRL3,MPU AHB Region 3 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR3,MPU AHB Start Address Register 3" line.long 0x08 "EADDR3,MPU AHB End Address Register 3" else if ((((per.l(ad:0xB4710000+0x28))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x28++0x0B line.long 0x00 "CTRL3,MPU AHB Region 3 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR3,MPU AHB Start Address Register 3" line.long 0x08 "EADDR3,MPU AHB End Address Register 3" else group.long 0x28++0x03 line.long 0x00 "CTRL3,MPU AHB Region 3 Control Register" rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" rgroup.long (0x28+0x04)++0x07 line.long 0x00 "SADDR3,MPU AHB Start Address Register 3" line.long 0x04 "EADDR3,MPU AHB End Address Register 3" endif endif tree.end tree "Region 4" if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x34++0x0B line.long 0x00 "CTRL4,MPU AHB Region 4 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR4,MPU AHB Start Address Register 4" line.long 0x08 "EADDR4,MPU AHB End Address Register 4" else if ((((per.l(ad:0xB4710000+0x34))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x34++0x0B line.long 0x00 "CTRL4,MPU AHB Region 4 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR4,MPU AHB Start Address Register 4" line.long 0x08 "EADDR4,MPU AHB End Address Register 4" else group.long 0x34++0x03 line.long 0x00 "CTRL4,MPU AHB Region 4 Control Register" rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" rgroup.long (0x34+0x04)++0x07 line.long 0x00 "SADDR4,MPU AHB Start Address Register 4" line.long 0x04 "EADDR4,MPU AHB End Address Register 4" endif endif tree.end tree "Region 5" if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x40++0x0B line.long 0x00 "CTRL5,MPU AHB Region 5 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR5,MPU AHB Start Address Register 5" line.long 0x08 "EADDR5,MPU AHB End Address Register 5" else if ((((per.l(ad:0xB4710000+0x40))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x40++0x0B line.long 0x00 "CTRL5,MPU AHB Region 5 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR5,MPU AHB Start Address Register 5" line.long 0x08 "EADDR5,MPU AHB End Address Register 5" else group.long 0x40++0x03 line.long 0x00 "CTRL5,MPU AHB Region 5 Control Register" rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" rgroup.long (0x40+0x04)++0x07 line.long 0x00 "SADDR5,MPU AHB Start Address Register 5" line.long 0x04 "EADDR5,MPU AHB End Address Register 5" endif endif tree.end tree "Region 6" if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x4C++0x0B line.long 0x00 "CTRL6,MPU AHB Region 6 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR6,MPU AHB Start Address Register 6" line.long 0x08 "EADDR6,MPU AHB End Address Register 6" else if ((((per.l(ad:0xB4710000+0x4C))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x4C++0x0B line.long 0x00 "CTRL6,MPU AHB Region 6 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR6,MPU AHB Start Address Register 6" line.long 0x08 "EADDR6,MPU AHB End Address Register 6" else group.long 0x4C++0x03 line.long 0x00 "CTRL6,MPU AHB Region 6 Control Register" rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" rgroup.long (0x4C+0x04)++0x07 line.long 0x00 "SADDR6,MPU AHB Start Address Register 6" line.long 0x04 "EADDR6,MPU AHB End Address Register 6" endif endif tree.end tree "Region 7" if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x58++0x0B line.long 0x00 "CTRL7,MPU AHB Region 7 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR7,MPU AHB Start Address Register 7" line.long 0x08 "EADDR7,MPU AHB End Address Register 7" else if ((((per.l(ad:0xB4710000+0x58))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x58++0x0B line.long 0x00 "CTRL7,MPU AHB Region 7 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR7,MPU AHB Start Address Register 7" line.long 0x08 "EADDR7,MPU AHB End Address Register 7" else group.long 0x58++0x03 line.long 0x00 "CTRL7,MPU AHB Region 7 Control Register" rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" rgroup.long (0x58+0x04)++0x07 line.long 0x00 "SADDR7,MPU AHB Start Address Register 7" line.long 0x04 "EADDR7,MPU AHB End Address Register 7" endif endif tree.end tree "Region 8" if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x64++0x0B line.long 0x00 "CTRL8,MPU AHB Region 8 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR8,MPU AHB Start Address Register 8" line.long 0x08 "EADDR8,MPU AHB End Address Register 8" else if ((((per.l(ad:0xB4710000+0x64))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x64++0x0B line.long 0x00 "CTRL8,MPU AHB Region 8 Control Register" bitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" line.long 0x04 "SADDR8,MPU AHB Start Address Register 8" line.long 0x08 "EADDR8,MPU AHB End Address Register 8" else group.long 0x64++0x03 line.long 0x00 "CTRL8,MPU AHB Region 8 Control Register" rbitfld.long 0x00 8.--10. " AP ,Access permissions (privileged mode/non-privileged mode)" "No access/No access,Read+write/No access,Read+write/Read only,Read+write/Read+write,No access/No access,Read only/No access,Read only/Read only,Read+write/Read+write" bitfld.long 0x00 1. " MPUENC ,Memory protection enable" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Memory protection status" "Disabled,Enabled" rgroup.long (0x64+0x04)++0x07 line.long 0x00 "SADDR8,MPU AHB Start Address Register 8" line.long 0x04 "EADDR8,MPU AHB End Address Register 8" endif endif tree.end else if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x10++0x03 line.long 0x00 "CTRL1,MPU16 AHB Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x10))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x10++0x03 line.long 0x00 "CTRL1,MPU16 AHB Region Control Register 1" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "CTRL1,MPU16 AHB Region Control Register 1" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x1C++0x03 line.long 0x00 "CTRL2,MPU16 AHB Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x1C))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x1C++0x03 line.long 0x00 "CTRL2,MPU16 AHB Region Control Register 2" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "CTRL2,MPU16 AHB Region Control Register 2" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x28++0x03 line.long 0x00 "CTRL3,MPU16 AHB Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x28))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x28++0x03 line.long 0x00 "CTRL3,MPU16 AHB Region Control Register 3" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x28++0x03 line.long 0x00 "CTRL3,MPU16 AHB Region Control Register 3" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x34++0x03 line.long 0x00 "CTRL4,MPU16 AHB Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x34))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x34++0x03 line.long 0x00 "CTRL4,MPU16 AHB Region Control Register 4" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "CTRL4,MPU16 AHB Region Control Register 4" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x40++0x03 line.long 0x00 "CTRL5,MPU16 AHB Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x40))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x40++0x03 line.long 0x00 "CTRL5,MPU16 AHB Region Control Register 5" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x40++0x03 line.long 0x00 "CTRL5,MPU16 AHB Region Control Register 5" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x4C++0x03 line.long 0x00 "CTRL6,MPU16 AHB Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x4C))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x4C++0x03 line.long 0x00 "CTRL6,MPU16 AHB Region Control Register 6" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x4C++0x03 line.long 0x00 "CTRL6,MPU16 AHB Region Control Register 6" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x58++0x03 line.long 0x00 "CTRL7,MPU16 AHB Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x58))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x58++0x03 line.long 0x00 "CTRL7,MPU16 AHB Region Control Register 7" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x58++0x03 line.long 0x00 "CTRL7,MPU16 AHB Region Control Register 7" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if ((per.l(ad:0xB4710000)&0x100)==0x100) rgroup.long 0x64++0x03 line.long 0x00 "CTRL8,MPU16 AHB Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x64))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x64++0x03 line.long 0x00 "CTRL8,MPU16 AHB Region Control Register 8" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x64++0x03 line.long 0x00 "CTRL8,MPU16 AHB Region Control Register 8" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if (((per.l(ad:0xB4710000))&0x100)==0x100) rgroup.long 0x110++0x03 line.long 0x00 "CTRL9,MPU16 AHB Region Control Register 9" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x110))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x110++0x03 line.long 0x00 "CTRL9,MPU16 AHB Region Control Register 9" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x110++0x03 line.long 0x00 "CTRL9,MPU16 AHB Region Control Register 9" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if (((per.l(ad:0xB4710000))&0x100)==0x100) rgroup.long 0x11C++0x03 line.long 0x00 "CTRL10,MPU16 AHB Region Control Register 10" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x11C))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x11C++0x03 line.long 0x00 "CTRL10,MPU16 AHB Region Control Register 10" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x11C++0x03 line.long 0x00 "CTRL10,MPU16 AHB Region Control Register 10" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if (((per.l(ad:0xB4710000))&0x100)==0x100) rgroup.long 0x128++0x03 line.long 0x00 "CTRL11,MPU16 AHB Region Control Register 11" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x128))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x128++0x03 line.long 0x00 "CTRL11,MPU16 AHB Region Control Register 11" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x128++0x03 line.long 0x00 "CTRL11,MPU16 AHB Region Control Register 11" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if (((per.l(ad:0xB4710000))&0x100)==0x100) rgroup.long 0x134++0x03 line.long 0x00 "CTRL12,MPU16 AHB Region Control Register 12" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x134))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x134++0x03 line.long 0x00 "CTRL12,MPU16 AHB Region Control Register 12" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x134++0x03 line.long 0x00 "CTRL12,MPU16 AHB Region Control Register 12" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if (((per.l(ad:0xB4710000))&0x100)==0x100) rgroup.long 0x140++0x03 line.long 0x00 "CTRL13,MPU16 AHB Region Control Register 13" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x140))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x140++0x03 line.long 0x00 "CTRL13,MPU16 AHB Region Control Register 13" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x140++0x03 line.long 0x00 "CTRL13,MPU16 AHB Region Control Register 13" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if (((per.l(ad:0xB4710000))&0x100)==0x100) rgroup.long 0x14C++0x03 line.long 0x00 "CTRL14,MPU16 AHB Region Control Register 14" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x14C))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x14C++0x03 line.long 0x00 "CTRL14,MPU16 AHB Region Control Register 14" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x14C++0x03 line.long 0x00 "CTRL14,MPU16 AHB Region Control Register 14" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if (((per.l(ad:0xB4710000))&0x100)==0x100) rgroup.long 0x158++0x03 line.long 0x00 "CTRL15,MPU16 AHB Region Control Register 15" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x158))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x158++0x03 line.long 0x00 "CTRL15,MPU16 AHB Region Control Register 15" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x158++0x03 line.long 0x00 "CTRL15,MPU16 AHB Region Control Register 15" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if (((per.l(ad:0xB4710000))&0x100)==0x100) rgroup.long 0x164++0x03 line.long 0x00 "CTRL16,MPU16 AHB Region Control Register 16" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" bitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else if ((((per.l(ad:0xB4710000+0x164))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x10000)==0x0000)) group.long 0x164++0x03 line.long 0x00 "CTRL16,MPU16 AHB Region Control Register 16" bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" else group.long 0x164++0x03 line.long 0x00 "CTRL16,MPU16 AHB Region Control Register 16" rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled" rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled" endif endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x14-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x14++0x03 line.long 0x00 "SADDR1,MPU16 AHB Start Address Register 1" else rgroup.long 0x14++0x03 line.long 0x00 "SADDR1,MPU16 AHB Start Address Register 1" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x20-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x20++0x03 line.long 0x00 "SADDR2,MPU16 AHB Start Address Register 2" else rgroup.long 0x20++0x03 line.long 0x00 "SADDR2,MPU16 AHB Start Address Register 2" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x2C-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x2C++0x03 line.long 0x00 "SADDR3,MPU16 AHB Start Address Register 3" else rgroup.long 0x2C++0x03 line.long 0x00 "SADDR3,MPU16 AHB Start Address Register 3" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x38-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x38++0x03 line.long 0x00 "SADDR4,MPU16 AHB Start Address Register 4" else rgroup.long 0x38++0x03 line.long 0x00 "SADDR4,MPU16 AHB Start Address Register 4" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x44-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x44++0x03 line.long 0x00 "SADDR5,MPU16 AHB Start Address Register 5" else rgroup.long 0x44++0x03 line.long 0x00 "SADDR5,MPU16 AHB Start Address Register 5" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x50-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x50++0x03 line.long 0x00 "SADDR6,MPU16 AHB Start Address Register 6" else rgroup.long 0x50++0x03 line.long 0x00 "SADDR6,MPU16 AHB Start Address Register 6" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x5C-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x5C++0x03 line.long 0x00 "SADDR7,MPU16 AHB Start Address Register 7" else rgroup.long 0x5C++0x03 line.long 0x00 "SADDR7,MPU16 AHB Start Address Register 7" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x68-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x68++0x03 line.long 0x00 "SADDR8,MPU16 AHB Start Address Register 8" else rgroup.long 0x68++0x03 line.long 0x00 "SADDR8,MPU16 AHB Start Address Register 8" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x114-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x114++0x03 line.long 0x00 "SADDR9,MPU16 AHB Start Address Register 9" else rgroup.long 0x114++0x03 line.long 0x00 "SADDR9,MPU16 AHB Start Address Register 9" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x120-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x120++0x03 line.long 0x00 "SADDR10,MPU16 AHB Start Address Register 10" else rgroup.long 0x120++0x03 line.long 0x00 "SADDR10,MPU16 AHB Start Address Register 10" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x12C-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x12C++0x03 line.long 0x00 "SADDR11,MPU16 AHB Start Address Register 11" else rgroup.long 0x12C++0x03 line.long 0x00 "SADDR11,MPU16 AHB Start Address Register 11" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x138-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x138++0x03 line.long 0x00 "SADDR12,MPU16 AHB Start Address Register 12" else rgroup.long 0x138++0x03 line.long 0x00 "SADDR12,MPU16 AHB Start Address Register 12" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x144-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x144++0x03 line.long 0x00 "SADDR13,MPU16 AHB Start Address Register 13" else rgroup.long 0x144++0x03 line.long 0x00 "SADDR13,MPU16 AHB Start Address Register 13" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x150-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x150++0x03 line.long 0x00 "SADDR14,MPU16 AHB Start Address Register 14" else rgroup.long 0x150++0x03 line.long 0x00 "SADDR14,MPU16 AHB Start Address Register 14" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x15C-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x15C++0x03 line.long 0x00 "SADDR15,MPU16 AHB Start Address Register 15" else rgroup.long 0x15C++0x03 line.long 0x00 "SADDR15,MPU16 AHB Start Address Register 15" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x168-0x04))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x168++0x03 line.long 0x00 "SADDR16,MPU16 AHB Start Address Register 16" else rgroup.long 0x168++0x03 line.long 0x00 "SADDR16,MPU16 AHB Start Address Register 16" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x18-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x18++0x03 line.long 0x00 "EADDR1,MPU16 AHB End Address Register 1" else rgroup.long 0x18++0x03 line.long 0x00 "EADDR1,MPU16 AHB End Address Register 1" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x24-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x24++0x03 line.long 0x00 "EADDR2,MPU16 AHB End Address Register 2" else rgroup.long 0x24++0x03 line.long 0x00 "EADDR2,MPU16 AHB End Address Register 2" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x30-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x30++0x03 line.long 0x00 "EADDR3,MPU16 AHB End Address Register 3" else rgroup.long 0x30++0x03 line.long 0x00 "EADDR3,MPU16 AHB End Address Register 3" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x3C-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x3C++0x03 line.long 0x00 "EADDR4,MPU16 AHB End Address Register 4" else rgroup.long 0x3C++0x03 line.long 0x00 "EADDR4,MPU16 AHB End Address Register 4" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x48-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x48++0x03 line.long 0x00 "EADDR5,MPU16 AHB End Address Register 5" else rgroup.long 0x48++0x03 line.long 0x00 "EADDR5,MPU16 AHB End Address Register 5" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x54-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x54++0x03 line.long 0x00 "EADDR6,MPU16 AHB End Address Register 6" else rgroup.long 0x54++0x03 line.long 0x00 "EADDR6,MPU16 AHB End Address Register 6" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x60-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x60++0x03 line.long 0x00 "EADDR7,MPU16 AHB End Address Register 7" else rgroup.long 0x60++0x03 line.long 0x00 "EADDR7,MPU16 AHB End Address Register 7" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x6C-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x6C++0x03 line.long 0x00 "EADDR8,MPU16 AHB End Address Register 8" else rgroup.long 0x6C++0x03 line.long 0x00 "EADDR8,MPU16 AHB End Address Register 8" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x118-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x118++0x03 line.long 0x00 "EADDR9,MPU16 AHB End Address Register 9" else rgroup.long 0x118++0x03 line.long 0x00 "EADDR9,MPU16 AHB End Address Register 9" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x124-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x124++0x03 line.long 0x00 "EADDR10,MPU16 AHB End Address Register 10" else rgroup.long 0x124++0x03 line.long 0x00 "EADDR10,MPU16 AHB End Address Register 10" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x130-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x130++0x03 line.long 0x00 "EADDR11,MPU16 AHB End Address Register 11" else rgroup.long 0x130++0x03 line.long 0x00 "EADDR11,MPU16 AHB End Address Register 11" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x13C-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x13C++0x03 line.long 0x00 "EADDR12,MPU16 AHB End Address Register 12" else rgroup.long 0x13C++0x03 line.long 0x00 "EADDR12,MPU16 AHB End Address Register 12" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x148-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x148++0x03 line.long 0x00 "EADDR13,MPU16 AHB End Address Register 13" else rgroup.long 0x148++0x03 line.long 0x00 "EADDR13,MPU16 AHB End Address Register 13" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x154-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x154++0x03 line.long 0x00 "EADDR14,MPU16 AHB End Address Register 14" else rgroup.long 0x154++0x03 line.long 0x00 "EADDR14,MPU16 AHB End Address Register 14" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x160-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x160++0x03 line.long 0x00 "EADDR15,MPU16 AHB End Address Register 15" else rgroup.long 0x160++0x03 line.long 0x00 "EADDR15,MPU16 AHB End Address Register 15" endif if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x16C-0x08))&0x01)==0x00)||(((per.l(ad:0xB4710000))&0x100)==0x00) group.long 0x16C++0x03 line.long 0x00 "EADDR16,MPU16 AHB End Address Register 16" else rgroup.long 0x16C++0x03 line.long 0x00 "EADDR16,MPU16 AHB End Address Register 16" endif endif newline sif (!cpuis("S6J342*")) wgroup.long 0x70++0x03 line.long 0x00 "UNLOCK,MPU AHB Unlock Register" else group.long 0x70++0x03 line.long 0x00 "UNLOCK,MPU AHB Unlock Register" endif rgroup.long 0x74++0x03 line.long 0x00 "MID,MPU AHB Module ID Register" width 0x0B tree.end tree.open "CAN-FD" tree "Channel 0" base ad:0xB4900000 width 8. if (((per.l(ad:0xB4900000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4900000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4900000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4900000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4900000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4900000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4900000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4900000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4900000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4900000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end tree "Channel 1" base ad:0xB4910000 width 8. if (((per.l(ad:0xB4910000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4910000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4910000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4910000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4910000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4910000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4910000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4910000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4910000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4910000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end tree "Channel 2" base ad:0xB4920000 width 8. if (((per.l(ad:0xB4920000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4920000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4920000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4920000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4920000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4920000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4920000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4920000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4920000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4920000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4920000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end tree "Channel 3" base ad:0xB4930000 width 8. if (((per.l(ad:0xB4930000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4930000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4930000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4930000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4930000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4930000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4930000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4930000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4930000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4930000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4930000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end tree "Channel 4" base ad:0xB4940000 width 8. if (((per.l(ad:0xB4940000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4940000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4940000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4940000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4940000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4940000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4940000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4940000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4940000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4940000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4940000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end tree "Channel 8" base ad:0xB4950000 width 8. if (((per.l(ad:0xB4950000+0x00))&0xF000)==0x1000) if (((per.l(ad:0xB4950000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif else if (((per.l(ad:0xB4950000+0x00))&0xF0)==0x30) rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,?..." else rgroup.long 0x00++0x03 line.long 0x00 "CREL,Core Release Register" bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,?..." newline bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 12.--15. " MON ,Time stamp month (second digit)" "0,1,-,-,-,-,-,-,-,-,?..." bitfld.long 0x00 8.--11. ",Time stamp month (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 4.--7. " DAY ,Time stamp day (second digit)" "0,1,2,3,-,-,-,-,-,-,?..." bitfld.long 0x00 0.--3. ",Time stamp day (first digit)" "0,1,2,3,4,5,6,7,8,9,?..." endif endif rgroup.long 0x04++0x03 line.long 0x00 "ENDN,Endian Register" if (((per.l(ad:0xB4950000+0x0C))&0x800000)==0x800000) if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,?..." newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "DBTP,Fast Bit Timing & Prescaler Register" bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled" bitfld.long 0x00 16.--20. " DBRP ,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DSJW ,Data (Re) synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif if (((per.l(ad:0xB4950000+0x18))&0x80)==0x80) group.long 0x10++0x03 line.long 0x00 "TEST,Test Register" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" else rgroup.long 0x10++0x03 line.long 0x00 "TEST,Test Register" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "CAN Core,Sample Point,Dominant,Recessive" newline bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled" endif group.long 0x14++0x03 line.long 0x00 "RWD,RAM Watchdog Register" hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value" hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog configuration" if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" bitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" bitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" bitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline bitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" bitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" bitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" bitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" elif (((per.l(ad:0xB4950000+0x18))&0x01)==0x01) group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline bitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" else group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control Register" rbitfld.long 0x00 15. " NISO ,Non ISO operation" "ISO,Bosch" rbitfld.long 0x00 14. " TXP ,Transmit pause" "Disabled,Enabled" rbitfld.long 0x00 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled" newline rbitfld.long 0x00 12. " PXHD ,Protocol exception handling disable" "No,Yes" rbitfld.long 0x00 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled" rbitfld.long 0x00 8. " FDOE ,FD operation enable" "Disabled,Enabled" newline rbitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" rbitfld.long 0x00 6. " DAR ,Disable automatic retransmission" "No,Yes" rbitfld.long 0x00 5. " MON ,Bus monitoring mode" "Disabled,Enabled" newline bitfld.long 0x00 4. " CSR ,Clock stop request" "Not requested,Requested" rbitfld.long 0x00 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged" rbitfld.long 0x00 2. " ASM ,Restricted operation mode" "Disabled,Enabled" newline rbitfld.long 0x00 1. " CCE ,Configuration change enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" endif if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" else rgroup.long 0x1C++0x07 line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register" hexmask.long.byte 0x00 25.--31. 1. " NSJW ,Nominal (Re) synchronization jump width" hexmask.long.word 0x00 16.--24. 1. " NBRP ,Nominal bit rate prescaler" hexmask.long.byte 0x00 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point" newline hexmask.long.byte 0x00 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point" line.long 0x04 "TSCC,Timestamp Counter Configuration Register" bitfld.long 0x04 16.--19. " TCP ,Timestamp counter prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 0.--1. " TSS ,Timestamp select" "Not selected,Incremented by TCP,External counter,Not selected" endif group.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp counter" if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" else rgroup.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration Register" hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout period" bitfld.long 0x00 1.--2. " TOS ,Timeout select" "Continuous,TX FIFO,RX FIFO 0,RX FIFO 1" bitfld.long 0x00 0. " ETOC ,Enable timeout counter" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout counter" newline hgroup.long 0x40++0x03 hide.long 0x00 "ECR,Error Counter Register" in hgroup.long 0x44++0x03 hide.long 0x00 "PSR,Protocol Status Register" in newline sif (cpuis("S6J336*")||cpuis("S6J337*"))||cpuis("S6J342*") if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length" endif else if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" else rgroup.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensation Register" hexmask.long.byte 0x00 8.--15. 0x01 " TDCO ,Transmitter delay compensation offset" hexmask.long.byte 0x00 0.--7. 1. " TDCF ,Transmitter delay compensation filter window length" endif endif group.long 0x50++0x0F line.long 0x00 "IR,Interrupt Register" eventfld.long 0x00 29. " ARA ,Access to reserved address" "No Error,Error" eventfld.long 0x00 28. " PED ,Protocol error in data phase" "No Error,Error" eventfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No Error,Error" newline eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BO ,Bus_Off status" "Not Changed,Changed" eventfld.long 0x00 24. " EW ,Warning status" "Not Changed,Changed" newline eventfld.long 0x00 23. " EP ,Error passive" "Not Changed,Changed" eventfld.long 0x00 22. " ELO ,Error logging overflow" "No Overflow,Overflow" eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "No Error,Error uncorrected" newline eventfld.long 0x00 20. " BEC ,Bit error corrected" "No Error,Error corrected" eventfld.long 0x00 19. " DRX ,Message stored to dedicated RX buffer" "No,Yes" eventfld.long 0x00 18. " TOO ,Timeout occurred" "No Timeout,Timeout" newline eventfld.long 0x00 17. " MRAF ,Message RAM access failure" "No Failure,Failure" eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not wrapped,Wrapped" eventfld.long 0x00 15. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" newline eventfld.long 0x00 14. " TEFF ,TX event FIFO full" "Not Full,Full" eventfld.long 0x00 13. " TEFW ,TX event FIFO watermark reached" "Not Reached,Reached" eventfld.long 0x00 12. " TEFN ,TX event FIFO new entry" "No,Yes" newline eventfld.long 0x00 11. " TFE ,TX FIFO empty" "Not empty,Empty" eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not Finished,Finished" eventfld.long 0x00 9. " TC ,Transmission completed" "Not Completed,Completed" newline eventfld.long 0x00 8. " HPM ,High priority message received" "Not Received,Received" eventfld.long 0x00 7. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" eventfld.long 0x00 6. " RF1F ,RX FIFO 1 full" "Not Full,Full" newline eventfld.long 0x00 5. " RF1W ,RX FIFO 1 watermark reached" "Not Reached,Reached" eventfld.long 0x00 4. " RF1N ,RX FIFO 1 new message" "No,Yes" eventfld.long 0x00 3. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" newline eventfld.long 0x00 2. " RF0F ,RX FIFO 0 full" "Not Full,Full" eventfld.long 0x00 1. " RF0W ,RX FIFO 0 watermark reached" "Not Reached,Reached" eventfld.long 0x00 0. " RF0N ,RX FIFO 0 new message" "No,Yes" line.long 0x04 "IE,Interrupt Enable Register" bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled" bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled" bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled" newline bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled" bitfld.long 0x04 25. " BOE ,Bus_Off status enable" "Disabled,Enabled" bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled" bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled" bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled" newline bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled" bitfld.long 0x04 19. " DRXE ,Message stored to dedicated RX buffer enable" "Disabled,Enabled" bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled" bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled" bitfld.long 0x04 15. " TEFLE ,TX event FIFO element lost enable" "Disabled,Enabled" newline bitfld.long 0x04 14. " TEFFE ,TX event FIFO full enable" "Disabled,Enabled" bitfld.long 0x04 13. " TEFWE ,TX event FIFO watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 12. " TEFNE ,TX event FIFO new entry enable" "Disabled,Enabled" newline bitfld.long 0x04 11. " TFEE ,TX FIFO empty enable" "Disabled,Enabled" bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled" bitfld.long 0x04 9. " TCE ,Transmission completed enable" "Disabled,Enabled" newline bitfld.long 0x04 8. " HPME ,High priority message received enable" "Disabled,Enabled" bitfld.long 0x04 7. " RF1LE ,RX FIFO 1 message lost enable" "Disabled,Enabled" bitfld.long 0x04 6. " RF1FE ,RX FIFO 1 full enable" "Disabled,Enabled" newline bitfld.long 0x04 5. " RF1WE ,RX FIFO 1 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 4. " RF1NE ,RX FIFO 1 new message enable" "Disabled,Enabled" bitfld.long 0x04 3. " RF0LE ,RX FIFO 0 message lost enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " RF0FE ,RX FIFO 0 full enable" "Disabled,Enabled" bitfld.long 0x04 1. " RF0WE ,RX FIFO 0 watermark reached enable" "Disabled,Enabled" bitfld.long 0x04 0. " RF0NE ,RX FIFO 0 new message enable" "Disabled,Enabled" line.long 0x08 "ILS,Interrupt Line Select Register" bitfld.long 0x08 29. " ARAL ,Access to reserved address line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 28. " PEDL ,Protocol error in data phase line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 25. " BOL ,Bus_Off status interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 19. " DRXL ,Message stored to dedicated RX buffer interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 15. " TEFLL ,TX event FIFO element lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 14. " TEFFL ,TX event FIFO full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 13. " TEFWL ,TX event FIFO watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 12. " TEFNL ,TX event FIFO new entry interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 11. " TFEL ,TX FIFO empty interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 9. " TCL ,Transmission completed interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 8. " HPML ,High priority message received interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 7. " RF1LL ,RX FIFO 1 message lost interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 6. " RF1FE ,RX FIFO 1 full interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 5. " RF1WL ,RX FIFO 1 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 4. " RF1NL ,RX FIFO 1 new message interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 3. " RF0LL ,RX FIFO 0 message lost interrupt line" "Canfd_Int0,Canfd_Int1" newline bitfld.long 0x08 2. " RF0FL ,RX FIFO 0 full interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 1. " RF0WL ,RX FIFO 0 watermark reached interrupt line" "Canfd_Int0,Canfd_Int1" bitfld.long 0x08 0. " RF0NL ,RX FIFO 0 new message interrupt line" "Canfd_Int0,Canfd_Int1" line.long 0x0C "ILE,Interrupt Line Enable Register" bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled" bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled" if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" else rgroup.long 0x80++0x0B line.long 0x00 "GFC,Global Filter Configuration Register" bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject" bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject" newline bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject" line.long 0x04 "SIDFC,Standard ID Filter Configuration Register" hexmask.long.byte 0x04 16.--23. 1. " LSS ,List size standard" hexmask.long.word 0x04 2.--15. 0x04 " FLSSA ,Filter list standard start address" line.long 0x08 "XIDFC,Extended ID Filter Configuration Register" hexmask.long.byte 0x08 16.--22. 1. " LSE ,List size extended" hexmask.long.word 0x08 2.--15. 0x04 " FLESA ,Filter list extended start address" rgroup.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask Register" hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask" endif if (((per.l(ad:0xB4950000+0x94))&0x80)==0x80) rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status Register" bitfld.long 0x00 15. " FLST ,Filter list" "Standard,Extended" hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index" bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No FIFO,FIFO Message Lost,Stored In FIFO 0,Stored In FIFO 1" newline endif group.long 0x98++0x07 line.long 0x00 "NDAT1,New Data 1 Register" eventfld.long 0x00 31. " ND[31] ,New data_31" "Not Updated,Updated" eventfld.long 0x00 30. " [30] ,New data_30" "Not Updated,Updated" eventfld.long 0x00 29. " [29] ,New data_29" "Not Updated,Updated" newline eventfld.long 0x00 28. " [28] ,New data_28" "Not Updated,Updated" eventfld.long 0x00 27. " [27] ,New data_27" "Not Updated,Updated" eventfld.long 0x00 26. " [26] ,New data_26" "Not Updated,Updated" newline eventfld.long 0x00 25. " [25] ,New data_25" "Not Updated,Updated" eventfld.long 0x00 24. " [24] ,New data_24" "Not Updated,Updated" eventfld.long 0x00 23. " [23] ,New data_23" "Not Updated,Updated" newline eventfld.long 0x00 22. " [22] ,New data_22" "Not Updated,Updated" eventfld.long 0x00 21. " [21] ,New data_21" "Not Updated,Updated" eventfld.long 0x00 20. " [20] ,New data_20" "Not Updated,Updated" newline eventfld.long 0x00 19. " [19] ,New data_19" "Not Updated,Updated" eventfld.long 0x00 18. " [18] ,New data_18" "Not Updated,Updated" eventfld.long 0x00 17. " [17] ,New data_17" "Not Updated,Updated" newline eventfld.long 0x00 16. " [16] ,New data_16" "Not Updated,Updated" eventfld.long 0x00 15. " [15] ,New data_15" "Not Updated,Updated" eventfld.long 0x00 14. " [14] ,New data_14" "Not Updated,Updated" newline eventfld.long 0x00 13. " [13] ,New data_13" "Not Updated,Updated" eventfld.long 0x00 12. " [12] ,New data_12" "Not Updated,Updated" eventfld.long 0x00 11. " [11] ,New data_11" "Not Updated,Updated" newline eventfld.long 0x00 10. " [10] ,New data_10" "Not Updated,Updated" eventfld.long 0x00 9. " [9] ,New data_9" "Not Updated,Updated" eventfld.long 0x00 8. " [8] ,New data_8" "Not Updated,Updated" newline eventfld.long 0x00 7. " [7] ,New data_7" "Not Updated,Updated" eventfld.long 0x00 6. " [6] ,New data_6" "Not Updated,Updated" eventfld.long 0x00 5. " [5] ,New data_5" "Not Updated,Updated" newline eventfld.long 0x00 4. " [4] ,New data_4" "Not Updated,Updated" eventfld.long 0x00 3. " [3] ,New data_3" "Not Updated,Updated" eventfld.long 0x00 2. " [2] ,New data_2" "Not Updated,Updated" newline eventfld.long 0x00 1. " [1] ,New data_1" "Not Updated,Updated" eventfld.long 0x00 0. " [0] ,New data_0" "Not Updated,Updated" line.long 0x04 "NDAT2,New Data 2 Register" eventfld.long 0x04 31. " ND[63] ,New data_63" "Not Updated,Updated" eventfld.long 0x04 30. " [62] ,New data_62" "Not Updated,Updated" eventfld.long 0x04 29. " [61] ,New data_61" "Not Updated,Updated" newline eventfld.long 0x04 28. " [60] ,New data_60" "Not Updated,Updated" eventfld.long 0x04 27. " [59] ,New data_59" "Not Updated,Updated" eventfld.long 0x04 26. " [58] ,New data_58" "Not Updated,Updated" newline eventfld.long 0x04 25. " [57] ,New data_57" "Not Updated,Updated" eventfld.long 0x04 24. " [56] ,New data_56" "Not Updated,Updated" eventfld.long 0x04 23. " [55] ,New data_55" "Not Updated,Updated" newline eventfld.long 0x04 22. " [54] ,New data_54" "Not Updated,Updated" eventfld.long 0x04 21. " [53] ,New data_53" "Not Updated,Updated" eventfld.long 0x04 20. " [52] ,New data_52" "Not Updated,Updated" newline eventfld.long 0x04 19. " [51] ,New data_51" "Not Updated,Updated" eventfld.long 0x04 18. " [50] ,New data_50" "Not Updated,Updated" eventfld.long 0x04 17. " [49] ,New data_49" "Not Updated,Updated" newline eventfld.long 0x04 16. " [48] ,New data_48" "Not Updated,Updated" eventfld.long 0x04 15. " [47] ,New data_47" "Not Updated,Updated" eventfld.long 0x04 14. " [46] ,New data_46" "Not Updated,Updated" newline eventfld.long 0x04 13. " [45] ,New data_45" "Not Updated,Updated" eventfld.long 0x04 12. " [44] ,New data_44" "Not Updated,Updated" eventfld.long 0x04 11. " [43] ,New data_43" "Not Updated,Updated" newline eventfld.long 0x04 10. " [42] ,New data_42" "Not Updated,Updated" eventfld.long 0x04 9. " [41] ,New data_41" "Not Updated,Updated" eventfld.long 0x04 8. " [40] ,New data_40" "Not Updated,Updated" newline eventfld.long 0x04 7. " [39] ,New data_39" "Not Updated,Updated" eventfld.long 0x04 6. " [38] ,New data_38" "Not Updated,Updated" eventfld.long 0x04 5. " [37] ,New data_37" "Not Updated,Updated" newline eventfld.long 0x04 4. " [36] ,New data_36" "Not Updated,Updated" eventfld.long 0x04 3. " [35] ,New data_35" "Not Updated,Updated" eventfld.long 0x04 2. " [34] ,New data_34" "Not Updated,Updated" newline eventfld.long 0x04 1. " [33] ,New data_33" "Not Updated,Updated" eventfld.long 0x04 0. " [32] ,New data_32" "Not Updated,Updated" if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" else rgroup.long 0xA0++0x03 line.long 0x00 "RXF0C,RX FIFO 0 Configuration Register" bitfld.long 0x00 31. " F0OM ,FIFO 0 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x00 24.--30. 1. " F0WM ,RX FIFO 0 watermark" hexmask.long.byte 0x00 16.--22. 1. " F0S ,RX FIFO 0 size" newline hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,RX FIFO 0 start address" endif rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,RX FIFO 0 Status Register" bitfld.long 0x00 25. " RF0L ,RX FIFO 0 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F0F ,RX FIFO 0 full" "Not full,Full" bitfld.long 0x00 16.--21. " F0PI ,RX FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. " F0GI ,RX FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F0FL ,RX 0 fill level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register" bitfld.long 0x00 0.--5. " F0AI ,RX FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" else rgroup.long 0xAC++0x07 line.long 0x00 "RXBC,RX Buffer Configuration Register" hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,RX buffer start address" line.long 0x04 "RXF1C,RX FIFO 1 Configuration Register" bitfld.long 0x04 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite" hexmask.long.byte 0x04 24.--30. 1. " F1WM ,RX FIFO 1 watermark" hexmask.long.byte 0x04 16.--22. 1. " F1S ,RX FIFO 1 size" newline hexmask.long.word 0x04 2.--15. 0x04 " F1SA ,RX FIFO 1 start address" endif rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,RX FIFO 1 Status Register" bitfld.long 0x00 30.--31. " DMS ,Debug message status" "Idle,A Received,A B Received,A B C Received" bitfld.long 0x00 25. " RF1L ,RX FIFO 1 message lost" "Not Lost,Lost" bitfld.long 0x00 24. " F1F ,RX FIFO 1 full" "Not Full,Full" newline bitfld.long 0x00 16.--21. " F1PI ,RX FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " F1GI ,RX FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--6. 1. " F1FL ,RX FIFO 1 fill level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,RX FIFO 1 Acknowledge Register" bitfld.long 0x00 0.--5. " F1AI ,RX FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX Queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" else rgroup.long 0xBC++0x07 line.long 0x00 "RXESC,RX Buffer/FIFO Element Size Configuration Register" bitfld.long 0x00 8.--10. " RBDS ,RX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 4.--6. " F1DS ,RX FIFO 1 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" bitfld.long 0x00 0.--2. " F0DS ,RX FIFO 0 data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" line.long 0x04 "TXBC,TX Buffer Configuration Register" bitfld.long 0x04 30. " TFQM ,TX FIFO/queue mode" "TX FIFO,TX queue" bitfld.long 0x04 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" bitfld.long 0x04 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" newline hexmask.long.word 0x04 2.--15. 0x04 " TBSA ,TX buffers start address" endif rgroup.long 0xC4++0x03 line.long 0x00 "TXFQS,TX FIFO/Queue Status Register" bitfld.long 0x00 21. " TFQF ,FIFO/Queue full" "Not Full,Full" bitfld.long 0x00 16.--20. " TFQPI ,TX FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TFGI ,TX FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " TFFL ,TX FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" else rgroup.long 0xC8++0x03 line.long 0x00 "TXESC,TX Buffer Element Size Configuration Register" bitfld.long 0x00 0.--2. " TBDS ,TX buffer data field size" "8-Byte,12-Byte,16-Byte,20-Byte,24-Byte,32-Byte,48-Byte,64-Byte" endif rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,TX Buffer Request Pending Register" bitfld.long 0x00 31. " TRP[31] ,Transmission request pending 31" "Not Pending,Pending" bitfld.long 0x00 30. " [30] ,Transmission request pending 30" "Not Pending,Pending" bitfld.long 0x00 29. " [29] ,Transmission request pending 29" "Not Pending,Pending" newline bitfld.long 0x00 28. " [28] ,Transmission request pending 28" "Not Pending,Pending" bitfld.long 0x00 27. " [27] ,Transmission request pending 27" "Not Pending,Pending" bitfld.long 0x00 26. " [26] ,Transmission request pending 26" "Not Pending,Pending" newline bitfld.long 0x00 25. " [25] ,Transmission request pending 25" "Not Pending,Pending" bitfld.long 0x00 24. " [24] ,Transmission request pending 24" "Not Pending,Pending" bitfld.long 0x00 23. " [23] ,Transmission request pending 23" "Not Pending,Pending" newline bitfld.long 0x00 22. " [22] ,Transmission request pending 22" "Not Pending,Pending" bitfld.long 0x00 21. " [21] ,Transmission request pending 21" "Not Pending,Pending" bitfld.long 0x00 20. " [20] ,Transmission request pending 20" "Not Pending,Pending" newline bitfld.long 0x00 19. " [19] ,Transmission request pending 19" "Not Pending,Pending" bitfld.long 0x00 18. " [18] ,Transmission request pending 18" "Not Pending,Pending" bitfld.long 0x00 17. " [17] ,Transmission request pending 17" "Not Pending,Pending" newline bitfld.long 0x00 16. " [16] ,Transmission request pending 16" "Not Pending,Pending" bitfld.long 0x00 15. " [15] ,Transmission request pending 15" "Not Pending,Pending" bitfld.long 0x00 14. " [14] ,Transmission request pending 14" "Not Pending,Pending" newline bitfld.long 0x00 13. " [13] ,Transmission request pending 13" "Not Pending,Pending" bitfld.long 0x00 12. " [12] ,Transmission request pending 12" "Not Pending,Pending" bitfld.long 0x00 11. " [11] ,Transmission request pending 11" "Not Pending,Pending" newline bitfld.long 0x00 10. " [10] ,Transmission request pending 10" "Not Pending,Pending" bitfld.long 0x00 9. " [9] ,Transmission request pending 9" "Not Pending,Pending" bitfld.long 0x00 8. " [8] ,Transmission request pending 8" "Not Pending,Pending" newline bitfld.long 0x00 7. " [7] ,Transmission request pending 7" "Not Pending,Pending" bitfld.long 0x00 6. " [6] ,Transmission request pending 6" "Not Pending,Pending" bitfld.long 0x00 5. " [5] ,Transmission request pending 5" "Not Pending,Pending" newline bitfld.long 0x00 4. " [4] ,Transmission request pending 4" "Not Pending,Pending" bitfld.long 0x00 3. " [3] ,Transmission request pending 3" "Not Pending,Pending" bitfld.long 0x00 2. " [2] ,Transmission request pending 2" "Not Pending,Pending" newline bitfld.long 0x00 1. " [1] ,Transmission request pending 1" "Not Pending,Pending" bitfld.long 0x00 0. " [0] ,Transmission request pending 0" "Not Pending,Pending" group.long 0xD0++0x07 line.long 0x00 "TXBAR,TX Buffer Add Request Register" bitfld.long 0x00 31. " AR[31] ,Add request 31" "Not Added,Added" bitfld.long 0x00 30. " [30] ,Add request 30" "Not Added,Added" bitfld.long 0x00 29. " [29] ,Add request 29" "Not Added,Added" newline bitfld.long 0x00 28. " [28] ,Add request 28" "Not Added,Added" bitfld.long 0x00 27. " [27] ,Add request 27" "Not Added,Added" bitfld.long 0x00 26. " [26] ,Add request 26" "Not Added,Added" newline bitfld.long 0x00 25. " [25] ,Add request 25" "Not Added,Added" bitfld.long 0x00 24. " [24] ,Add request 24" "Not Added,Added" bitfld.long 0x00 23. " [23] ,Add request 23" "Not Added,Added" newline bitfld.long 0x00 22. " [22] ,Add request 22" "Not Added,Added" bitfld.long 0x00 21. " [21] ,Add request 21" "Not Added,Added" bitfld.long 0x00 20. " [20] ,Add request 20" "Not Added,Added" newline bitfld.long 0x00 19. " [19] ,Add request 19" "Not Added,Added" bitfld.long 0x00 18. " [18] ,Add request 18" "Not Added,Added" bitfld.long 0x00 17. " [17] ,Add request 17" "Not Added,Added" newline bitfld.long 0x00 16. " [16] ,Add request 16" "Not Added,Added" bitfld.long 0x00 15. " [15] ,Add request 15" "Not Added,Added" bitfld.long 0x00 14. " [14] ,Add request 14" "Not Added,Added" newline bitfld.long 0x00 13. " [13] ,Add request 13" "Not Added,Added" bitfld.long 0x00 12. " [12] ,Add request 12" "Not Added,Added" bitfld.long 0x00 11. " [11] ,Add request 11" "Not Added,Added" newline bitfld.long 0x00 10. " [10] ,Add request 10" "Not Added,Added" bitfld.long 0x00 9. " [9] ,Add request 9" "Not Added,Added" bitfld.long 0x00 8. " [8] ,Add request 8" "Not Added,Added" newline bitfld.long 0x00 7. " [7] ,Add request 7" "Not Added,Added" bitfld.long 0x00 6. " [6] ,Add request 6" "Not Added,Added" bitfld.long 0x00 5. " [5] ,Add request 5" "Not Added,Added" newline bitfld.long 0x00 4. " [4] ,Add request 4" "Not Added,Added" bitfld.long 0x00 3. " [3] ,Add request 3" "Not Added,Added" bitfld.long 0x00 2. " [2] ,Add request 2" "Not Added,Added" newline bitfld.long 0x00 1. " [1] ,Add request 1" "Not Added,Added" bitfld.long 0x00 0. " [0] ,Add request 0" "Not Added,Added" line.long 0x04 "TXBCR,TX Buffer Cancellation Request Register" bitfld.long 0x04 31. " CR[31] ,Cancellation request 31" "Not Requested,Requested" bitfld.long 0x04 30. " [30] ,Cancellation request 30" "Not Requested,Requested" bitfld.long 0x04 29. " [29] ,Cancellation request 29" "Not Requested,Requested" newline bitfld.long 0x04 28. " [28] ,Cancellation request 28" "Not Requested,Requested" bitfld.long 0x04 27. " [27] ,Cancellation request 27" "Not Requested,Requested" bitfld.long 0x04 26. " [26] ,Cancellation request 26" "Not Requested,Requested" newline bitfld.long 0x04 25. " [25] ,Cancellation request 25" "Not Requested,Requested" bitfld.long 0x04 24. " [24] ,Cancellation request 24" "Not Requested,Requested" bitfld.long 0x04 23. " [23] ,Cancellation request 23" "Not Requested,Requested" newline bitfld.long 0x04 22. " [22] ,Cancellation request 22" "Not Requested,Requested" bitfld.long 0x04 21. " [21] ,Cancellation request 21" "Not Requested,Requested" bitfld.long 0x04 20. " [20] ,Cancellation request 20" "Not Requested,Requested" newline bitfld.long 0x04 19. " [19] ,Cancellation request 19" "Not Requested,Requested" bitfld.long 0x04 18. " [18] ,Cancellation request 18" "Not Requested,Requested" bitfld.long 0x04 17. " [17] ,Cancellation request 17" "Not Requested,Requested" newline bitfld.long 0x04 16. " [16] ,Cancellation request 16" "Not Requested,Requested" bitfld.long 0x04 15. " [15] ,Cancellation request 15" "Not Requested,Requested" bitfld.long 0x04 14. " [14] ,Cancellation request 14" "Not Requested,Requested" newline bitfld.long 0x04 13. " [13] ,Cancellation request 13" "Not Requested,Requested" bitfld.long 0x04 12. " [12] ,Cancellation request 12" "Not Requested,Requested" bitfld.long 0x04 11. " [11] ,Cancellation request 11" "Not Requested,Requested" newline bitfld.long 0x04 10. " [10] ,Cancellation request 10" "Not Requested,Requested" bitfld.long 0x04 9. " [9] ,Cancellation request 9" "Not Requested,Requested" bitfld.long 0x04 8. " [8] ,Cancellation request 8" "Not requested,Requested" newline bitfld.long 0x04 7. " [7] ,Cancellation request 7" "Not Requested,Requested" bitfld.long 0x04 6. " [6] ,Cancellation request 6" "Not Requested,Requested" bitfld.long 0x04 5. " [5] ,Cancellation request 5" "Not Requested,Requested" newline bitfld.long 0x04 4. " [4] ,Cancellation request 4" "Not Requested,Requested" bitfld.long 0x04 3. " [3] ,Cancellation request 3" "Not Requested,Requested" bitfld.long 0x04 2. " [2] ,Cancellation request 2" "Not Requested,Requested" newline bitfld.long 0x04 1. " [1] ,Cancellation request 1" "Not Requested,Requested" bitfld.long 0x04 0. " [0] ,Cancellation request 0" "Not Requested,Requested" rgroup.long 0xD8++0x0F line.long 0x00 "TXBTO,TX Buffer Transmission Occurred Register" bitfld.long 0x00 31. " TO[31] ,Transmission occurred 31" "Not Occurred,Occurred" bitfld.long 0x00 30. " [30] ,Transmission occurred 30" "Not Occurred,Occurred" bitfld.long 0x00 29. " [29] ,Transmission occurred 29" "Not Occurred,Occurred" newline bitfld.long 0x00 28. " [28] ,Transmission occurred 28" "Not Occurred,Occurred" bitfld.long 0x00 27. " [27] ,Transmission occurred 27" "Not Occurred,Occurred" bitfld.long 0x00 26. " [26] ,Transmission occurred 26" "Not Occurred,Occurred" newline bitfld.long 0x00 25. " [25] ,Transmission occurred 25" "Not Occurred,Occurred" bitfld.long 0x00 24. " [24] ,Transmission occurred 24" "Not Occurred,Occurred" bitfld.long 0x00 23. " [23] ,Transmission occurred 23" "Not Occurred,Occurred" newline bitfld.long 0x00 22. " [22] ,Transmission occurred 22" "Not Occurred,Occurred" bitfld.long 0x00 21. " [21] ,Transmission occurred 21" "Not Occurred,Occurred" bitfld.long 0x00 20. " [20] ,Transmission occurred 20" "Not Occurred,Occurred" newline bitfld.long 0x00 19. " [19] ,Transmission occurred 19" "Not Occurred,Occurred" bitfld.long 0x00 18. " [18] ,Transmission occurred 18" "Not Occurred,Occurred" bitfld.long 0x00 17. " [17] ,Transmission occurred 17" "Not Occurred,Occurred" newline bitfld.long 0x00 16. " [16] ,Transmission occurred 16" "Not Occurred,Occurred" bitfld.long 0x00 15. " [15] ,Transmission occurred 15" "Not Occurred,Occurred" bitfld.long 0x00 14. " [14] ,Transmission occurred 14" "Not Occurred,Occurred" newline bitfld.long 0x00 13. " [13] ,Transmission occurred 13" "Not Occurred,Occurred" bitfld.long 0x00 12. " [12] ,Transmission occurred 12" "Not Occurred,Occurred" bitfld.long 0x00 11. " [11] ,Transmission occurred 11" "Not Occurred,Occurred" newline bitfld.long 0x00 10. " [10] ,Transmission occurred 10" "Not Occurred,Occurred" bitfld.long 0x00 9. " [9] ,Transmission occurred 9" "Not Occurred,Occurred" bitfld.long 0x00 8. " [8] ,Transmission occurred 8" "Not Occurred,Occurred" newline bitfld.long 0x00 7. " [7] ,Transmission occurred 7" "Not Occurred,Occurred" bitfld.long 0x00 6. " [6] ,Transmission occurred 6" "Not Occurred,Occurred" bitfld.long 0x00 5. " [5] ,Transmission occurred 5" "Not Occurred,Occurred" newline bitfld.long 0x00 4. " [4] ,Transmission occurred 4" "Not Occurred,Occurred" bitfld.long 0x00 3. " [3] ,Transmission occurred 3" "Not Occurred,Occurred" bitfld.long 0x00 2. " [2] ,Transmission occurred 2" "Not Occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Transmission occurred 1" "Not Occurred,Occurred" bitfld.long 0x00 0. " [0] ,Transmission occurred 0" "Not Occurred,Occurred" line.long 0x04 "TXBCF,TX Buffer Cancellation Finished Register" bitfld.long 0x04 31. " CF[31] ,Cancellation finished 31" "Not Finished,Finished" bitfld.long 0x04 30. " [30] ,Cancellation finished 30" "Not Finished,Finished" bitfld.long 0x04 29. " [29] ,Cancellation finished 29" "Not Finished,Finished" newline bitfld.long 0x04 28. " [28] ,Cancellation finished 28" "Not Finished,Finished" bitfld.long 0x04 27. " [27] ,Cancellation finished 27" "Not Finished,Finished" bitfld.long 0x04 26. " [26] ,Cancellation finished 26" "Not Finished,Finished" newline bitfld.long 0x04 25. " [25] ,Cancellation finished 25" "Not Finished,Finished" bitfld.long 0x04 24. " [24] ,Cancellation finished 24" "Not Finished,Finished" bitfld.long 0x04 23. " [23] ,Cancellation finished 23" "Not Finished,Finished" newline bitfld.long 0x04 22. " [22] ,Cancellation finished 22" "Not Finished,Finished" bitfld.long 0x04 21. " [21] ,Cancellation finished 21" "Not Finished,Finished" bitfld.long 0x04 20. " [20] ,Cancellation finished 20" "Not Finished,Finished" newline bitfld.long 0x04 19. " [19] ,Cancellation finished 19" "Not Finished,Finished" bitfld.long 0x04 18. " [18] ,Cancellation finished 18" "Not Finished,Finished" bitfld.long 0x04 17. " [17] ,Cancellation finished 17" "Not Finished,Finished" newline bitfld.long 0x04 16. " [16] ,Cancellation finished 16" "Not Finished,Finished" bitfld.long 0x04 15. " [15] ,Cancellation finished 15" "Not Finished,Finished" bitfld.long 0x04 14. " [14] ,Cancellation finished 14" "Not Finished,Finished" newline bitfld.long 0x04 13. " [13] ,Cancellation finished 13" "Not Finished,Finished" bitfld.long 0x04 12. " [12] ,Cancellation finished 12" "Not Finished,Finished" bitfld.long 0x04 11. " [11] ,Cancellation finished 11" "Not Finished,Finished" newline bitfld.long 0x04 10. " [10] ,Cancellation finished 10" "Not Finished,Finished" bitfld.long 0x04 9. " [9] ,Cancellation finished 9" "Not Finished,Finished" bitfld.long 0x04 8. " [8] ,Cancellation finished 8" "Not Finished,Finished" newline bitfld.long 0x04 7. " [7] ,Cancellation finished 7" "Not Finished,Finished" bitfld.long 0x04 6. " [6] ,Cancellation finished 6" "Not Finished,Finished" bitfld.long 0x04 5. " [5] ,Cancellation finished 5" "Not Finished,Finished" newline bitfld.long 0x04 4. " [4] ,Cancellation finished 4" "Not Finished,Finished" bitfld.long 0x04 3. " [3] ,Cancellation finished 3" "Not Finished,Finished" bitfld.long 0x04 2. " [2] ,Cancellation finished 2" "Not Finished,Finished" newline bitfld.long 0x04 1. " [1] ,Cancellation finished 1" "Not Finished,Finished" bitfld.long 0x04 0. " [0] ,Cancellation finished 0" "Not Finished,Finished" line.long 0x08 "TXBTIE,TX Buffer Transmission Interrupt Enable Register" bitfld.long 0x08 31. " TIE[31] ,Transmission interrupt enable 31" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled" line.long 0x0C "TXBCIE,TX Buffer Cancellation Finished Interrupt Enable Register" bitfld.long 0x0C 31. " CFIE[31] ,Cancellation finished interrupt enable 31" "Disabled,Enabled" bitfld.long 0x0C 30. " [30] ,Cancellation finished interrupt enable 30" "Disabled,Enabled" bitfld.long 0x0C 29. " [29] ,Cancellation finished interrupt enable 29" "Disabled,Enabled" newline bitfld.long 0x0C 28. " [28] ,Cancellation finished interrupt enable 28" "Disabled,Enabled" bitfld.long 0x0C 27. " [27] ,Cancellation finished interrupt enable 27" "Disabled,Enabled" bitfld.long 0x0C 26. " [26] ,Cancellation finished interrupt enable 26" "Disabled,Enabled" newline bitfld.long 0x0C 25. " [25] ,Cancellation finished interrupt enable 25" "Disabled,Enabled" bitfld.long 0x0C 24. " [24] ,Cancellation finished interrupt enable 24" "Disabled,Enabled" bitfld.long 0x0C 23. " [23] ,Cancellation finished interrupt enable 23" "Disabled,Enabled" newline bitfld.long 0x0C 22. " [22] ,Cancellation finished interrupt enable 22" "Disabled,Enabled" bitfld.long 0x0C 21. " [21] ,Cancellation finished interrupt enable 21" "Disabled,Enabled" bitfld.long 0x0C 20. " [20] ,Cancellation finished interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x0C 19. " [19] ,Cancellation finished interrupt enable 19" "Disabled,Enabled" bitfld.long 0x0C 18. " [18] ,Cancellation finished interrupt enable 18" "Disabled,Enabled" bitfld.long 0x0C 17. " [17] ,Cancellation finished interrupt enable 17" "Disabled,Enabled" newline bitfld.long 0x0C 16. " [16] ,Cancellation finished interrupt enable 16" "Disabled,Enabled" bitfld.long 0x0C 15. " [15] ,Cancellation finished interrupt enable 15" "Disabled,Enabled" bitfld.long 0x0C 14. " [14] ,Cancellation finished interrupt enable 14" "Disabled,Enabled" newline bitfld.long 0x0C 13. " [13] ,Cancellation finished interrupt enable 13" "Disabled,Enabled" bitfld.long 0x0C 12. " [12] ,Cancellation finished interrupt enable 12" "Disabled,Enabled" bitfld.long 0x0C 11. " [11] ,Cancellation finished interrupt enable 11" "Disabled,Enabled" newline bitfld.long 0x0C 10. " [10] ,Cancellation finished interrupt enable 10" "Disabled,Enabled" bitfld.long 0x0C 9. " [9] ,Cancellation finished interrupt enable 9" "Disabled,Enabled" bitfld.long 0x0C 8. " [8] ,Cancellation finished interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x0C 7. " [7] ,Cancellation finished interrupt enable 7" "Disabled,Enabled" bitfld.long 0x0C 6. " [6] ,Cancellation finished interrupt enable 6" "Disabled,Enabled" bitfld.long 0x0C 5. " [5] ,Cancellation finished interrupt enable 5" "Disabled,Enabled" newline bitfld.long 0x0C 4. " [4] ,Cancellation finished interrupt enable 4" "Disabled,Enabled" bitfld.long 0x0C 3. " [3] ,Cancellation finished interrupt enable 3" "Disabled,Enabled" bitfld.long 0x0C 2. " [2] ,Cancellation finished interrupt enable 2" "Disabled,Enabled" newline bitfld.long 0x0C 1. " [1] ,Cancellation finished interrupt enable 1" "Disabled,Enabled" bitfld.long 0x0C 0. " [0] ,Cancellation finished interrupt enable 0" "Disabled,Enabled" if (((per.l(ad:0xB4950000+0x18))&0x03)==0x03) group.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" else rgroup.long 0xF0++0x03 line.long 0x00 "TXEFC,TX Event FIFO Configuration Register" bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32" hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address" endif rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,TX Event FIFO Status Register" bitfld.long 0x00 25. " TEFL ,TX event FIFO element lost" "Not Lost,Lost" bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not Full,Full" bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group.long 0xF8++0x03 line.long 0x00 "TXEFA,TX Event FIFO Acknowledge Register" bitfld.long 0x00 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "MESSAGE RAM ECC FUNCTION" if (((per.l(ad:0xB4950000+0x18))&0x02)==0x02) group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" else group.byte 0x200++0x00 line.byte 0x00 "FDECR,ECC Error Control Register" rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes" rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled" endif rgroup.byte 0x201++0x00 line.byte 0x00 "FDESR,ECC Error Status Register" bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not Detected,Detected" bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not Detected,Detected" group.byte 0x205++0x00 line.byte 0x00 "FDESCR,ECC Status Clear Register" bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No Effect,Clear" bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No Effect,Clear" if (((per.l(ad:0xB4950000+0x201))&0x02)==0x02) rgroup.word 0x206++0x01 line.word 0x00 "FDDEAR,ECC Double-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " DRA ,Double-bit error message RAM address bits" else hgroup.word 0x206++0x01 hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register" endif if (((per.l(ad:0xB4950000+0x201))&0x01)==0x01) rgroup.word 0x202++0x01 line.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" hexmask.word 0x00 0.--15. 0x01 " SRA ,Single-bit error message RAM address bits" else hgroup.word 0x202++0x01 hide.word 0x00 "FDSEAR,ECC Single-bit Error Address Register" endif group.long 0x208++0x03 line.long 0x00 "FDFECR,ECC False Error Control Register" bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled" bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No Error,Error" bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No Error,Error" newline bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No Error,Error" bitfld.long 0x00 15. " EI[15] ,Error specification bit 15" "No Error,Error" bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No Error,Error" newline bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No Error,Error" bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No Error,Error" bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No Error,Error" newline bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No Error,Error" bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No Error,Error" bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No Error,Error" newline bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No Error,Error" bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No Error,Error" bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No Error,Error" newline bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No Error,Error" bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No Error,Error" bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No Error,Error" newline bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No Error,Error" bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No Error,Error" tree.end width 0x0B tree.end tree.end tree.open "TS (External Timestamp Counter For CAN FD)" tree "Channel 0" base ad:0xB4900000 width 9. wgroup.word 0x300++0x01 line.word 0x00 "TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB4900000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB4900000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB4900000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end tree "Channel 1" base ad:0xB4910000 width 9. wgroup.word 0x300++0x01 line.word 0x00 "TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB4910000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB4910000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB4910000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end tree "Channel 2" base ad:0xB4920000 width 9. wgroup.word 0x300++0x01 line.word 0x00 "TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB4920000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB4920000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB4920000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end tree "Channel 3" base ad:0xB4930000 width 9. wgroup.word 0x300++0x01 line.word 0x00 "TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB4930000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB4930000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB4930000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end tree "Channel 4" base ad:0xB4940000 width 9. wgroup.word 0x300++0x01 line.word 0x00 "TSCNTR,Time Stamp Control Register" bitfld.word 0x00 0. " CCLR ,Counter clear bit" "No effect,Clear" group.word 0x302++0x01 line.word 0x00 "TSMDR,Time Stamp Mode Register" bitfld.word 0x00 0. " CNTEN ,Counter enable bit" "Disabled,Enabled" sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU") if (((per.l(ad:0xB4940000+0x302))&0x01)==0x00) group.word 0x304++0x01 line.word 0x00 "TSDIVR,Time Stamp Divider Register" else hgroup.word 0x304++0x01 hide.word 0x00 "TSDIVR,Time Stamp Divider Register" endif else if (((per.l(ad:0xB4940000+0x302))&0x01)==0x00) group.long 0x304++0x03 line.long 0x00 "TSDIVR,Time Stamp Divider Register" hexmask.long.word 0x00 0.--15. 1. " CDIV ,Counter clock division ratio setting bits" else hgroup.long 0x304++0x03 hide.long 0x00 "TSDIVR,Time Stamp Divider Register" endif endif rgroup.word 0x308++0x01 line.word 0x00 "TSCDTR,Time Stamp Counter Data Register" if (((per.l(ad:0xB4940000+0x302))&0x01)==0x00) group.word 0x30A++0x01 line.word 0x00 "TSCPCLR,Time Stamp Compare Clear Register" else hgroup.word 0x30A++0x01 hide.word 0x00 "TSCPCLR,Time Stamp Compare Clear Register" endif width 0x0B tree.end tree.end tree "CANP (CAN Prescaler)" base ad:0xB0688C00 width 5. group.long 0x00++0x03 line.long 0x00 "CTR,CAN Prescaler Control Register" bitfld.long 0x00 8. " CPCKS ,CAN prescaler source clock selection bit" "PLL clock,Main clock" bitfld.long 0x00 0.--5. " CANPRE ,CAN prescaler division setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" rgroup.long 0x04++0x03 line.long 0x00 "STR,CAN Prescaler Status Register" bitfld.long 0x00 1.--2. " SCKM ,Source clock display" "Stopped,PLL clock,Main clock,In the middle" bitfld.long 0x00 0. " BUSY ,Busy" "Idle,Busy" width 0x0B tree.end tree.open "MFS (MULTI-FUNCTION SERIAL INTERFACE)" tree "Channel 0" base ad:0xB4800000 if (((per.b(ad:0xB4800000))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4800000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800000))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4800000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800000+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800000+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4800000+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800000+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4800000+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x40)||(((per.b(ad:0xB4800000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800000+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800000+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4800000+0x01))&0x43)==0x00)||(((per.b(ad:0xB4800000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800000))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800000))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 1" base ad:0xB4800400 if (((per.b(ad:0xB4800400))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4800400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800400))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4800400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800400+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800400+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800400+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4800400+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800400+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4800400+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x40)||(((per.b(ad:0xB4800400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800400+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800400+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4800400+0x01))&0x43)==0x00)||(((per.b(ad:0xB4800400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800400))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800400))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 2" base ad:0xB4800800 if (((per.b(ad:0xB4800800))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4800800+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800800+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800800+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800800+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800800+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800800))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4800800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800800+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800800+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800800+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4800800+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800800+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4800800+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x40)||(((per.b(ad:0xB4800800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800800+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800800+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4800800+0x01))&0x43)==0x00)||(((per.b(ad:0xB4800800+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800800))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800800))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800800+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 3" base ad:0xB4800C00 if (((per.b(ad:0xB4800C00))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4800C00+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4800C00+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800C00))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800C00+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800C00+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800C00+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4800C00+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4800C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800C00+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4800C00+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x40)||(((per.b(ad:0xB4800C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4800C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4800C00+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4800C00+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00)||(((per.b(ad:0xB4800C00+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800C00))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4800C00))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4800C00+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 4" base ad:0xB4801000 if (((per.b(ad:0xB4801000))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4801000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801000))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801000+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801000+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4801000+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801000+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4801000+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)||(((per.b(ad:0xB4801000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801000+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801000+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)||(((per.b(ad:0xB4801000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801000))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801000))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 5" base ad:0xB4801400 if (((per.b(ad:0xB4801400))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4801400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801400))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4801400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801400+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801400+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801400+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4801400+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801400+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4801400+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x40)||(((per.b(ad:0xB4801400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801400+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801400+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4801400+0x01))&0x43)==0x00)||(((per.b(ad:0xB4801400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801400))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801400))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 6" base ad:0xB4801800 if (((per.b(ad:0xB4801800))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4801800+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801800+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801800+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801800+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801800+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801800))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4801800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801800+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801800+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801800+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4801800+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801800+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4801800+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x40)||(((per.b(ad:0xB4801800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801800+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801800+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4801800+0x01))&0x43)==0x00)||(((per.b(ad:0xB4801800+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801800))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801800))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801800+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 7" base ad:0xB4801C00 if (((per.b(ad:0xB4801C00))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4801C00+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4801C00+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801C00))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801C00+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801C00+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801C00+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4801C00+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4801C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801C00+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4801C00+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x40)||(((per.b(ad:0xB4801C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4801C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4801C00+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4801C00+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00)||(((per.b(ad:0xB4801C00+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801C00))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4801C00))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4801C00+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 8" base ad:0xB4880000 if (((per.b(ad:0xB4880000))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4880000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880000))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880000+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880000+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4880000+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880000+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4880000+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)||(((per.b(ad:0xB4880000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880000+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880000+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)||(((per.b(ad:0xB4880000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880000))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880000))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 9" base ad:0xB4880400 if (((per.b(ad:0xB4880400))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4880400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880400))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880400+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880400+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880400+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4880400+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880400+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4880400+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)||(((per.b(ad:0xB4880400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880400+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880400+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)||(((per.b(ad:0xB4880400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880400))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880400))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 10" base ad:0xB4880800 if (((per.b(ad:0xB4880800))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4880800+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880800+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880800+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880800+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880800+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880800))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880800+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880800+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880800+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4880800+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880800+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4880800+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)||(((per.b(ad:0xB4880800+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880800+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880800+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880800+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)||(((per.b(ad:0xB4880800+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880800))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880800))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880800+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 11" base ad:0xB4880C00 if (((per.b(ad:0xB4880C00))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4880C00+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4880C00+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880C00))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880C00+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880C00+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880C00+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4880C00+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4880C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880C00+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4880C00+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)||(((per.b(ad:0xB4880C00+0x02))&0x20)==0x00)||((((per.b(ad:0xB4880C00+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4880C00+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4880C00+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)||(((per.b(ad:0xB4880C00+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880C00))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4880C00))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4880C00+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end tree "Channel 12" base ad:0xB4881000 if (((per.b(ad:0xB4881000))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4881000+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881000+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4881000+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4881000+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4881000+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881000))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4881000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4881000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4881000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4881000+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4881000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4881000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4881000+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881000+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4881000+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4881000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4881000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4881000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4881000+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4881000+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x40)||(((per.b(ad:0xB4881000+0x02))&0x20)==0x00)||((((per.b(ad:0xB4881000+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4881000+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881000+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4881000+0x01))&0x43)==0x00)||(((per.b(ad:0xB4881000+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881000))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881000))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4881000+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end sif cpuis("S6J342*J*") tree "Channel 13" base ad:0xB4881400 if (((per.b(ad:0xB4881400))&0xE0)<0x40) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" newline if (((per.b(ad:0xB4881400+0x02))&0x40)==0x40) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881400+0x00))&0xE0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4881400+0x00))&0xE0)==0x00) if (((per.b(ad:0xB4881400+0x02))&0x10)==0x10) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif elif (((per.b(ad:0xB4881400+0x00))&0xE0)==0x20) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted" newline bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif newline hgroup.word 0x04++0x01 hide.word 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x18++0x00 line.byte 0x00 "TBYTE0,Transfer Byte Register" group.word 0x1C++0x01 line.word 0x00 "BGR,Baud Rate Generator Register" bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" "No effect,Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881400))&0xE0)==0x40) width 16. if (((per.b(ad:0xB4881400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4881400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4881400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4881400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4881400+0x0E))&0x02)==0x02)) group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI" newline bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" else group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4881400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4881400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4881400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4881400+0x0E))&0x02)==0x02)) group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format" bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881400+0x01))&0x03)==0x00)&&(((per.b(ad:0xB4881400+0x03))&0x06)==0x06) group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" else group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear" rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" newline rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" endif if (((per.b(ad:0xB4881400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4881400+0x0E))&0x1E)==0x00)||(((per.b(ad:0xB4881400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4881400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4881400+0x0E))&0x02)==0x02)) if (((per.b(ad:0xB4881400+0x01))&0x03)==0x00) group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" rbitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" newline rbitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif else group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set" bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits" endif newline hgroup.long 0x04++0x03 hide.long 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_SET/CLR ,Transfer byte error enable bit" "Disabled,Enabled" setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_SET/CLR ,Chip select error interrupt enable bit" "Disabled,Enabled" newline rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" newline setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_SET/CLR ,Synchronous transmission enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" if (((per.b(ad:0xB4881400+0x01))&0x43)==(0x01||0x02||0x03)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4881400+0x01))&0x43)==0x00) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active" bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled" newline bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled" bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" elif (((per.b(ad:0xB4881400+0x01))&0x43)==0x40)||(((per.b(ad:0xB4881400+0x02))&0x20)==0x00)||((((per.b(ad:0xB4881400+0x02))&0x20)==0x20)&&(((per.w(ad:0xB4881400+0x0E))&0x02)==0x02)) group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" else group.word 0x0E++0x01 line.word 0x00 "SCSCR,Serial Chip Select Control Status Register" rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3" rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3" bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3" newline rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..." rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High" rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled" newline rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled" endif if (((per.b(ad:0xB4881400+0x01))&0x43)==0x43) group.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" else rgroup.word 0x10++0x03 line.word 0x00 "SCSTR0,Serial Chip Select Timing Register 0" hexmask.word.byte 0x00 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x00 0.--7. 1. " CSHD ,Serial chip select hold delay bits" line.word 0x02 "SCSTR1,Serial Chip Select Timing Register 1" hexmask.word.byte 0x02 8.--15. 1. " CSSU ,Serial chip select setup delay bits" hexmask.word.byte 0x02 0.--7. 1. " CSHD ,Serial chip select hold delay bits" endif if (((per.b(ad:0xB4881400+0x01))&0x43)==0x00)||(((per.b(ad:0xB4881400+0x02))&0x20)==0x20) group.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." else rgroup.byte 0x14++0x02 line.byte 0x00 "SCSFR0,Serial Chip Select Format Register 0" bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High" bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low" bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI" newline bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB" bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x01 "SCSFR1,Serial Chip Select Format Register 1" bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High" bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low" bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI" newline bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB" bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." line.byte 0x02 "SCSFR2,Serial Chip Select Format Register 2" bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High" bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low" bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI" newline bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB" bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..." endif if (((per.b(ad:0xB4881400+0x01))&0x40)==0x00) group.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" else rgroup.byte 0x18++0x03 line.byte 0x00 "TBYTE0,Transfer Byte Register 0" line.byte 0x01 "TBYTE1,Transfer Byte Register 1" line.byte 0x02 "TBYTE2,Transfer Byte Register 2" line.byte 0x03 "TBYTE3,Transfer Byte Register 3" endif group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881400))&0xE0)==0x60) width 16. group.byte 0x01++0x00 line.byte 0x00 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " MS_SET/CLR ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 1. 0x44 1. 0x2C 1. " RXE_SET/CLR ,Reception operation enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " TXE_SET/CLR ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " SBL_SET/CLR ,Stop bit length selection bit" "1-bits,2-bits" newline setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " SOE_SET/CLR ,Serial data output enable bit" "Disabled,Enabled" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected" rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" group.byte 0x02++0x00 line.byte 0x00 "ESCR,Extended Communication Control Register" setclrfld.byte 0x00 6. 0x44 6. 0x2C 6. " ESBL_SET/CLR ,Extended stop bit length" "1-2bit,3-4bit" setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " LBIE_SET/CLR ,LIN break field detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits" newline bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_SET/CLR ,Serial test bit" "Disabled,Enabled" rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled" rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected" newline setclrfld.word 0x00 12. 0x40 12. 0x28 12. " SFDE_SET/CLR ,Sync field detection interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 11. 0x40 11. 0x28 11. " AUTE_SET/CLR ,Auto baud rate adjustment bit" "Disabled,Enabled" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." newline rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt" setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" newline bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits division ratio" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_SET/CLR ,Serial time enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x05 line.word 0x00 "STMCR,Serial Timer Comparison Register" line.word 0x02 "SFUR,Sync Field Upper Limit Register" hexmask.word 0x02 0.--14. 1. " TU ,Upper limit bits" line.word 0x04 "SFLR,Sync Field Lower Limit Register" hexmask.word 0x04 0.--14. 1. " TL ,Lower limit bits" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" bitfld.byte 0x01 7. " EXT ,External clock selection bit" "Internal,External" hexmask.byte 0x01 0.--6. 1. " BGR ,Baud rate generator" group.byte 0x12++0x00 line.byte 0x00 "LAMCR,LIN Assist Mode Control Register" bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..." bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear" setclrfld.byte 0x00 2. 0x3C 2. 0x24 2. " LCSTYP_SET/CLR ,LIN checksum type selection bit" "Standard,Extended" newline setclrfld.byte 0x00 1. 0x3C 1. 0x24 1. " LIDEN_SET/CLR ,LIN ID register use enable bit" "RDR/TDR,LAMRID/LAMTID" setclrfld.byte 0x00 0. 0x3C 0. 0x24 0. " LAMEN_SET/CLR ,LIN assist mode processing enable bit" "Manual,Assist" rgroup.byte 0x13++0x00 line.byte 0x00 "LAMSR,LIN Assist Mode Status Register" bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error" bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error" bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full" newline bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission" bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected" newline bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected" wgroup.byte 0x18++0x00 line.byte 0x00 "LAMTID,LIN Assist Mode Transmission ID Register" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.byte 0x18++0x00 line.byte 0x00 "LAMRID,LIN Assist Mode Reception ID Register" bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3" bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19++0x00 line.byte 0x00 "LAMIER_SET/CLR,LIN Assist Mode Interrupt Enable Register" setclrfld.byte 0x00 6. 0x38 6. 0x20 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x38 5. 0x20 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x38 4. 0x20 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 3. 0x38 3. 0x20 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x38 2. 0x20 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x38 0. 0x20 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x1B++0x00 line.byte 0x00 "LAMESR,LIN Assist Mode Error Status Register" bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error" bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error" newline bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error" group.byte 0x1A++0x00 line.byte 0x00 "LAMERT,LIN Assist Mode Error Test Register" bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3" bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error" newline bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error" bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit" "FIFO1/2,FIFO2/1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO1 operation enable bit" "Disabled,Enabled" group.word 0x22++0x03 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit" line.word 0x02 "FTICR,Transmission FIFO interrupt Control Register" hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit" hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2F++0x00 line.byte 0x00 "SSRC,Serial Status Clear Register" bitfld.byte 0x00 5. " LBDC ,Clearing the LIN break field detection flag bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 13. " SFDC ,Clearing the sync field detection flag" ",Clear" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x37++0x00 line.byte 0x00 "LAMSRC,LIN Assist Mode Status Clear Register" bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear" bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear" wgroup.byte 0x3B++0x00 line.byte 0x00 "LAMESRC,LIN Assist Mode Error Status Clear Register" bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear" bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear" bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear" newline bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "SCRS,Serial Control Set Register" bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set" bitfld.byte 0x00 5. " LBRS ,Setting the LIN break field setting bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" wgroup.byte 0x4E++0x00 line.byte 0x00 "LAMCRS,LIN Assist Mode Control Set Register" bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B elif (((per.b(ad:0xB4881400))&0xE0)==0x80) width 16. group.byte 0x01++0x00 line.byte 0x00 "IBCR,I2C Bus Control Register" setclrfld.byte 0x00 7. 0x44 7. 0x2C 7. " MSS_SET/CLR ,Master/Slave selection bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation Flag/Repeated start condition generation bit" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " ACKE_SET/CLR ,Data byte acknowledgment enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WSEL_SET/CLR ,Wait selection bit" "9th bit,8th bit" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " CNDE_SET/CLR ,Condition detection interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " INTE_SET/CLR ,Interrupt enable bit" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" setclrfld.byte 0x00 0. 0x44 0. 0x2C 0. " INT_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt" group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " WUCR_SET/CLR ,Wake up control bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x44 3. 0x2C 3. " RIE_SET/CLR ,Reception interrupt enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 2. 0x44 2. 0x2C 2. " TIE_SET/CLR ,Transmission interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x02++0x00 line.byte 0x00 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not 1st byte,Processed" bitfld.byte 0x00 6. " RACK ,Acknowledgment flag bit" "Low,High" bitfld.byte 0x00 5. " RSA ,Reserved address detection bit" "Not detected,Detected" newline bitfld.byte 0x00 4. " TRX ,Data direction bit" "Reception,Transmission" bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "No arbitration,Arbitration" bitfld.byte 0x00 2. " RSC ,Repeated start condition check bit" "Not detected,Detected" newline bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus status bit" "Idle,Transmission and reception state" group.byte 0x03++0x00 line.byte 0x00 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmission buffer empty flag set bit" "No effect,Set" setclrfld.byte 0x00 5. 0x44 5. 0x2C 5. " DMA_SET/CLR ,DMA mode enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 4. 0x44 4. 0x2C 4. " TBIE_SET/CLR ,Transmission bus idle interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" newline rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Not empty" rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty" newline rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "Not transmission,Transmission" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "RDR/TDR,Reception/Transmission Data Register" in newline group.word 0x08++0x01 line.word 0x00 "SACSR,Serial Auxiliary Control Status Register" bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..." rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "Not occurred,Occurred" setclrfld.word 0x00 7. 0x40 7. 0x22 7. " TINTE_SET/CLR ,Timer interrupt enable bit" "Disabled,Enabled" newline setclrfld.word 0x00 5. 0x40 5. 0x22 5. " TRGE_SET/CLR ,External trigger enable bit" "Disabled,Enabled" bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." setclrfld.word 0x00 0. 0x40 0. 0x22 0. " TMRE_SET/CLR ,Serial timer enable bit" "Disabled,Enabled" rgroup.word 0x0A++0x01 line.word 0x00 "STMR,Serial Timer Register" group.word 0x0C++0x01 line.word 0x00 "STMCR,Serial Timer Comparison Register" group.byte 0x10++0x00 line.byte 0x00 "NFCR,Noise Filter Control Register" bitfld.byte 0x00 0.--4. " NFT ,Noise filter time selection bits" "8MHz to < 40MHz,40MHZ to < 60MHz,60MHz to < 80MHz,80MHz to < 100MHz,100MHz to < 120MHz,120MHz to < 140MHz,140MHz to < 160MHz,160MHz to < 180MHz,180MHz to < 200MHz,200MHz to < 220MHz,220MHz to < 240MHz,240MHz to < 260MHz,260MHz to < 280MHz,280MHz to < 300MHz,300MHz to < 320MHz,320MHz to < 340MHz,340MHz to < 360MHz,360MHz to < 380MHz,380MHz to < 400MHz,?..." if (((per.l(ad:0xB4881400+0x1F))&0x80)==0x80) group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" rbitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" rbitfld.byte 0x00 4. " SCLS ,SCL status bit" "Low,High" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" newline bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" else group.byte 0x11++0x00 line.byte 0x00 "EIBCR,Extended I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Stop,Continue" endif group.byte 0x1F++0x00 line.byte 0x00 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM[6] ,Slave address mask bit 6" "0,1" bitfld.byte 0x00 5. " [5] ,Slave address mask bit 5" "0,1" newline bitfld.byte 0x00 4. " [4] ,Slave address mask bit 4" "0,1" bitfld.byte 0x00 3. " [3] ,Slave address mask bit 3" "0,1" bitfld.byte 0x00 2. " [2] ,Slave address mask bit 2" "0,1" newline bitfld.byte 0x00 1. " [1] ,Slave address mask bit 1" "0,1" bitfld.byte 0x00 0. " [0] ,Slave address mask bit 0" "0,1" group.byte 0x1E++0x00 line.byte 0x00 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA ,7-bit slave address" group.byte 0x1C++0x01 line.byte 0x00 "BGR0,Baud Rate Generator Register 0" line.byte 0x01 "BGR1,Baud Rate Generator Register 1" group.byte 0x21++0x00 line.byte 0x00 "FCR1,FIFO Control Register 1" setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_SET/CLR ,Retransmission data lost detection enable bit" "Disabled,Enabled" setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_SET/CLR ,Reception FIFO idle detection enable bit" "Disabled,Enabled" rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission" newline setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_SET/CLR ,Transmission FIFO interrupt enable bit" "Disabled,Enabled" setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_SET/CLR ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1" group.byte 0x20++0x00 line.byte 0x00 "FCR0,FIFO Control Register 0" rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "No data lost,Data lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved" newline bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" newline setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_SET/CLR ,FIFO2 operation enable bit" "Disabled,Enabled" group.word 0x22++0x01 line.word 0x00 "FBYTE,FIFO Byte Register" hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits" hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits" group.word 0x24++0x01 line.word 0x00 "FTICR,Transmission FIFO Interrupt Control Register" hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,Transmission FIFO interrupt control register" hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,Transmission FIFO interrupt control register" group.byte 0x26++0x00 line.byte 0x00 "ECR,Extended Control Register" bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error" bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand mode,Block mode" bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand mode,Block mode" rgroup.byte 0x27++0x00 line.byte 0x00 "ESR,Extended Status Register" bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred" bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred" newline bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred" group.byte 0x28++0x00 line.byte 0x00 "TBSIZE,Transmission Block Size Register" wgroup.byte 0x2E++0x00 line.byte 0x00 "IBSRC,I2C Bus Status Clear Register" bitfld.byte 0x00 2. " RSCC ,Clearing the repeated start condition check bit" ",Clear" bitfld.byte 0x00 1. " SPCC ,Clearing the stop condition check bit" ",Clear" wgroup.word 0x30++0x01 line.word 0x00 "SACSRC,Serial Auxiliary Control Status Clear Register" bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear" wgroup.byte 0x3D++0x00 line.byte 0x00 "FCR1C,FIFO Control Clear Register 1" bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear" wgroup.byte 0x43++0x00 line.byte 0x00 "ESRC,Extended Status Clear Register" bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 2. " TXOVRC ,Reception FIFO under run flag clear bit" ",Clear" bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear" newline bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear" wgroup.byte 0x45++0x00 line.byte 0x00 "IBCRS,Bus Control Set Register" bitfld.byte 0x00 6. " ACTS ,Setting the repeated start condition generation bit" ",Set" wgroup.byte 0x47++0x00 line.byte 0x00 "SSRS,Serial Status Set Register" bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set" bitfld.byte 0x00 6. " TSETS ,Setting the transmission buffer empty flag set bit" ",Set" wgroup.byte 0x54++0x00 line.byte 0x00 "FCR0S,FIFO Control Set Register 0" bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set" bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set" bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set" newline bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set" width 0x0B else width 16. newline newline newline group.byte 0x00++0x00 line.byte 0x00 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..." newline endif width 0x0B tree.end endif tree.end tree.open "BT (Base Timer)" tree "Channel 0" base ad:0xB4808000 width 14. if (((per.w(ad:0xB4808000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4808000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4808000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4808000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4808000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL0 1 ,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL0 1 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB4808000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 1" base ad:0xB4808400 width 14. if (((per.w(ad:0xB4808400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4808400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4808400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4808400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4808400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 2" base ad:0xB4808800 width 14. if (((per.w(ad:0xB4808800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4808800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4808800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4808800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4808800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2 3 ,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2 3 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 3" base ad:0xB4808C00 width 14. if (((per.w(ad:0xB4808C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4808C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4808C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4808C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 4" base ad:0xB4809000 width 14. if (((per.w(ad:0xB4809000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4809000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4809000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4809000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4809000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4 5 ,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4 5 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 5" base ad:0xB4809400 width 14. if (((per.w(ad:0xB4809400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4809400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4809400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4809400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4809400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 6" base ad:0xB4809800 width 14. if (((per.w(ad:0xB4809800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4809800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4809800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4809800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4809800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL6 7 ,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL6 7 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 7" base ad:0xB4809C00 width 14. if (((per.w(ad:0xB4809C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4809C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4809C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4809C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 8" base ad:0xB480A000 width 14. if (((per.w(ad:0xB480A000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB480A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480A000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB480A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480A000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB480A000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480A000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480A000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480A000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480A000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB480A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL8 9 ,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL8 9 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 9" base ad:0xB480A400 width 14. if (((per.w(ad:0xB480A400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB480A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480A400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB480A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480A400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB480A400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480A400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480A400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480A400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480A400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB480A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 10" base ad:0xB480A800 width 14. if (((per.w(ad:0xB480A800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB480A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480A800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB480A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480A800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB480A800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480A800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480A800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480A800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480A800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB480A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL1011,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1011 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 11" base ad:0xB480AC00 width 14. if (((per.w(ad:0xB480AC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480AC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480AC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB480AC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480AC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480AC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB480AC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB480AC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 12" base ad:0xB4888000 width 14. if (((per.w(ad:0xB4888000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4888000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4888000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL1213,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1213 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB4888000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 13" base ad:0xB4888400 width 14. if (((per.w(ad:0xB4888400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4888400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4888400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4888400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4888400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 14" base ad:0xB4888800 width 14. if (((per.w(ad:0xB4888800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4888800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4888800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4888800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4888800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL1415,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1415 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 15" base ad:0xB4888C00 width 14. if (((per.w(ad:0xB4888C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4888C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4888C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4888C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4888C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4888C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4888C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 16" base ad:0xB4889000 width 14. if (((per.w(ad:0xB4889000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4889000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4889000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4889000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4889000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL1617,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1617 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 17" base ad:0xB4889400 width 14. if (((per.w(ad:0xB4889400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4889400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4889400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4889400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4889400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 18" base ad:0xB4889800 width 14. if (((per.w(ad:0xB4889800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4889800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4889800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4889800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4889800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL1819,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL1819 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 19" base ad:0xB4889C00 width 14. if (((per.w(ad:0xB4889C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4889C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4889C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4889C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4889C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4889C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4889C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 20" base ad:0xB488A000 width 14. if (((per.w(ad:0xB488A000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB488A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488A000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB488A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488A000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB488A000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488A000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488A000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488A000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488A000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB488A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2021,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2021 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 21" base ad:0xB488A400 width 14. if (((per.w(ad:0xB488A400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB488A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488A400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB488A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488A400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB488A400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488A400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488A400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488A400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488A400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB488A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 22" base ad:0xB488A800 width 14. if (((per.w(ad:0xB488A800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB488A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488A800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB488A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488A800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB488A800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488A800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488A800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488A800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488A800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB488A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2223,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2223 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 23" base ad:0xB488AC00 width 14. if (((per.w(ad:0xB488AC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB488AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488AC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB488AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488AC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB488AC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488AC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488AC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB488AC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB488AC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB488AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end sif cpuis("S6J342?F*") tree "Channel 24" base ad:0xB4846000 width 14. if (((per.w(ad:0xB4846000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2425,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2425 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB4846000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 25" base ad:0xB4846400 width 14. if (((per.w(ad:0xB4846400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 26" base ad:0xB4846800 width 14. if (((per.w(ad:0xB4846800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2627,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2627 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 27" base ad:0xB4846C00 width 14. if (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 28" base ad:0xB4847000 width 14. if (((per.w(ad:0xB4847000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2829,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2829 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 29" base ad:0xB4847400 width 14. if (((per.w(ad:0xB4847400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 30" base ad:0xB4847800 width 14. if (((per.w(ad:0xB4847800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3031,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3031 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 31" base ad:0xB4847C00 width 14. if (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 32" base ad:0xB4848000 width 14. if (((per.w(ad:0xB4848000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3233,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3233 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 33" base ad:0xB4848400 width 14. if (((per.w(ad:0xB4848400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 34" base ad:0xB4848800 width 14. if (((per.w(ad:0xB4848800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3435,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3435 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 35" base ad:0xB4848C00 width 14. if (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 36" base ad:0xB4849000 width 14. if (((per.w(ad:0xB4849000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3637,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3637 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB4849000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 37" base ad:0xB4849400 width 14. if (((per.w(ad:0xB4849400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 38" base ad:0xB4849800 width 14. if (((per.w(ad:0xB4849800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3839,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3839 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 39" base ad:0xB4849C00 width 14. if (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 40" base ad:0xB484A000 width 14. if (((per.w(ad:0xB484A000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484A000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4041,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4041 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 41" base ad:0xB484A400 width 14. if (((per.w(ad:0xB484A400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484A400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 42" base ad:0xB484A800 width 14. if (((per.w(ad:0xB484A800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484A800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4243,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4243 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 43" base ad:0xB484AC00 width 14. if (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484AC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484AC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484AC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484AC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 44" base ad:0xB484B000 width 14. if (((per.w(ad:0xB484B000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484B000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4445,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4445 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 45" base ad:0xB484B400 width 14. if (((per.w(ad:0xB484B400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484B400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 46" base ad:0xB484B800 width 14. if (((per.w(ad:0xB484B800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484B800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4647,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4647 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 47" base ad:0xB484BC00 width 14. if (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484BC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484BC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484BC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484BC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end elif cpuis("S6J342?H*") tree "Channel 24" base ad:0xB4846000 width 14. if (((per.w(ad:0xB4846000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2425,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2425 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB4846000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 25" base ad:0xB4846400 width 14. if (((per.w(ad:0xB4846400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 26" base ad:0xB4846800 width 14. if (((per.w(ad:0xB4846800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2627,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2627 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 27" base ad:0xB4846C00 width 14. if (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 28" base ad:0xB4847000 width 14. if (((per.w(ad:0xB4847000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2829,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2829 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 29" base ad:0xB4847400 width 14. if (((per.w(ad:0xB4847400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 30" base ad:0xB4847800 width 14. if (((per.w(ad:0xB4847800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3031,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3031 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 31" base ad:0xB4847C00 width 14. if (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 32" base ad:0xB4848000 width 14. if (((per.w(ad:0xB4848000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3233,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3233 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 33" base ad:0xB4848400 width 14. if (((per.w(ad:0xB4848400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 34" base ad:0xB4848800 width 14. if (((per.w(ad:0xB4848800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3435,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3435 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 35" base ad:0xB4848C00 width 14. if (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 36" base ad:0xB4849000 width 14. if (((per.w(ad:0xB4849000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3637,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3637 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB4849000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 37" base ad:0xB4849400 width 14. if (((per.w(ad:0xB4849400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 38" base ad:0xB4849800 width 14. if (((per.w(ad:0xB4849800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3839,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3839 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 39" base ad:0xB4849C00 width 14. if (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 40" base ad:0xB484A000 width 14. if (((per.w(ad:0xB484A000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484A000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4041,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4041 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 41" base ad:0xB484A400 width 14. if (((per.w(ad:0xB484A400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484A400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 42" base ad:0xB484A800 width 14. if (((per.w(ad:0xB484A800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484A800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4243,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4243 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 43" base ad:0xB484AC00 width 14. if (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484AC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484AC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484AC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484AC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 44" base ad:0xB484B000 width 14. if (((per.w(ad:0xB484B000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484B000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4445,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4445 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 45" base ad:0xB484B400 width 14. if (((per.w(ad:0xB484B400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484B400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 46" base ad:0xB484B800 width 14. if (((per.w(ad:0xB484B800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484B800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4647,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4647 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 47" base ad:0xB484BC00 width 14. if (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484BC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484BC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484BC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484BC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 48" base ad:0xB484C000 width 14. if (((per.w(ad:0xB484C000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484C000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4849,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4849 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB484C000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 49" base ad:0xB484C400 width 14. if (((per.w(ad:0xB484C400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484C400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484C400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484C400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484C400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 50" base ad:0xB484C800 width 14. if (((per.w(ad:0xB484C800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484C800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484C800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484C800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484C800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL5051,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL5051 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 51" base ad:0xB484CC00 width 14. if (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484CC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484CC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484CC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484CC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 52" base ad:0xB484D000 width 14. if (((per.w(ad:0xB484D000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484D000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484D000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484D000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484D000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL5253,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL5253 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 53" base ad:0xB484D400 width 14. if (((per.w(ad:0xB484D400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484D400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484D400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484D400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484D400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 54" base ad:0xB484D800 width 14. if (((per.w(ad:0xB484D800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484D800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484D800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484D800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484D800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL5455,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL5455 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 55" base ad:0xB484DC00 width 14. if (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484DC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484DC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484DC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484DC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 56" base ad:0xB484E000 width 14. if (((per.w(ad:0xB484E000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484E000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484E000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484E000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484E000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL5657,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL5657 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 57" base ad:0xB484E400 width 14. if (((per.w(ad:0xB484E400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484E400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484E400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484E400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484E400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 58" base ad:0xB484E800 width 14. if (((per.w(ad:0xB484E800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484E800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484E800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484E800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484E800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL5859,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL5859 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 59" base ad:0xB484EC00 width 14. if (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484EC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484EC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484EC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484EC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end else tree "Channel 24" base ad:0xB4846000 width 14. if (((per.w(ad:0xB4846000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2425,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2425 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB4846000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 25" base ad:0xB4846400 width 14. if (((per.w(ad:0xB4846400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 26" base ad:0xB4846800 width 14. if (((per.w(ad:0xB4846800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2627,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2627 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 27" base ad:0xB4846C00 width 14. if (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4846C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4846C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4846C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 28" base ad:0xB4847000 width 14. if (((per.w(ad:0xB4847000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL2829,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL2829 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 29" base ad:0xB4847400 width 14. if (((per.w(ad:0xB4847400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 30" base ad:0xB4847800 width 14. if (((per.w(ad:0xB4847800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3031,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3031 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 31" base ad:0xB4847C00 width 14. if (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4847C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4847C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4847C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 32" base ad:0xB4848000 width 14. if (((per.w(ad:0xB4848000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3233,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3233 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 33" base ad:0xB4848400 width 14. if (((per.w(ad:0xB4848400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 34" base ad:0xB4848800 width 14. if (((per.w(ad:0xB4848800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3435,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3435 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 35" base ad:0xB4848C00 width 14. if (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4848C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4848C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4848C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4848C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 36" base ad:0xB4849000 width 14. if (((per.w(ad:0xB4849000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3637,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3637 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB4849000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 37" base ad:0xB4849400 width 14. if (((per.w(ad:0xB4849400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 38" base ad:0xB4849800 width 14. if (((per.w(ad:0xB4849800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL3839,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL3839 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 39" base ad:0xB4849C00 width 14. if (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB4849C00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849C00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849C00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB4849C00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB4849C00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB4849C00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 40" base ad:0xB484A000 width 14. if (((per.w(ad:0xB484A000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484A000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484A000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4041,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4041 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 41" base ad:0xB484A400 width 14. if (((per.w(ad:0xB484A400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484A400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484A400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 42" base ad:0xB484A800 width 14. if (((per.w(ad:0xB484A800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484A800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484A800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484A800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484A800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4243,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4243 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 43" base ad:0xB484AC00 width 14. if (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484AC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484AC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484AC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484AC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484AC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484AC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 44" base ad:0xB484B000 width 14. if (((per.w(ad:0xB484B000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484B000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484B000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4445,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4445 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 45" base ad:0xB484B400 width 14. if (((per.w(ad:0xB484B400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484B400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484B400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 46" base ad:0xB484B800 width 14. if (((per.w(ad:0xB484B800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484B800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484B800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484B800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484B800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4647,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4647 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 47" base ad:0xB484BC00 width 14. if (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484BC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484BC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484BC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484BC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484BC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484BC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 48" base ad:0xB484C000 width 14. if (((per.w(ad:0xB484C000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484C000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484C000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL4849,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL4849 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB484C000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 49" base ad:0xB484C400 width 14. if (((per.w(ad:0xB484C400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484C400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484C400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484C400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484C400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 50" base ad:0xB484C800 width 14. if (((per.w(ad:0xB484C800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484C800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484C800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484C800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484C800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484C800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484C800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL5051,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL5051 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 51" base ad:0xB484CC00 width 14. if (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484CC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484CC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484CC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484CC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484CC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484CC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 52" base ad:0xB484D000 width 14. if (((per.w(ad:0xB484D000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484D000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484D000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484D000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484D000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL5253,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL5253 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 53" base ad:0xB484D400 width 14. if (((per.w(ad:0xB484D400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484D400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484D400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484D400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484D400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 54" base ad:0xB484D800 width 14. if (((per.w(ad:0xB484D800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484D800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484D800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484D800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484D800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484D800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484D800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL5455,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL5455 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 55" base ad:0xB484DC00 width 14. if (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484DC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484DC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484DC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484DC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484DC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484DC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 56" base ad:0xB484E000 width 14. if (((per.w(ad:0xB484E000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484E000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484E000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484E000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484E000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL5657,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL5657 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 57" base ad:0xB484E400 width 14. if (((per.w(ad:0xB484E400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484E400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484E400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484E400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484E400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 58" base ad:0xB484E800 width 14. if (((per.w(ad:0xB484E800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484E800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484E800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484E800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484E800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484E800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484E800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL5859,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL5859 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." width 0x0B tree.end tree "Channel 59" base ad:0xB484EC00 width 14. if (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484EC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484EC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484EC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484EC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484EC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484EC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 60" base ad:0xB484F000 width 14. if (((per.w(ad:0xB484F000+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484F000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484F000+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484F000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484F000+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484F000+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484F000+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484F000+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484F000+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484F000+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484F000+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline group.long 0x30++0x03 line.long 0x00 "BT_BTSEL6061,I/O Selection Register" bitfld.long 0x00 0.--3. " BTSEL6061 ,I/O mode selection bits" "16-Bit Timer Standard,32-Bit Timer Full-Function,Ppg Trigger 2-Channel Sharing,,Timer Start/Stop,Simultaneous Soft Start,Start/Stop And Simultaneous Soft Start,Timer Start,?..." if (((per.l(ad:0xB484F000+0x30))&0x0F)==(0x05||0x06)) group.long 0x34++0x03 line.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" bitfld.long 0x00 11. " SSSR[11] ,Simultaneous soft start bit 11" "No effect,Started" bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started" bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started" bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started" newline bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started" bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started" bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started" bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started" newline bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started" bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started" bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started" bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started" else hgroup.long 0x34++0x03 hide.long 0x00 "BT_BTSSSR,Simultaneous Soft Start Register" endif rgroup.long 0x38++0x03 line.long 0x00 "BT_BTTRR,TOUT Read Register" bitfld.long 0x00 11. " TRR[11] ,Simultaneous TOUT read bit 11" "0,1" bitfld.long 0x00 10. " [10] ,Simultaneous TOUT read bit 10" "0,1" bitfld.long 0x00 9. " [9] ,Simultaneous TOUT read bit 9" "0,1" bitfld.long 0x00 8. " [8] ,Simultaneous TOUT read bit 8" "0,1" newline bitfld.long 0x00 7. " [7] ,Simultaneous TOUT read bit 7" "0,1" bitfld.long 0x00 6. " [6] ,Simultaneous TOUT read bit 6" "0,1" bitfld.long 0x00 5. " [5] ,Simultaneous TOUT read bit 5" "0,1" bitfld.long 0x00 4. " [4] ,Simultaneous TOUT read bit 4" "0,1" newline bitfld.long 0x00 3. " [3] ,Simultaneous TOUT read bit 3" "0,1" bitfld.long 0x00 2. " [2] ,Simultaneous TOUT read bit 2" "0,1" bitfld.long 0x00 1. " [1] ,Simultaneous TOUT read bit 1" "0,1" bitfld.long 0x00 0. " [0] ,Simultaneous TOUT read bit 0" "0,1" width 0x0B tree.end tree "Channel 61" base ad:0xB484F400 width 14. if (((per.w(ad:0xB484F400+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484F400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484F400+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484F400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484F400+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484F400+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484F400+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484F400+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484F400+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484F400+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484F400+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 62" base ad:0xB484F800 width 14. if (((per.w(ad:0xB484F800+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484F800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484F800+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484F800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484F800+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484F800+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484F800+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484F800+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484F800+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484F800+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484F800+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end tree "Channel 63" base ad:0xB484FC00 width 14. if (((per.w(ad:0xB484FC00+0x0C))&0x70)==0x10) if (((per.b(ad:0xB484FC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" sif cpuis("S6J35*") bitfld.byte 0x00 1. " ETCEN ,External timer compare enable bit" "Disabled,Enabled" newline endif bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_SET/CLR ,Duty match interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x1C++0x01 line.word 0x00 "PSDR,Start Delay Value Setting Register" group.word 0x20++0x01 line.word 0x00 "ADTR,ADC Trigger Value Setting Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484FC00+0x0C))&0x70)==0x20) if (((per.b(ad:0xB484FC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" ",Clear" else group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PRLL,L Width Setting Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,H Width Setting Reload Register" sif cpuis("S6J35*") group.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" else rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484FC00+0x0C))&0x70)==0x30) if (((per.b(ad:0xB484FC00+0x11))&0x81)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484FC00+0x11))&0x81)==0x01) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" ",Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484FC00+0x11))&0x81)==0x80) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" elif (((per.b(ad:0xB484FC00+0x11))&0x81)==0x81) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register 1" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Low,High,Low,High" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot" newline bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_SET/CLR ,Trigger interrupt request enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_SET/CLR ,Underflow interrupt request enable" "Disabled,Enabled" rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "Not requested,Requested" rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "Not requested,Requested" sif cpuis("S6J35*") group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" else wgroup.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" ",Clear" bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" ",Clear" endif group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Setting Register" sif cpuis("S6J35*") group.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" else rgroup.long 0x08++0x03 line.long 0x00 "TMR,Timer Register" hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits" endif group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ETCDR,External Timer Compare Data Register" elif (((per.w(ad:0xB484FC00+0x0C))&0x70)==0x40) if (((per.b(ad:0xB484FC00+0x11))&0x01)==0x00) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" bitfld.word 0x00 12.--14. " CKS[0:2] ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset Mode,16-Bit PWM,16-Bit PPG,16/32-Bit Reload,16/32-Bit PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-Shot" bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled" endif group.byte 0x11++0x00 line.byte 0x00 "TMCR2,Timer Control Register 2" bitfld.byte 0x00 0. " CKS3 ,Count clock selection" "0,1" group.byte 0x10++0x00 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag" "No Error,Error" setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_SET/CLR ,Measurement end interrupt enable" "Disabled,Enabled" setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_SET/CLR ,Overflow interrupt request enable" "Disabled,Enabled" newline rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request" "Not requested,Requested" group.byte 0x14++0x00 line.byte 0x00 "STCC,Status Control Clear Register" bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear" ",Clear" rgroup.word 0x04++0x01 line.word 0x00 "DTBF,Data Buffer Register" group.word 0x24++0x01 line.word 0x00 "DEBUG,Base Timer Debug Register" bitfld.word 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Register" newline bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-Bit PWM,16-Bit PPG,16/32-bit reload,16/32-Bit PWC,?..." endif newline width 0x0B tree.end endif tree.end tree "BTSO (Base Timer Simultaneous Operation)" base ad:0xB488B000 width 8. group.long 0x00++0x0B line.long 0x00 "CPCLR,Compare Clear Register" hexmask.long.word 0x00 0.--15. 1. " CL ,Compare clear value bits" line.long 0x04 "TCDT,Timer Data Register" hexmask.long.word 0x04 0.--15. 1. " T ,Global timer data value bits" line.long 0x08 "TCCS,Timer State Control Register" bitfld.long 0x08 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth" rbitfld.long 0x08 9. " ICLR ,Compare clear interrupt flag bit" "No interrupt,Interrupt" setclrfld.long 0x08 8. 0x0C 8. 0x08 8. " ICRE_SET/CLR ,Compare clear interrupt request enable bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x0C 6. 0x08 6. " STOP_SET/CLR ,Timer enable bit" "No,Yes" newline bitfld.long 0x08 0.--3. " CLK ,Clock frequency selection bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,?..." group.long 0x10++0x3 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 9. " ICLRC ,CLR clear bit" "No effect,Clear" group.long 0x18++0x03 line.long 0x00 "DEBUG,Timer State Control Clear Register" bitfld.long 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "MSCTR,Global Timer Match Starting Control Register" bitfld.long 0x00 2. " TREN ,Transfer request enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " MODE ,Mode select bit" "Disabled,Enabled" bitfld.long 0x00 0. " GTMOE ,Global timer match output enable bit" "Disabled,Enabled" hgroup.long 0x24++0x03 hide.long 0x00 "MSCHB0,Global Timer Match Starting Channel 0 Buffer Register" in hgroup.long 0x28++0x03 hide.long 0x00 "MSCHB1,Global Timer Match Starting Channel 1 Buffer Register" in sif cpuis("S6J342*") rgroup.long 0x2C++0x07 line.long 0x00 "MSCH0,Global Timer Match Starting Channel 0 Register" line.long 0x04 "MSCH1,Global Timer Match Starting Channel 1 Register" else group.long 0x2C++0x07 line.long 0x00 "MSCH0,Global Timer Match Starting Channel 0 Register" line.long 0x04 "MSCH1,Global Timer Match Starting Channel 1 Register" endif width 0x0B tree.end tree.open "FRT (32-Bit Free-Run Timer)" tree "FRT ch.0" base ad:0xB4820000 width 8. if (((per.l(ad:0xB4820000+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820000+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820000+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820000+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820000+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT ch.1" base ad:0xB4820400 width 8. if (((per.l(ad:0xB4820400+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820400+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820400+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820400+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820400+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT ch.2" base ad:0xB4820800 width 8. if (((per.l(ad:0xB4820800+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820800+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820800+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820800+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820800+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT ch.3" base ad:0xB4820C00 width 8. if (((per.l(ad:0xB4820C00+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820C00+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820C00+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820C00+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820C00+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT ch.4" base ad:0xB4821000 width 8. if (((per.l(ad:0xB4821000+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4821000+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4821000+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4821000+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4821000+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT ch.8" base ad:0xB4820000 width 8. if (((per.l(ad:0xB4820000+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820000+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820000+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820000+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820000+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT ch.9" base ad:0xB4820400 width 8. if (((per.l(ad:0xB4820400+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820400+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820400+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820400+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820400+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "FRT ch.10" base ad:0xB4820800 width 8. if (((per.l(ad:0xB4820800+0x08))&0x80)==0x80) wgroup.long 0x00++0x03 line.long 0x00 "CPCLRB,Compare Clear Buffer Register" else hgroup.long 0x00++0x03 hide.long 0x00 "CPCLRB,Compare Clear Buffer Register" endif rgroup.long 0x00++0x03 line.long 0x00 "CPCLR,Compare Clear Register" if (((per.l(ad:0xB4820800+0x08))&0x40)==0x40) group.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" else rgroup.long 0x04++0x03 line.long 0x00 "TCDT,Timer Data Register" endif group.long 0x08++0x03 line.long 0x00 "TCCS,Timer State Control Register" bitfld.long 0x00 15. " ECKE ,Clock selection bit" "Peripheral,External" rbitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 13. " IRQZE ,0 detection request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" rbitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected" bitfld.long 0x00 8. " ICRE ,Compare clear interrupt request enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. " BFE ,Compare clear buffer enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " STOP ,Timer disable bit" "No,Yes" bitfld.long 0x00 5. " MODE ,Timer count mode bit" "Up count,Up/Down count" newline bitfld.long 0x00 4. " SCLR ,Timer clear bit" "No effect,Clear" bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..." if (((per.l(ad:0xB4820800+0x08))&0x20)==0x20)&&(((per.l(ad:0xB4820800+0x0C))&0x800)==0x800) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "1st,2nd,3rd,4th,5th,6th,7th,8th" elif (((per.l(ad:0xB4820800+0x08))&0x20)==0x00) group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,?..." else group.long 0x0C++0x03 line.long 0x00 "TECCS,Timer Extended State Control Register" bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid" endif group.long 0x10++0x07 line.long 0x00 "TCCSC,Timer State Control Clear Register" bitfld.long 0x00 15. " ECKEC ,Clock selection clear bit" "No effect,Clear" bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear" "No effect,Clear" bitfld.long 0x00 13. " IRQZEC ,0 detection request enable clear bit" "No effect,Clear" newline bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear" "No effect,Clear" bitfld.long 0x00 8. " ICREC ,Compare clear interrupt request enable bit" "No effect,Clear" newline bitfld.long 0x00 7. " BFEC ,Compare clear buffer enable clear bit" "No effect,Clear" bitfld.long 0x00 6. " STOPC ,Timer enable clear bit" "No effect,Clear" bitfld.long 0x00 5. " MODEC ,Timer count mode clear bit" "No effect,Clear" line.long 0x04 "TCCSS,Timer State Control Set Register" bitfld.long 0x04 15. " ECKES ,Clock selection set bit" "No effect,Set" bitfld.long 0x04 13. " IRQZES ,0 detection request enable set bit" "No effect,Set" newline bitfld.long 0x04 8. " ICRES ,Compare clear interrupt request enable set bit" "No effect,Set" newline bitfld.long 0x04 7. " BFES ,Compare clear buffer enable set bit" "No effect,Set" bitfld.long 0x04 6. " STOPS ,Timer enable set bit" "No effect,Set" bitfld.long 0x04 5. " MODES ,Timer count mode set bit" "No effect,Set" newline bitfld.long 0x04 4. " SCLRS ,Timer clear set bit" "No effect,Set" group.word 0x18++0x01 line.word 0x00 "DEBUG,Timer State Control Clear Register" sif cpuis("S6J342*") bitfld.word 0x00 0. " DBGEN ,Debug enable bit" "Disabled,Enabled" else bitfld.word 0x00 9. " DBGEN ,Debug enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree.end tree.open "IC (32-Bit Input Capture)" tree "ICU 0/1" base ad:0xB4828000 width 7. rgroup.long 0x00++0x03 line.long 0x00 "IPCP0,Input Capture Data Register 0" sif cpuis("S6J342*")||cpuis("S6J35*") rgroup.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" else group.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU 2/3" base ad:0xB4828400 width 7. rgroup.long 0x00++0x03 line.long 0x00 "IPCP0,Input Capture Data Register 0" sif cpuis("S6J342*")||cpuis("S6J35*") rgroup.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" else group.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU 4/5" base ad:0xB4828800 width 7. rgroup.long 0x00++0x03 line.long 0x00 "IPCP0,Input Capture Data Register 0" sif cpuis("S6J342*")||cpuis("S6J35*") rgroup.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" else group.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU 16/17" base ad:0xB48A8000 width 7. rgroup.long 0x00++0x03 line.long 0x00 "IPCP0,Input Capture Data Register 0" sif cpuis("S6J342*")||cpuis("S6J35*") rgroup.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" else group.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU 18/19" base ad:0xB48A8400 width 7. rgroup.long 0x00++0x03 line.long 0x00 "IPCP0,Input Capture Data Register 0" sif cpuis("S6J342*")||cpuis("S6J35*") rgroup.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" else group.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree "ICU 20/21" base ad:0xB48A8800 width 7. rgroup.long 0x00++0x03 line.long 0x00 "IPCP0,Input Capture Data Register 0" sif cpuis("S6J342*")||cpuis("S6J35*") rgroup.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" else group.long 0x04++0x03 line.long 0x00 "IPCP1,Input Capture Data Register 1" endif group.long 0x08++0x03 line.long 0x00 "ICS,Input Capture State Control Register" rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising" rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising" rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected" newline rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both" wgroup.long 0x0C++0x03 line.long 0x00 "ICSC,Input Capture State Control Clear Register" bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear" width 0x0B tree.end tree.end tree.open "OCT (32-Bit Output Compare Timer)" tree "OCU 0/1" base ad:0xB4830000 width 8. wgroup.long 0x00++0x07 line.long 0x00 "OCCPB0,Output Compare Buffer Register 0" line.long 0x04 "OCCPB1,Output Compare Buffer Register 1" rgroup.long 0x00++0x07 line.long 0x00 "OCCP0,Output Compare Register 0" line.long 0x04 "OCCP1,Output Compare Register 1" group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" endif newline sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" sif cpuis("S6J342*") group.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" endif width 0x0B tree.end tree "OCU 2/3" base ad:0xB4830400 width 8. wgroup.long 0x00++0x07 line.long 0x00 "OCCPB0,Output Compare Buffer Register 0" line.long 0x04 "OCCPB1,Output Compare Buffer Register 1" rgroup.long 0x00++0x07 line.long 0x00 "OCCP0,Output Compare Register 0" line.long 0x04 "OCCP1,Output Compare Register 1" group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" endif newline sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" sif cpuis("S6J342*") group.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" endif width 0x0B tree.end tree "OCU 4/5" base ad:0xB4830800 width 8. wgroup.long 0x00++0x07 line.long 0x00 "OCCPB0,Output Compare Buffer Register 0" line.long 0x04 "OCCPB1,Output Compare Buffer Register 1" rgroup.long 0x00++0x07 line.long 0x00 "OCCP0,Output Compare Register 0" line.long 0x04 "OCCP1,Output Compare Register 1" group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" endif newline sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" sif cpuis("S6J342*") group.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" endif width 0x0B tree.end tree "OCU 16/17" base ad:0xB48B0000 width 8. wgroup.long 0x00++0x07 line.long 0x00 "OCCPB0,Output Compare Buffer Register 0" line.long 0x04 "OCCPB1,Output Compare Buffer Register 1" rgroup.long 0x00++0x07 line.long 0x00 "OCCP0,Output Compare Register 0" line.long 0x04 "OCCP1,Output Compare Register 1" group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" endif newline sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" sif cpuis("S6J342*") group.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" endif width 0x0B tree.end tree "OCU 18/19" base ad:0xB48B0400 width 8. wgroup.long 0x00++0x07 line.long 0x00 "OCCPB0,Output Compare Buffer Register 0" line.long 0x04 "OCCPB1,Output Compare Buffer Register 1" rgroup.long 0x00++0x07 line.long 0x00 "OCCP0,Output Compare Register 0" line.long 0x04 "OCCP1,Output Compare Register 1" group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" endif newline sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" sif cpuis("S6J342*") group.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" endif width 0x0B tree.end tree "OCU 20/21" base ad:0xB48B0800 width 8. wgroup.long 0x00++0x07 line.long 0x00 "OCCPB0,Output Compare Buffer Register 0" line.long 0x04 "OCCPB1,Output Compare Buffer Register 1" rgroup.long 0x00++0x07 line.long 0x00 "OCCP0,Output Compare Register 0" line.long 0x04 "OCCP1,Output Compare Register 1" group.long 0x08++0x03 line.long 0x00 "OCS,Compare Control Register" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1" newline setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1" sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected" endif newline sif cpuis("S6J342*")||cpuis("S6J35*") rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" else bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected" endif setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" newline setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled" sif cpuis("S6J342*") group.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" else wgroup.long 0x0C++0x03 line.long 0x00 "OCSC,Compare Control Clear Register" bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear" bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear" endif width 0x0B tree.end tree.end tree.open "RLDT (32-Bit Reload Timer)" tree "Channel 0" base ad:0xB4810000 width 8. group.long 0x00++0x03 line.long 0x00 "DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" if (((per.l(ad:0xB4810000+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start low,Start high" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810000+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "TMRLR,32-bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "TMR,32-bit Timer Register" width 0x0B tree.end tree "Channel 1" base ad:0xB4810400 width 8. group.long 0x00++0x03 line.long 0x00 "DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" if (((per.l(ad:0xB4810400+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start low,Start high" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810400+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "TMRLR,32-bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "TMR,32-bit Timer Register" width 0x0B tree.end tree "Channel 2" base ad:0xB4810800 width 8. group.long 0x00++0x03 line.long 0x00 "DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" if (((per.l(ad:0xB4810800+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start low,Start high" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810800+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "TMRLR,32-bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "TMR,32-bit Timer Register" width 0x0B tree.end tree "Channel 3" base ad:0xB4810C00 width 8. group.long 0x00++0x03 line.long 0x00 "DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" if (((per.l(ad:0xB4810C00+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start low,Start high" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4810C00+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "TMRLR,32-bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "TMR,32-bit Timer Register" width 0x0B tree.end tree "Channel 16" base ad:0xB4890000 width 8. group.long 0x00++0x03 line.long 0x00 "DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" if (((per.l(ad:0xB4890000+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start low,Start high" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890000+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "TMRLR,32-bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "TMR,32-bit Timer Register" width 0x0B tree.end tree "Channel 17" base ad:0xB4890400 width 8. group.long 0x00++0x03 line.long 0x00 "DMACFG,DMA Configuration Register" bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled" if (((per.l(ad:0xB4890400+0x08))&0x1001810)==0x1001810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start low,Start high" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x1001810)==0x1001800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x1000010)==0x1000010) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x1000010)==0x1000000) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger" bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x1810)==0x1810) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x1810)==0x1800) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" elif (((per.l(ad:0xB4890400+0x08))&0x10)==0x10) group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "TMCSR,Timer Control Status Register" bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled" textfld " " bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear" newline rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes" bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High" bitfld.long 0x00 10.--12. " CSL ,Clock select" "1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN" newline bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled" bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled" bitfld.long 0x00 5. " OUTL ,Output level" "High,Low" newline bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload" bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled" endif group.long 0x10++0x03 line.long 0x00 "TMRLR,32-bit Reload Register" rgroup.long 0x14++0x03 line.long 0x00 "TMR,32-bit Timer Register" width 0x0B tree.end tree.end tree.open "RTSSS (Reload Timer Simultaneous Soft Start)" tree "Channel 0/1/2/3" base ad:0xB483FC00 width 6. group.long 0x00++0x07 line.long 0x00 "TSEL,Reload Timer Trigger Selection Register" bitfld.long 0x00 15. " TSEL_[15] ,Trigger selection bit 15" "External,Software" bitfld.long 0x00 14. " [14] ,Trigger selection bit 14" "External,Software" bitfld.long 0x00 13. " [13] ,Trigger selection bit 13" "External,Software" bitfld.long 0x00 12. " [12] ,Trigger selection bit 12" "External,Software" newline bitfld.long 0x00 11. " [11] ,Trigger selection bit 11" "External,Software" bitfld.long 0x00 10. " [10] ,Trigger selection bit 10" "External,Software" bitfld.long 0x00 9. " [9] ,Trigger selection bit 9" "External,Software" bitfld.long 0x00 8. " [8] ,Trigger selection bit 8" "External,Software" newline bitfld.long 0x00 7. " [7] ,Trigger selection bit 7" "External,Software" bitfld.long 0x00 6. " [6] ,Trigger selection bit 6" "External,Software" bitfld.long 0x00 5. " [5] ,Trigger selection bit 5" "External,Software" bitfld.long 0x00 4. " [4] ,Trigger selection bit 4" "External,Software" newline bitfld.long 0x00 3. " [3] ,Trigger selection bit 3" "External,Software" bitfld.long 0x00 2. " [2] ,Trigger selection bit 2" "External,Software" bitfld.long 0x00 1. " [1] ,Trigger selection bit 1" "External,Software" bitfld.long 0x00 0. " [0] ,Trigger selection bit 0" "External,Software" line.long 0x04 "SSSR,Reload Timer Simultaneous Soft Start Register" bitfld.long 0x04 15. " SSSR_[15] ,Simultaneous soft start bit 15" "Not active,Active" bitfld.long 0x04 14. " [14] ,Simultaneous soft start bit 14" "Not active,Active" bitfld.long 0x04 13. " [13] ,Simultaneous soft start bit 13" "Not active,Active" bitfld.long 0x04 12. " [12] ,Simultaneous soft start bit 12" "Not active,Active" newline bitfld.long 0x04 11. " [11] ,Simultaneous soft start bit 11" "Not active,Active" bitfld.long 0x04 10. " [10] ,Simultaneous soft start bit 10" "Not active,Active" bitfld.long 0x04 9. " [9] ,Simultaneous soft start bit 9" "Not active,Active" bitfld.long 0x04 8. " [8] ,Simultaneous soft start bit 8" "Not active,Active" newline bitfld.long 0x04 7. " [7] ,Simultaneous soft start bit 7" "Not active,Active" bitfld.long 0x04 6. " [6] ,Simultaneous soft start bit 6" "Not active,Active" bitfld.long 0x04 5. " [5] ,Simultaneous soft start bit 5" "Not active,Active" bitfld.long 0x04 4. " [4] ,Simultaneous soft start bit 4" "Not active,Active" newline bitfld.long 0x04 3. " [3] ,Simultaneous soft start bit 3" "Not active,Active" bitfld.long 0x04 2. " [2] ,Simultaneous soft start bit 2" "Not active,Active" bitfld.long 0x04 1. " [1] ,Simultaneous soft start bit 1" "Not active,Active" bitfld.long 0x04 0. " [0] ,Simultaneous soft start bit 0" "Not active,Active" width 0x0B tree.end tree "Channel 16/17" base ad:0xB48BFC00 width 6. group.long 0x00++0x07 line.long 0x00 "TSEL,Reload Timer Trigger Selection Register" bitfld.long 0x00 15. " TSEL_[15] ,Trigger selection bit 15" "External,Software" bitfld.long 0x00 14. " [14] ,Trigger selection bit 14" "External,Software" bitfld.long 0x00 13. " [13] ,Trigger selection bit 13" "External,Software" bitfld.long 0x00 12. " [12] ,Trigger selection bit 12" "External,Software" newline bitfld.long 0x00 11. " [11] ,Trigger selection bit 11" "External,Software" bitfld.long 0x00 10. " [10] ,Trigger selection bit 10" "External,Software" bitfld.long 0x00 9. " [9] ,Trigger selection bit 9" "External,Software" bitfld.long 0x00 8. " [8] ,Trigger selection bit 8" "External,Software" newline bitfld.long 0x00 7. " [7] ,Trigger selection bit 7" "External,Software" bitfld.long 0x00 6. " [6] ,Trigger selection bit 6" "External,Software" bitfld.long 0x00 5. " [5] ,Trigger selection bit 5" "External,Software" bitfld.long 0x00 4. " [4] ,Trigger selection bit 4" "External,Software" newline bitfld.long 0x00 3. " [3] ,Trigger selection bit 3" "External,Software" bitfld.long 0x00 2. " [2] ,Trigger selection bit 2" "External,Software" bitfld.long 0x00 1. " [1] ,Trigger selection bit 1" "External,Software" bitfld.long 0x00 0. " [0] ,Trigger selection bit 0" "External,Software" line.long 0x04 "SSSR,Reload Timer Simultaneous Soft Start Register" bitfld.long 0x04 15. " SSSR_[15] ,Simultaneous soft start bit 15" "Not active,Active" bitfld.long 0x04 14. " [14] ,Simultaneous soft start bit 14" "Not active,Active" bitfld.long 0x04 13. " [13] ,Simultaneous soft start bit 13" "Not active,Active" bitfld.long 0x04 12. " [12] ,Simultaneous soft start bit 12" "Not active,Active" newline bitfld.long 0x04 11. " [11] ,Simultaneous soft start bit 11" "Not active,Active" bitfld.long 0x04 10. " [10] ,Simultaneous soft start bit 10" "Not active,Active" bitfld.long 0x04 9. " [9] ,Simultaneous soft start bit 9" "Not active,Active" bitfld.long 0x04 8. " [8] ,Simultaneous soft start bit 8" "Not active,Active" newline bitfld.long 0x04 7. " [7] ,Simultaneous soft start bit 7" "Not active,Active" bitfld.long 0x04 6. " [6] ,Simultaneous soft start bit 6" "Not active,Active" bitfld.long 0x04 5. " [5] ,Simultaneous soft start bit 5" "Not active,Active" bitfld.long 0x04 4. " [4] ,Simultaneous soft start bit 4" "Not active,Active" newline bitfld.long 0x04 3. " [3] ,Simultaneous soft start bit 3" "Not active,Active" bitfld.long 0x04 2. " [2] ,Simultaneous soft start bit 2" "Not active,Active" bitfld.long 0x04 1. " [1] ,Simultaneous soft start bit 1" "Not active,Active" bitfld.long 0x04 0. " [0] ,Simultaneous soft start bit 0" "Not active,Active" width 0x0B tree.end tree.end tree.open "QPRC (Quadrature Position/Revolution Counter)" tree "Channel 8" base ad:0xB4898000 width 7. group.word 0x00++0x07 line.word 0x00 "QPCR,QPRC Position Count Register" line.word 0x02 "QRCR,QPRC Revolution Count Register" line.word 0x04 "QPCCR,QPRC Position Counter Compare Register" line.word 0x06 "QPRCR,QPRC Position And Revolution Counter Compare Register" if ((per.w(ad:0xB4898000+0x0C)&0x20)==0x20)&&((per.w(ad:0xB4898000+0x0C)&0x0C)==(0x00||0x0C)) group.word 0x0C++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" elif ((per.w(ad:0xB4898000+0x0C)&0x20)==0x20)&&((per.w(ad:0xB4898000+0x0C)&0x0C)==(0x04||0x08)) group.word 0x0C++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" elif ((per.w(ad:0xB4898000+0x0C)&0x20)==0x00)&&((per.w(ad:0xB4898000+0x0C)&0x0C)==(0x00||0x0C)) group.word 0x0C++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" else group.word 0x0C++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" endif group.word 0x0E++0x01 line.word 0x00 "QECR,QPRC Extension Control Register" bitfld.word 0x00 2. " ORNGIE ,Outrange interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " ORNGF ,Outrange interrupt request flag bit (read/write)" "Not detected/Cleared,Detected/No effect" bitfld.word 0x00 0. " ORNGMD ,Outrange mode selection bit" "Positive number,8K value" group.byte 0x0A++0x01 line.byte 0x00 "QICRL,Low-Order Bytes of QPRC Interrupt Control Register" bitfld.byte 0x00 7. " ZIIF ,Zero index interrupt request flag bit (read/write)" "Not detected/Cleared,Detected/No effect" bitfld.byte 0x00 6. " OFDF ,Overflow interrupt request flag bit (read/write)" "Not detected/Cleared,Detected/No effect" bitfld.byte 0x00 5. " UFDF ,Underflow interrupt request flag bit (read/write)" "Not detected/Cleared,Detected/No effect" newline bitfld.byte 0x00 4. " OUZIE ,Overflow/Underflow/Zero index interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " QPRCMF ,PC and RC match interrupt request flag bit (read/write)" "Not matched/Cleared,Matched/No effect" bitfld.byte 0x00 2. " QPRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " QPCMF ,PC match interrupt request flag bit (read/write)" "Not compared/Cleared,Compared/No effect" bitfld.byte 0x00 0. " QPCMIE ,PC match interrupt enable bit" "Disabled,Enabled" line.byte 0x01 "QICRH,High-Order Bytes of QPRC Interrupt Control Register" bitfld.byte 0x01 5. " QPCNRCMF ,PC and RC match interrupt request flag bit (read/write)" "Not matched/Cleared,Matched/No effect" bitfld.byte 0x01 4. " QPCNRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x01 3. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented" newline rbitfld.byte 0x01 2. " DIRPC ,Last position counter direction bit" "Incremented,Decremented" bitfld.byte 0x01 1. " CDCF ,Count inversion interrupt request flag bit (read/write)" "Not inverted/Cleared,Inverted/No effect" bitfld.byte 0x01 0. " CDCIE ,Count inversion interrupt enable bit" "Disabled,Enabled" group.word 0x08++0x01 line.word 0x00 "QMPR,QPRC Maximum Position Register" width 0x0B tree.end tree "Channel 9" base ad:0xB4898400 width 7. group.word 0x00++0x07 line.word 0x00 "QPCR,QPRC Position Count Register" line.word 0x02 "QRCR,QPRC Revolution Count Register" line.word 0x04 "QPCCR,QPRC Position Counter Compare Register" line.word 0x06 "QPRCR,QPRC Position And Revolution Counter Compare Register" if ((per.w(ad:0xB4898400+0x0C)&0x20)==0x20)&&((per.w(ad:0xB4898400+0x0C)&0x0C)==(0x00||0x0C)) group.word 0x0C++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" elif ((per.w(ad:0xB4898400+0x0C)&0x20)==0x20)&&((per.w(ad:0xB4898400+0x0C)&0x0C)==(0x04||0x08)) group.word 0x0C++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" elif ((per.w(ad:0xB4898400+0x0C)&0x20)==0x00)&&((per.w(ad:0xB4898400+0x0C)&0x0C)==(0x00||0x0C)) group.word 0x0C++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "Disabled,2-times,4-times,8-times" bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" else group.word 0x0C++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both" newline bitfld.word 0x00 7. " SWAP ,Swap bit" "No swap,Swap" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" newline bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Not stopped,Stopped" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" newline bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "PC_Mode0,PC_Mode1,PC_Mode2,PC_Mode3" endif group.word 0x0E++0x01 line.word 0x00 "QECR,QPRC Extension Control Register" bitfld.word 0x00 2. " ORNGIE ,Outrange interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " ORNGF ,Outrange interrupt request flag bit (read/write)" "Not detected/Cleared,Detected/No effect" bitfld.word 0x00 0. " ORNGMD ,Outrange mode selection bit" "Positive number,8K value" group.byte 0x0A++0x01 line.byte 0x00 "QICRL,Low-Order Bytes of QPRC Interrupt Control Register" bitfld.byte 0x00 7. " ZIIF ,Zero index interrupt request flag bit (read/write)" "Not detected/Cleared,Detected/No effect" bitfld.byte 0x00 6. " OFDF ,Overflow interrupt request flag bit (read/write)" "Not detected/Cleared,Detected/No effect" bitfld.byte 0x00 5. " UFDF ,Underflow interrupt request flag bit (read/write)" "Not detected/Cleared,Detected/No effect" newline bitfld.byte 0x00 4. " OUZIE ,Overflow/Underflow/Zero index interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " QPRCMF ,PC and RC match interrupt request flag bit (read/write)" "Not matched/Cleared,Matched/No effect" bitfld.byte 0x00 2. " QPRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" newline bitfld.byte 0x00 1. " QPCMF ,PC match interrupt request flag bit (read/write)" "Not compared/Cleared,Compared/No effect" bitfld.byte 0x00 0. " QPCMIE ,PC match interrupt enable bit" "Disabled,Enabled" line.byte 0x01 "QICRH,High-Order Bytes of QPRC Interrupt Control Register" bitfld.byte 0x01 5. " QPCNRCMF ,PC and RC match interrupt request flag bit (read/write)" "Not matched/Cleared,Matched/No effect" bitfld.byte 0x01 4. " QPCNRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x01 3. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented" newline rbitfld.byte 0x01 2. " DIRPC ,Last position counter direction bit" "Incremented,Decremented" bitfld.byte 0x01 1. " CDCF ,Count inversion interrupt request flag bit (read/write)" "Not inverted/Cleared,Inverted/No effect" bitfld.byte 0x01 0. " CDCIE ,Count inversion interrupt enable bit" "Disabled,Enabled" group.word 0x08++0x01 line.word 0x00 "QMPR,QPRC Maximum Position Register" width 0x0B tree.end tree.end tree "EICU (External Interrupt Capture Unit)" base ad:0xB0688000 width 7. group.long 0x00++0x27 line.long 0x00 "CNFGR,Configuration Register" bitfld.long 0x00 26. " IRQEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " OBSEN ,Observation enable" "Disabled,Enabled" bitfld.long 0x00 24. " DATARESET ,Data reset" "No effect,Reset" rbitfld.long 0x00 23. " DATAVALID ,Data valid" "Not valid,Valid" newline rbitfld.long 0x00 22. " BUSY ,Sampling status" "Not ongoing,Ongoing" rbitfld.long 0x00 16.--20. " OBSCH ,Observed channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--7. " PRESCALE ,Prescale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. " CLKSEL ,Clock select" "Slow RC,Fast RC,Main,Sub" line.long 0x04 "IRENR,External Interrupt Pin Enable Register" bitfld.long 0x04 31. " IREN_[31] ,External interrupt pin observe enable 31" "Disabled,Enabled" bitfld.long 0x04 30. " [30] ,External interrupt pin observe enable 30" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,External interrupt pin observe enable 29" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,External interrupt pin observe enable 28" "Disabled,Enabled" newline bitfld.long 0x04 27. " [27] ,External interrupt pin observe enable 27" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,External interrupt pin observe enable 26" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,External interrupt pin observe enable 25" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,External interrupt pin observe enable 24" "Disabled,Enabled" newline bitfld.long 0x04 23. " [23] ,External interrupt pin observe enable 23" "Disabled,Enabled" bitfld.long 0x04 22. " [22] ,External interrupt pin observe enable 22" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,External interrupt pin observe enable 21" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,External interrupt pin observe enable 20" "Disabled,Enabled" newline bitfld.long 0x04 19. " [19] ,External interrupt pin observe enable 19" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,External interrupt pin observe enable 18" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,External interrupt pin observe enable 17" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,External interrupt pin observe enable 16" "Disabled,Enabled" newline bitfld.long 0x04 15. " [15] ,External interrupt pin observe enable 15" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,External interrupt pin observe enable 14" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,External interrupt pin observe enable 13" "Disabled,Enabled" bitfld.long 0x04 12. " [12] ,External interrupt pin observe enable 12" "Disabled,Enabled" newline bitfld.long 0x04 11. " [11] ,External interrupt pin observe enable 11" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,External interrupt pin observe enable 10" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,External interrupt pin observe enable 9" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,External interrupt pin observe enable 8" "Disabled,Enabled" newline bitfld.long 0x04 7. " [7] ,External interrupt pin observe enable 7" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,External interrupt pin observe enable 6" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,External interrupt pin observe enable 5" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,External interrupt pin observe enable 4" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,External interrupt pin observe enable 3" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,External interrupt pin observe enable 2" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,External interrupt pin observe enable 1" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,External interrupt pin observe enable 0" "Disabled,Enabled" line.long 0x08 "SPLR0,Sample Register" bitfld.long 0x08 31. " SPL_[31] ,Sample bit 31" "Not occurred,Occurred" bitfld.long 0x08 30. " [30] ,Sample bit 30" "Not occurred,Occurred" bitfld.long 0x08 29. " [29] ,Sample bit 29" "Not occurred,Occurred" bitfld.long 0x08 28. " [28] ,Sample bit 28" "Not occurred,Occurred" newline bitfld.long 0x08 27. " [27] ,Sample bit 27" "Not occurred,Occurred" bitfld.long 0x08 26. " [26] ,Sample bit 26" "Not occurred,Occurred" bitfld.long 0x08 25. " [25] ,Sample bit 25" "Not occurred,Occurred" bitfld.long 0x08 24. " [24] ,Sample bit 24" "Not occurred,Occurred" newline bitfld.long 0x08 23. " [23] ,Sample bit 23" "Not occurred,Occurred" bitfld.long 0x08 22. " [22] ,Sample bit 22" "Not occurred,Occurred" bitfld.long 0x08 21. " [21] ,Sample bit 21" "Not occurred,Occurred" bitfld.long 0x08 20. " [20] ,Sample bit 20" "Not occurred,Occurred" newline bitfld.long 0x08 19. " [19] ,Sample bit 19" "Not occurred,Occurred" bitfld.long 0x08 18. " [18] ,Sample bit 18" "Not occurred,Occurred" bitfld.long 0x08 17. " [17] ,Sample bit 17" "Not occurred,Occurred" bitfld.long 0x08 16. " [16] ,Sample bit 16" "Not occurred,Occurred" newline bitfld.long 0x08 15. " [15] ,Sample bit 15" "Not occurred,Occurred" bitfld.long 0x08 14. " [14] ,Sample bit 14" "Not occurred,Occurred" bitfld.long 0x08 13. " [13] ,Sample bit 13" "Not occurred,Occurred" bitfld.long 0x08 12. " [12] ,Sample bit 12" "Not occurred,Occurred" newline bitfld.long 0x08 11. " [11] ,Sample bit 11" "Not occurred,Occurred" bitfld.long 0x08 10. " [10] ,Sample bit 10" "Not occurred,Occurred" bitfld.long 0x08 9. " [9] ,Sample bit 9" "Not occurred,Occurred" bitfld.long 0x08 8. " [8] ,Sample bit 8" "Not occurred,Occurred" newline bitfld.long 0x08 7. " [7] ,Sample bit 7" "Not occurred,Occurred" bitfld.long 0x08 6. " [6] ,Sample bit 6" "Not occurred,Occurred" bitfld.long 0x08 5. " [5] ,Sample bit 5" "Not occurred,Occurred" bitfld.long 0x08 4. " [4] ,Sample bit 4" "Not occurred,Occurred" newline bitfld.long 0x08 3. " [3] ,Sample bit 3" "Not occurred,Occurred" bitfld.long 0x08 2. " [2] ,Sample bit 2" "Not occurred,Occurred" bitfld.long 0x08 1. " [1] ,Sample bit 1" "Not occurred,Occurred" bitfld.long 0x08 0. " [0] ,Sample bit 0" "Not occurred,Occurred" line.long 0x0C "SPLR1,Sample Register" bitfld.long 0x0C 31. " SPL_[63] ,Sample bit 63" "Not occurred,Occurred" bitfld.long 0x0C 30. " [62] ,Sample bit 62" "Not occurred,Occurred" bitfld.long 0x0C 29. " [61] ,Sample bit 61" "Not occurred,Occurred" bitfld.long 0x0C 28. " [60] ,Sample bit 60" "Not occurred,Occurred" newline bitfld.long 0x0C 27. " [59] ,Sample bit 59" "Not occurred,Occurred" bitfld.long 0x0C 26. " [58] ,Sample bit 58" "Not occurred,Occurred" bitfld.long 0x0C 25. " [57] ,Sample bit 57" "Not occurred,Occurred" bitfld.long 0x0C 24. " [56] ,Sample bit 56" "Not occurred,Occurred" newline bitfld.long 0x0C 23. " [55] ,Sample bit 55" "Not occurred,Occurred" bitfld.long 0x0C 22. " [54] ,Sample bit 54" "Not occurred,Occurred" bitfld.long 0x0C 21. " [53] ,Sample bit 53" "Not occurred,Occurred" bitfld.long 0x0C 20. " [52] ,Sample bit 52" "Not occurred,Occurred" newline bitfld.long 0x0C 19. " [51] ,Sample bit 51" "Not occurred,Occurred" bitfld.long 0x0C 18. " [50] ,Sample bit 50" "Not occurred,Occurred" bitfld.long 0x0C 17. " [49] ,Sample bit 49" "Not occurred,Occurred" bitfld.long 0x0C 16. " [48] ,Sample bit 48" "Not occurred,Occurred" newline bitfld.long 0x0C 15. " [47] ,Sample bit 47" "Not occurred,Occurred" bitfld.long 0x0C 14. " [46] ,Sample bit 46" "Not occurred,Occurred" bitfld.long 0x0C 13. " [45] ,Sample bit 45" "Not occurred,Occurred" bitfld.long 0x0C 12. " [44] ,Sample bit 44" "Not occurred,Occurred" newline bitfld.long 0x0C 11. " [43] ,Sample bit 43" "Not occurred,Occurred" bitfld.long 0x0C 10. " [42] ,Sample bit 42" "Not occurred,Occurred" bitfld.long 0x0C 9. " [41] ,Sample bit 41" "Not occurred,Occurred" bitfld.long 0x0C 8. " [40] ,Sample bit 40" "Not occurred,Occurred" newline bitfld.long 0x0C 7. " [39] ,Sample bit 39" "Not occurred,Occurred" bitfld.long 0x0C 6. " [38] ,Sample bit 38" "Not occurred,Occurred" bitfld.long 0x0C 5. " [37] ,Sample bit 37" "Not occurred,Occurred" bitfld.long 0x0C 4. " [36] ,Sample bit 36" "Not occurred,Occurred" newline bitfld.long 0x0C 3. " [35] ,Sample bit 35" "Not occurred,Occurred" bitfld.long 0x0C 2. " [34] ,Sample bit 34" "Not occurred,Occurred" bitfld.long 0x0C 1. " [33] ,Sample bit 33" "Not occurred,Occurred" bitfld.long 0x0C 0. " [32] ,Sample bit 32" "Not occurred,Occurred" line.long 0x10 "SPLR2,Sample Register" bitfld.long 0x10 31. " SPL_[95] ,Sample bit 95" "Not occurred,Occurred" bitfld.long 0x10 30. " [94] ,Sample bit 94" "Not occurred,Occurred" bitfld.long 0x10 29. " [93] ,Sample bit 93" "Not occurred,Occurred" bitfld.long 0x10 28. " [92] ,Sample bit 92" "Not occurred,Occurred" newline bitfld.long 0x10 27. " [91] ,Sample bit 91" "Not occurred,Occurred" bitfld.long 0x10 26. " [90] ,Sample bit 90" "Not occurred,Occurred" bitfld.long 0x10 25. " [89] ,Sample bit 89" "Not occurred,Occurred" bitfld.long 0x10 24. " [88] ,Sample bit 88" "Not occurred,Occurred" newline bitfld.long 0x10 23. " [87] ,Sample bit 87" "Not occurred,Occurred" bitfld.long 0x10 22. " [86] ,Sample bit 86" "Not occurred,Occurred" bitfld.long 0x10 21. " [85] ,Sample bit 85" "Not occurred,Occurred" bitfld.long 0x10 20. " [84] ,Sample bit 84" "Not occurred,Occurred" newline bitfld.long 0x10 19. " [83] ,Sample bit 83" "Not occurred,Occurred" bitfld.long 0x10 18. " [82] ,Sample bit 82" "Not occurred,Occurred" bitfld.long 0x10 17. " [81] ,Sample bit 81" "Not occurred,Occurred" bitfld.long 0x10 16. " [80] ,Sample bit 80" "Not occurred,Occurred" newline bitfld.long 0x10 15. " [79] ,Sample bit 79" "Not occurred,Occurred" bitfld.long 0x10 14. " [78] ,Sample bit 78" "Not occurred,Occurred" bitfld.long 0x10 13. " [77] ,Sample bit 77" "Not occurred,Occurred" bitfld.long 0x10 12. " [76] ,Sample bit 76" "Not occurred,Occurred" newline bitfld.long 0x10 11. " [75] ,Sample bit 75" "Not occurred,Occurred" bitfld.long 0x10 10. " [74] ,Sample bit 74" "Not occurred,Occurred" bitfld.long 0x10 9. " [73] ,Sample bit 73" "Not occurred,Occurred" bitfld.long 0x10 8. " [72] ,Sample bit 72" "Not occurred,Occurred" newline bitfld.long 0x10 7. " [71] ,Sample bit 71" "Not occurred,Occurred" bitfld.long 0x10 6. " [70] ,Sample bit 70" "Not occurred,Occurred" bitfld.long 0x10 5. " [69] ,Sample bit 69" "Not occurred,Occurred" bitfld.long 0x10 4. " [68] ,Sample bit 68" "Not occurred,Occurred" newline bitfld.long 0x10 3. " [67] ,Sample bit 67" "Not occurred,Occurred" bitfld.long 0x10 2. " [66] ,Sample bit 66" "Not occurred,Occurred" bitfld.long 0x10 1. " [65] ,Sample bit 65" "Not occurred,Occurred" bitfld.long 0x10 0. " [64] ,Sample bit 64" "Not occurred,Occurred" line.long 0x14 "SPLR3,Sample Register" bitfld.long 0x14 31. " SPL_[127] ,Sample bit 127" "Not occurred,Occurred" bitfld.long 0x14 30. " [126] ,Sample bit 126" "Not occurred,Occurred" bitfld.long 0x14 29. " [125] ,Sample bit 125" "Not occurred,Occurred" bitfld.long 0x14 28. " [124] ,Sample bit 124" "Not occurred,Occurred" newline bitfld.long 0x14 27. " [123] ,Sample bit 123" "Not occurred,Occurred" bitfld.long 0x14 26. " [122] ,Sample bit 122" "Not occurred,Occurred" bitfld.long 0x14 25. " [121] ,Sample bit 121" "Not occurred,Occurred" bitfld.long 0x14 24. " [120] ,Sample bit 120" "Not occurred,Occurred" newline bitfld.long 0x14 23. " [119] ,Sample bit 119" "Not occurred,Occurred" bitfld.long 0x14 22. " [118] ,Sample bit 118" "Not occurred,Occurred" bitfld.long 0x14 21. " [117] ,Sample bit 117" "Not occurred,Occurred" bitfld.long 0x14 20. " [116] ,Sample bit 116" "Not occurred,Occurred" newline bitfld.long 0x14 19. " [115] ,Sample bit 115" "Not occurred,Occurred" bitfld.long 0x14 18. " [114] ,Sample bit 114" "Not occurred,Occurred" bitfld.long 0x14 17. " [113] ,Sample bit 113" "Not occurred,Occurred" bitfld.long 0x14 16. " [112] ,Sample bit 112" "Not occurred,Occurred" newline bitfld.long 0x14 15. " [111] ,Sample bit 111" "Not occurred,Occurred" bitfld.long 0x14 14. " [110] ,Sample bit 110" "Not occurred,Occurred" bitfld.long 0x14 13. " [109] ,Sample bit 109" "Not occurred,Occurred" bitfld.long 0x14 12. " [108] ,Sample bit 108" "Not occurred,Occurred" newline bitfld.long 0x14 11. " [107] ,Sample bit 107" "Not occurred,Occurred" bitfld.long 0x14 10. " [106] ,Sample bit 106" "Not occurred,Occurred" bitfld.long 0x14 9. " [105] ,Sample bit 105" "Not occurred,Occurred" bitfld.long 0x14 8. " [104] ,Sample bit 104" "Not occurred,Occurred" newline bitfld.long 0x14 7. " [103] ,Sample bit 103" "Not occurred,Occurred" bitfld.long 0x14 6. " [102] ,Sample bit 102" "Not occurred,Occurred" bitfld.long 0x14 5. " [101] ,Sample bit 101" "Not occurred,Occurred" bitfld.long 0x14 4. " [100] ,Sample bit 100" "Not occurred,Occurred" newline bitfld.long 0x14 3. " [99] ,Sample bit 99" "Not occurred,Occurred" bitfld.long 0x14 2. " [98] ,Sample bit 98" "Not occurred,Occurred" bitfld.long 0x14 1. " [97] ,Sample bit 97" "Not occurred,Occurred" bitfld.long 0x14 0. " [96] ,Sample bit 96" "Not occurred,Occurred" line.long 0x18 "SPLR4,Sample Register" bitfld.long 0x18 31. " SPL_[159] ,Sample bit 159" "Not occurred,Occurred" bitfld.long 0x18 30. " [158] ,Sample bit 158" "Not occurred,Occurred" bitfld.long 0x18 29. " [157] ,Sample bit 157" "Not occurred,Occurred" bitfld.long 0x18 28. " [156] ,Sample bit 156" "Not occurred,Occurred" newline bitfld.long 0x18 27. " [155] ,Sample bit 155" "Not occurred,Occurred" bitfld.long 0x18 26. " [154] ,Sample bit 154" "Not occurred,Occurred" bitfld.long 0x18 25. " [153] ,Sample bit 153" "Not occurred,Occurred" bitfld.long 0x18 24. " [152] ,Sample bit 152" "Not occurred,Occurred" newline bitfld.long 0x18 23. " [151] ,Sample bit 151" "Not occurred,Occurred" bitfld.long 0x18 22. " [150] ,Sample bit 150" "Not occurred,Occurred" bitfld.long 0x18 21. " [149] ,Sample bit 149" "Not occurred,Occurred" bitfld.long 0x18 20. " [148] ,Sample bit 148" "Not occurred,Occurred" newline bitfld.long 0x18 19. " [147] ,Sample bit 147" "Not occurred,Occurred" bitfld.long 0x18 18. " [146] ,Sample bit 146" "Not occurred,Occurred" bitfld.long 0x18 17. " [145] ,Sample bit 145" "Not occurred,Occurred" bitfld.long 0x18 16. " [144] ,Sample bit 144" "Not occurred,Occurred" newline bitfld.long 0x18 15. " [143] ,Sample bit 143" "Not occurred,Occurred" bitfld.long 0x18 14. " [142] ,Sample bit 142" "Not occurred,Occurred" bitfld.long 0x18 13. " [141] ,Sample bit 141" "Not occurred,Occurred" bitfld.long 0x18 12. " [140] ,Sample bit 140" "Not occurred,Occurred" newline bitfld.long 0x18 11. " [139] ,Sample bit 139" "Not occurred,Occurred" bitfld.long 0x18 10. " [138] ,Sample bit 138" "Not occurred,Occurred" bitfld.long 0x18 9. " [137] ,Sample bit 137" "Not occurred,Occurred" bitfld.long 0x18 8. " [136] ,Sample bit 136" "Not occurred,Occurred" newline bitfld.long 0x18 7. " [135] ,Sample bit 135" "Not occurred,Occurred" bitfld.long 0x18 6. " [134] ,Sample bit 134" "Not occurred,Occurred" bitfld.long 0x18 5. " [133] ,Sample bit 133" "Not occurred,Occurred" bitfld.long 0x18 4. " [132] ,Sample bit 132" "Not occurred,Occurred" newline bitfld.long 0x18 3. " [131] ,Sample bit 131" "Not occurred,Occurred" bitfld.long 0x18 2. " [130] ,Sample bit 130" "Not occurred,Occurred" bitfld.long 0x18 1. " [129] ,Sample bit 129" "Not occurred,Occurred" bitfld.long 0x18 0. " [128] ,Sample bit 128" "Not occurred,Occurred" line.long 0x1C "SPLR5,Sample Register" bitfld.long 0x1C 31. " SPL_[191] ,Sample bit 191" "Not occurred,Occurred" bitfld.long 0x1C 30. " [190] ,Sample bit 190" "Not occurred,Occurred" bitfld.long 0x1C 29. " [189] ,Sample bit 189" "Not occurred,Occurred" bitfld.long 0x1C 28. " [188] ,Sample bit 188" "Not occurred,Occurred" newline bitfld.long 0x1C 27. " [187] ,Sample bit 187" "Not occurred,Occurred" bitfld.long 0x1C 26. " [186] ,Sample bit 186" "Not occurred,Occurred" bitfld.long 0x1C 25. " [185] ,Sample bit 185" "Not occurred,Occurred" bitfld.long 0x1C 24. " [184] ,Sample bit 184" "Not occurred,Occurred" newline bitfld.long 0x1C 23. " [183] ,Sample bit 183" "Not occurred,Occurred" bitfld.long 0x1C 22. " [182] ,Sample bit 182" "Not occurred,Occurred" bitfld.long 0x1C 21. " [181] ,Sample bit 181" "Not occurred,Occurred" bitfld.long 0x1C 20. " [180] ,Sample bit 180" "Not occurred,Occurred" newline bitfld.long 0x1C 19. " [179] ,Sample bit 179" "Not occurred,Occurred" bitfld.long 0x1C 18. " [178] ,Sample bit 178" "Not occurred,Occurred" bitfld.long 0x1C 17. " [177] ,Sample bit 177" "Not occurred,Occurred" bitfld.long 0x1C 16. " [176] ,Sample bit 176" "Not occurred,Occurred" newline bitfld.long 0x1C 15. " [175] ,Sample bit 175" "Not occurred,Occurred" bitfld.long 0x1C 14. " [174] ,Sample bit 174" "Not occurred,Occurred" bitfld.long 0x1C 13. " [173] ,Sample bit 173" "Not occurred,Occurred" bitfld.long 0x1C 12. " [172] ,Sample bit 172" "Not occurred,Occurred" newline bitfld.long 0x1C 11. " [171] ,Sample bit 171" "Not occurred,Occurred" bitfld.long 0x1C 10. " [170] ,Sample bit 170" "Not occurred,Occurred" bitfld.long 0x1C 9. " [169] ,Sample bit 169" "Not occurred,Occurred" bitfld.long 0x1C 8. " [168] ,Sample bit 168" "Not occurred,Occurred" newline bitfld.long 0x1C 7. " [167] ,Sample bit 167" "Not occurred,Occurred" bitfld.long 0x1C 6. " [166] ,Sample bit 166" "Not occurred,Occurred" bitfld.long 0x1C 5. " [165] ,Sample bit 165" "Not occurred,Occurred" bitfld.long 0x1C 4. " [164] ,Sample bit 164" "Not occurred,Occurred" newline bitfld.long 0x1C 3. " [163] ,Sample bit 163" "Not occurred,Occurred" bitfld.long 0x1C 2. " [162] ,Sample bit 162" "Not occurred,Occurred" bitfld.long 0x1C 1. " [161] ,Sample bit 161" "Not occurred,Occurred" bitfld.long 0x1C 0. " [160] ,Sample bit 160" "Not occurred,Occurred" line.long 0x20 "SPLR6,Sample Register" bitfld.long 0x20 31. " SPL_[223] ,Sample bit 223" "Not occurred,Occurred" bitfld.long 0x20 30. " [222] ,Sample bit 222" "Not occurred,Occurred" bitfld.long 0x20 29. " [221] ,Sample bit 221" "Not occurred,Occurred" bitfld.long 0x20 28. " [220] ,Sample bit 220" "Not occurred,Occurred" newline bitfld.long 0x20 27. " [219] ,Sample bit 219" "Not occurred,Occurred" bitfld.long 0x20 26. " [218] ,Sample bit 218" "Not occurred,Occurred" bitfld.long 0x20 25. " [217] ,Sample bit 217" "Not occurred,Occurred" bitfld.long 0x20 24. " [216] ,Sample bit 216" "Not occurred,Occurred" newline bitfld.long 0x20 23. " [215] ,Sample bit 215" "Not occurred,Occurred" bitfld.long 0x20 22. " [214] ,Sample bit 214" "Not occurred,Occurred" bitfld.long 0x20 21. " [213] ,Sample bit 213" "Not occurred,Occurred" bitfld.long 0x20 20. " [212] ,Sample bit 212" "Not occurred,Occurred" newline bitfld.long 0x20 19. " [211] ,Sample bit 211" "Not occurred,Occurred" bitfld.long 0x20 18. " [210] ,Sample bit 210" "Not occurred,Occurred" bitfld.long 0x20 17. " [209] ,Sample bit 209" "Not occurred,Occurred" bitfld.long 0x20 16. " [208] ,Sample bit 208" "Not occurred,Occurred" newline bitfld.long 0x20 15. " [207] ,Sample bit 207" "Not occurred,Occurred" bitfld.long 0x20 14. " [206] ,Sample bit 206" "Not occurred,Occurred" bitfld.long 0x20 13. " [205] ,Sample bit 205" "Not occurred,Occurred" bitfld.long 0x20 12. " [204] ,Sample bit 204" "Not occurred,Occurred" newline bitfld.long 0x20 11. " [203] ,Sample bit 203" "Not occurred,Occurred" bitfld.long 0x20 10. " [202] ,Sample bit 202" "Not occurred,Occurred" bitfld.long 0x20 9. " [201] ,Sample bit 201" "Not occurred,Occurred" bitfld.long 0x20 8. " [200] ,Sample bit 200" "Not occurred,Occurred" newline bitfld.long 0x20 7. " [199] ,Sample bit 199" "Not occurred,Occurred" bitfld.long 0x20 6. " [198] ,Sample bit 198" "Not occurred,Occurred" bitfld.long 0x20 5. " [197] ,Sample bit 197" "Not occurred,Occurred" bitfld.long 0x20 4. " [196] ,Sample bit 196" "Not occurred,Occurred" newline bitfld.long 0x20 3. " [195] ,Sample bit 195" "Not occurred,Occurred" bitfld.long 0x20 2. " [194] ,Sample bit 194" "Not occurred,Occurred" bitfld.long 0x20 1. " [193] ,Sample bit 193" "Not occurred,Occurred" bitfld.long 0x20 0. " [192] ,Sample bit 192" "Not occurred,Occurred" line.long 0x24 "SPLR7,Sample Register" bitfld.long 0x24 31. " SPL_[255] ,Sample bit 255" "Not occurred,Occurred" bitfld.long 0x24 30. " [254] ,Sample bit 254" "Not occurred,Occurred" bitfld.long 0x24 29. " [253] ,Sample bit 253" "Not occurred,Occurred" bitfld.long 0x24 28. " [252] ,Sample bit 252" "Not occurred,Occurred" newline bitfld.long 0x24 27. " [251] ,Sample bit 251" "Not occurred,Occurred" bitfld.long 0x24 26. " [250] ,Sample bit 250" "Not occurred,Occurred" bitfld.long 0x24 25. " [249] ,Sample bit 249" "Not occurred,Occurred" bitfld.long 0x24 24. " [248] ,Sample bit 248" "Not occurred,Occurred" newline bitfld.long 0x24 23. " [247] ,Sample bit 247" "Not occurred,Occurred" bitfld.long 0x24 22. " [246] ,Sample bit 246" "Not occurred,Occurred" bitfld.long 0x24 21. " [245] ,Sample bit 245" "Not occurred,Occurred" bitfld.long 0x24 20. " [244] ,Sample bit 244" "Not occurred,Occurred" newline bitfld.long 0x24 19. " [243] ,Sample bit 243" "Not occurred,Occurred" bitfld.long 0x24 18. " [242] ,Sample bit 242" "Not occurred,Occurred" bitfld.long 0x24 17. " [241] ,Sample bit 241" "Not occurred,Occurred" bitfld.long 0x24 16. " [240] ,Sample bit 240" "Not occurred,Occurred" newline bitfld.long 0x24 15. " [239] ,Sample bit 239" "Not occurred,Occurred" bitfld.long 0x24 14. " [238] ,Sample bit 238" "Not occurred,Occurred" bitfld.long 0x24 13. " [237] ,Sample bit 237" "Not occurred,Occurred" bitfld.long 0x24 12. " [236] ,Sample bit 236" "Not occurred,Occurred" newline bitfld.long 0x24 11. " [235] ,Sample bit 235" "Not occurred,Occurred" bitfld.long 0x24 10. " [234] ,Sample bit 234" "Not occurred,Occurred" bitfld.long 0x24 9. " [233] ,Sample bit 233" "Not occurred,Occurred" bitfld.long 0x24 8. " [232] ,Sample bit 232" "Not occurred,Occurred" newline bitfld.long 0x24 7. " [231] ,Sample bit 231" "Not occurred,Occurred" bitfld.long 0x24 6. " [230] ,Sample bit 230" "Not occurred,Occurred" bitfld.long 0x24 5. " [229] ,Sample bit 229" "Not occurred,Occurred" bitfld.long 0x24 4. " [228] ,Sample bit 228" "Not occurred,Occurred" newline bitfld.long 0x24 3. " [227] ,Sample bit 227" "Not occurred,Occurred" bitfld.long 0x24 2. " [226] ,Sample bit 226" "Not occurred,Occurred" bitfld.long 0x24 1. " [225] ,Sample bit 225" "Not occurred,Occurred" bitfld.long 0x24 0. " [224] ,Sample bit 224" "Not occurred,Occurred" width 0x0B tree.end tree.open "CRC (Cyclic Redundancy Check)" tree "Channel 0" base ad:0xB4718000 width 9. group.byte 0x00++0x00 line.byte 0x00 "CRCCR,CRC Control Register" bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available" bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB" bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian" newline bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB" bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian" bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32" newline bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled" if (((per.b(ad:0xB4718000))&0x02)==0x00) group.long 0x04++0x03 line.long 0x00 "CRCINIT,Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits" else group.long 0x04++0x03 line.long 0x00 "CRCINIT,Initial Value Register" endif group.long 0x08++0x03 line.long 0x00 "CRCIN,Input Data Register" if (((per.b(ad:0xB4718000))&0x12)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits" elif (((per.b(ad:0xB4718000))&0x12)==0x10) rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits" else rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" endif width 0x0B tree.end tree "Channel 1" base ad:0xB4718400 width 9. group.byte 0x00++0x00 line.byte 0x00 "CRCCR,CRC Control Register" bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available" bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB" bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian" newline bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB" bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian" bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32" newline bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled" if (((per.b(ad:0xB4718400))&0x02)==0x00) group.long 0x04++0x03 line.long 0x00 "CRCINIT,Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits" else group.long 0x04++0x03 line.long 0x00 "CRCINIT,Initial Value Register" endif group.long 0x08++0x03 line.long 0x00 "CRCIN,Input Data Register" if (((per.b(ad:0xB4718400))&0x12)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits" elif (((per.b(ad:0xB4718400))&0x12)==0x10) rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits" else rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" endif width 0x0B tree.end tree "Channel 2" base ad:0xB4718800 width 9. group.byte 0x00++0x00 line.byte 0x00 "CRCCR,CRC Control Register" bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available" bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB" bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian" newline bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB" bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian" bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32" newline bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled" if (((per.b(ad:0xB4718800))&0x02)==0x00) group.long 0x04++0x03 line.long 0x00 "CRCINIT,Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits" else group.long 0x04++0x03 line.long 0x00 "CRCINIT,Initial Value Register" endif group.long 0x08++0x03 line.long 0x00 "CRCIN,Input Data Register" if (((per.b(ad:0xB4718800))&0x12)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits" elif (((per.b(ad:0xB4718800))&0x12)==0x10) rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits" else rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" endif width 0x0B tree.end tree "Channel 3" base ad:0xB4718C00 width 9. group.byte 0x00++0x00 line.byte 0x00 "CRCCR,CRC Control Register" bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available" bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB" bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian" newline bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB" bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian" bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32" newline bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled" if (((per.b(ad:0xB4718C00))&0x02)==0x00) group.long 0x04++0x03 line.long 0x00 "CRCINIT,Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits" else group.long 0x04++0x03 line.long 0x00 "CRCINIT,Initial Value Register" endif group.long 0x08++0x03 line.long 0x00 "CRCIN,Input Data Register" if (((per.b(ad:0xB4718C00))&0x12)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits" elif (((per.b(ad:0xB4718C00))&0x12)==0x10) rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits" else rgroup.long 0x0C++0x03 line.long 0x00 "CRCR,CRC Register" endif width 0x0B tree.end tree.end tree.open "I/O PORT" tree "GPIO" base ad:0xB4738000 width 14. group.long 0x204++0x03 line.long 0x00 "DDR0_SET/CLR,Data Direction Set/Clear Register 0" sif cpuis("S6J342?F*") setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " [28] ,Data direction bit 28" "Input,Output" setclrfld.long 0x00 27. -0x1FC 27. -0x1F8 27. " [27] ,Data direction bit 27" "Input,Output" newline setclrfld.long 0x00 22. -0x1FC 22. -0x1F8 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1FC 21. -0x1F8 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1FC 20. -0x1F8 20. " [20] ,Data direction bit 20" "Input,Output" setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " [16] ,Data direction bit 16" "Input,Output" newline setclrfld.long 0x00 15. -0x1FC 15. -0x1F8 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 13. -0x1FC 13. -0x1F8 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1FC 12. -0x1F8 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 10. -0x1FC 10. -0x1F8 10. " [10] ,Data direction bit 10" "Input,Output" newline setclrfld.long 0x00 7. -0x1FC 7. -0x1F8 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1FC 6. -0x1F8 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1FC 5. -0x1F8 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 1. -0x1FC 1. -0x1F8 1. " [1] ,Data direction bit 1" "Input,Output" elif cpuis("S6342?H*") setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1FC 30. -0x1F8 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " [28] ,Data direction bit 28" "Input,Output" newline setclrfld.long 0x00 27. -0x1FC 27. -0x1F8 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 24. -0x1FC 24. -0x1F8 24. " [24] ,Data direction bit 24" "Input,Output" setclrfld.long 0x00 23. -0x1FC 23. -0x1F8 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1FC 22. -0x1F8 22. " [22] ,Data direction bit 22" "Input,Output" newline setclrfld.long 0x00 21. -0x1FC 21. -0x1F8 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1FC 20. -0x1F8 20. " [20] ,Data direction bit 20" "Input,Output" setclrfld.long 0x00 19. -0x1FC 19. -0x1F8 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1FC 18. -0x1F8 18. " [18] ,Data direction bit 18" "Input,Output" newline setclrfld.long 0x00 17. -0x1FC 17. -0x1F8 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " [16] ,Data direction bit 16" "Input,Output" setclrfld.long 0x00 15. -0x1FC 15. -0x1F8 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 13. -0x1FC 13. -0x1F8 13. " [13] ,Data direction bit 13" "Input,Output" newline setclrfld.long 0x00 12. -0x1FC 12. -0x1F8 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 10. -0x1FC 10. -0x1F8 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 9. -0x1FC 9. -0x1F8 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1FC 8. -0x1F8 8. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 7. -0x1FC 7. -0x1F8 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1FC 6. -0x1F8 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1FC 5. -0x1F8 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 3. -0x1FC 3. -0x1F8 3. " [3] ,Data direction bit 3" "Input,Output" newline setclrfld.long 0x00 1. -0x1FC 1. -0x1F8 1. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 0. -0x1FC 0. -0x1F8 0. " [0] ,Data direction bit 0" "Input,Output" else setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1FC 30. -0x1F8 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " [28] ,Data direction bit 28" "Input,Output" newline setclrfld.long 0x00 27. -0x1FC 27. -0x1F8 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1FC 26. -0x1F8 26. " [26] ,Data direction bit 26" "Input,Output" setclrfld.long 0x00 25. -0x1FC 25. -0x1F8 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1FC 24. -0x1F8 24. " [24] ,Data direction bit 24" "Input,Output" newline setclrfld.long 0x00 23. -0x1FC 23. -0x1F8 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1FC 22. -0x1F8 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1FC 21. -0x1F8 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1FC 20. -0x1F8 20. " [20] ,Data direction bit 20" "Input,Output" newline setclrfld.long 0x00 19. -0x1FC 19. -0x1F8 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1FC 18. -0x1F8 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1FC 17. -0x1F8 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " [16] ,Data direction bit 16" "Input,Output" newline setclrfld.long 0x00 15. -0x1FC 15. -0x1F8 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1FC 14. -0x1F8 14. " [14] ,Data direction bit 14" "Input,Output" setclrfld.long 0x00 13. -0x1FC 13. -0x1F8 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1FC 12. -0x1F8 12. " [12] ,Data direction bit 12" "Input,Output" newline setclrfld.long 0x00 11. -0x1FC 11. -0x1F8 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1FC 10. -0x1F8 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 9. -0x1FC 9. -0x1F8 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1FC 8. -0x1F8 8. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 7. -0x1FC 7. -0x1F8 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1FC 6. -0x1F8 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1FC 5. -0x1F8 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 4. -0x1FC 4. -0x1F8 4. " [4] ,Data direction bit 4" "Input,Output" newline setclrfld.long 0x00 3. -0x1FC 3. -0x1F8 3. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 2. -0x1FC 2. -0x1F8 2. " [2] ,Data direction bit 2" "Input,Output" setclrfld.long 0x00 1. -0x1FC 1. -0x1F8 1. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 0. -0x1FC 0. -0x1F8 0. " [0] ,Data direction bit 0" "Input,Output" endif group.long 0x20C++0x03 line.long 0x00 "DDR1_SET/CLR,Data Direction Set/Clear Register 1" sif cpuis("S6J342?F*") setclrfld.long 0x00 31. -0x1F4 31. -0x1F0 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1F4 30. -0x1F0 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 28. -0x1F4 28. -0x1F0 28. " [28] ,Data direction bit 28" "Input,Output" setclrfld.long 0x00 26. -0x1F4 26. -0x1F0 26. " [26] ,Data direction bit 26" "Input,Output" newline setclrfld.long 0x00 23. -0x1F4 23. -0x1F0 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1F4 22. -0x1F0 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 19. -0x1F4 19. -0x1F0 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 17. -0x1F4 17. -0x1F0 17. " [17] ,Data direction bit 17" "Input,Output" newline setclrfld.long 0x00 14. -0x1F4 14. -0x1F0 14. " [14] ,Data direction bit 14" "Input,Output" setclrfld.long 0x00 12. -0x1F4 12. -0x1F0 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 9. -0x1F4 9. -0x1F0 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1F4 8. -0x1F0 8. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 7. -0x1F4 7. -0x1F0 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1F4 6. -0x1F0 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1F4 5. -0x1F0 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 3. -0x1F4 3. -0x1F0 3. " [3] ,Data direction bit 3" "Input,Output" newline setclrfld.long 0x00 0. -0x1F4 0. -0x1F0 0. " [0] ,Data direction bit 0" "Input,Output" elif cpuis("S6J342?H*") setclrfld.long 0x00 31. -0x1F4 31. -0x1F0 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1F4 30. -0x1F0 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1F4 29. -0x1F0 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1F4 28. -0x1F0 28. " [28] ,Data direction bit 28" "Input,Output" newline setclrfld.long 0x00 27. -0x1F4 27. -0x1F0 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1F4 26. -0x1F0 26. " [26] ,Data direction bit 26" "Input,Output" setclrfld.long 0x00 23. -0x1F4 23. -0x1F0 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1F4 22. -0x1F0 22. " [22] ,Data direction bit 22" "Input,Output" newline setclrfld.long 0x00 20. -0x1F4 20. -0x1F0 20. " [20] ,Data direction bit 20" "Input,Output" setclrfld.long 0x00 19. -0x1F4 19. -0x1F0 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1F4 18. -0x1F0 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1F4 17. -0x1F0 17. " [17] ,Data direction bit 17" "Input,Output" newline setclrfld.long 0x00 15. -0x1F4 15. -0x1F0 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1F4 14. -0x1F0 14. " [14] ,Data direction bit 14" "Input,Output" setclrfld.long 0x00 13. -0x1F4 13. -0x1F0 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1F4 12. -0x1F0 12. " [12] ,Data direction bit 12" "Input,Output" newline setclrfld.long 0x00 9. -0x1F4 9. -0x1F0 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1F4 8. -0x1F0 8. " [8] ,Data direction bit 8" "Input,Output" setclrfld.long 0x00 7. -0x1F4 7. -0x1F0 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1F4 6. -0x1F0 6. " [6] ,Data direction bit 6" "Input,Output" newline setclrfld.long 0x00 5. -0x1F4 5. -0x1F0 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 3. -0x1F4 3. -0x1F0 3. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 1. -0x1F4 1. -0x1F0 1. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 0. -0x1F4 0. -0x1F0 0. " [0] ,Data direction bit 0" "Input,Output" else setclrfld.long 0x00 31. -0x1F4 31. -0x1F0 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1F4 30. -0x1F0 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1F4 29. -0x1F0 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1F4 28. -0x1F0 28. " [28] ,Data direction bit 28" "Input,Output" newline setclrfld.long 0x00 27. -0x1F4 27. -0x1F0 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1F4 26. -0x1F0 26. " [26] ,Data direction bit 26" "Input,Output" setclrfld.long 0x00 25. -0x1F4 25. -0x1F0 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1F4 24. -0x1F0 24. " [24] ,Data direction bit 24" "Input,Output" newline setclrfld.long 0x00 23. -0x1F4 23. -0x1F0 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1F4 22. -0x1F0 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1F4 21. -0x1F0 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1F4 20. -0x1F0 20. " [20] ,Data direction bit 20" "Input,Output" newline setclrfld.long 0x00 19. -0x1F4 19. -0x1F0 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1F4 18. -0x1F0 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1F4 17. -0x1F0 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1F4 16. -0x1F0 16. " [16] ,Data direction bit 16" "Input,Output" newline setclrfld.long 0x00 15. -0x1F4 15. -0x1F0 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1F4 14. -0x1F0 14. " [14] ,Data direction bit 14" "Input,Output" setclrfld.long 0x00 13. -0x1F4 13. -0x1F0 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1F4 12. -0x1F0 12. " [12] ,Data direction bit 12" "Input,Output" newline setclrfld.long 0x00 11. -0x1F4 11. -0x1F0 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1F4 10. -0x1F0 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 9. -0x1F4 9. -0x1F0 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1F4 8. -0x1F0 8. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 7. -0x1F4 7. -0x1F0 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1F4 6. -0x1F0 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1F4 5. -0x1F0 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 4. -0x1F4 4. -0x1F0 4. " [4] ,Data direction bit 4" "Input,Output" newline setclrfld.long 0x00 3. -0x1F4 3. -0x1F0 3. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 2. -0x1F4 2. -0x1F0 2. " [2] ,Data direction bit 2" "Input,Output" setclrfld.long 0x00 1. -0x1F4 1. -0x1F0 1. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 0. -0x1F4 0. -0x1F0 0. " [0] ,Data direction bit 0" "Input,Output" endif group.long 0x214++0x03 line.long 0x00 "DDR2_SET/CLR,Data Direction Set/Clear Register 2" sif cpuis("S6J342?F*") setclrfld.long 0x00 29. -0x1EC 29. -0x1E8 29. " DD[29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1EC 28. -0x1E8 28. " [28] ,Data direction bit 28" "Input,Output" setclrfld.long 0x00 27. -0x1EC 27. -0x1E8 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1EC 26. -0x1E8 26. " [26] ,Data direction bit 26" "Input,Output" newline setclrfld.long 0x00 25. -0x1EC 25. -0x1E8 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1EC 24. -0x1E8 24. " [24] ,Data direction bit 24" "Input,Output" setclrfld.long 0x00 23. -0x1EC 23. -0x1E8 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1EC 22. -0x1E8 22. " [22] ,Data direction bit 22" "Input,Output" newline setclrfld.long 0x00 20. -0x1EC 20. -0x1E8 20. " [20] ,Data direction bit 20" "Input,Output" setclrfld.long 0x00 15. -0x1EC 15. -0x1E8 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1EC 14. -0x1E8 14. " [14] ,Data direction bit 14" "Input,Output" setclrfld.long 0x00 13. -0x1EC 13. -0x1E8 13. " [13] ,Data direction bit 13" "Input,Output" newline setclrfld.long 0x00 11. -0x1EC 11. -0x1E8 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 9. -0x1EC 9. -0x1E8 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 7. -0x1EC 7. -0x1E8 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 5. -0x1EC 5. -0x1E8 5. " [5] ,Data direction bit 5" "Input,Output" newline setclrfld.long 0x00 4. -0x1EC 4. -0x1E8 4. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 2. -0x1EC 2. -0x1E8 2. " [2] ,Data direction bit 2" "Input,Output" elif cpuis("S6J342?H*") setclrfld.long 0x00 31. -0x1EC 31. -0x1E8 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1EC 30. -0x1E8 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1EC 29. -0x1E8 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1EC 28. -0x1E8 28. " [28] ,Data direction bit 28" "Input,Output" newline setclrfld.long 0x00 27. -0x1EC 27. -0x1E8 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1EC 26. -0x1E8 26. " [26] ,Data direction bit 26" "Input,Output" setclrfld.long 0x00 25. -0x1EC 25. -0x1E8 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1EC 24. -0x1E8 24. " [24] ,Data direction bit 24" "Input,Output" newline setclrfld.long 0x00 23. -0x1EC 23. -0x1E8 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1EC 22. -0x1E8 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 20. -0x1EC 20. -0x1E8 20. " [20] ,Data direction bit 20" "Input,Output" setclrfld.long 0x00 19. -0x1EC 19. -0x1E8 19. " [19] ,Data direction bit 19" "Input,Output" newline setclrfld.long 0x00 18. -0x1EC 18. -0x1E8 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 15. -0x1EC 15. -0x1E8 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1EC 14. -0x1E8 14. " [14] ,Data direction bit 14" "Input,Output" setclrfld.long 0x00 13. -0x1EC 13. -0x1E8 13. " [13] ,Data direction bit 13" "Input,Output" newline setclrfld.long 0x00 12. -0x1EC 12. -0x1E8 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 11. -0x1EC 11. -0x1E8 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1EC 10. -0x1E8 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 9. -0x1EC 9. -0x1E8 9. " [9] ,Data direction bit 9" "Input,Output" newline setclrfld.long 0x00 8. -0x1EC 8. -0x1E8 8. " [8] ,Data direction bit 8" "Input,Output" setclrfld.long 0x00 7. -0x1EC 7. -0x1E8 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1EC 6. -0x1E8 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1EC 5. -0x1E8 5. " [5] ,Data direction bit 5" "Input,Output" newline setclrfld.long 0x00 4. -0x1EC 4. -0x1E8 4. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 3. -0x1EC 3. -0x1E8 3. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 2. -0x1EC 2. -0x1E8 2. " [2] ,Data direction bit 2" "Input,Output" elif cpuis("S6J35??J*")||cpuis("S6J35??H*") setclrfld.long 0x00 29. -0x1EC 29. -0x1E8 29. " DD[29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1EC 28. -0x1E8 28. " [28] ,Data direction bit 28" "Input,Output" setclrfld.long 0x00 27. -0x1EC 27. -0x1E8 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1EC 26. -0x1E8 26. " [26] ,Data direction bit 26" "Input,Output" newline setclrfld.long 0x00 25. -0x1EC 25. -0x1E8 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1EC 24. -0x1E8 24. " [24] ,Data direction bit 24" "Input,Output" setclrfld.long 0x00 23. -0x1EC 23. -0x1E8 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1EC 22. -0x1E8 22. " [22] ,Data direction bit 22" "Input,Output" newline setclrfld.long 0x00 21. -0x1EC 21. -0x1E8 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1EC 20. -0x1E8 20. " [20] ,Data direction bit 20" "Input,Output" setclrfld.long 0x00 19. -0x1EC 19. -0x1E8 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1EC 18. -0x1E8 18. " [18] ,Data direction bit 18" "Input,Output" newline setclrfld.long 0x00 17. -0x1EC 17. -0x1E8 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1EC 16. -0x1E8 16. " [16] ,Data direction bit 16" "Input,Output" setclrfld.long 0x00 15. -0x1EC 15. -0x1E8 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1EC 14. -0x1E8 14. " [14] ,Data direction bit 14" "Input,Output" newline setclrfld.long 0x00 13. -0x1EC 13. -0x1E8 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1EC 12. -0x1E8 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 11. -0x1EC 11. -0x1E8 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1EC 10. -0x1E8 10. " [10] ,Data direction bit 10" "Input,Output" newline setclrfld.long 0x00 9. -0x1EC 9. -0x1E8 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1EC 8. -0x1E8 8. " [8] ,Data direction bit 8" "Input,Output" setclrfld.long 0x00 7. -0x1EC 7. -0x1E8 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1EC 6. -0x1E8 6. " [6] ,Data direction bit 6" "Input,Output" newline setclrfld.long 0x00 5. -0x1EC 5. -0x1E8 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 4. -0x1EC 4. -0x1E8 4. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 3. -0x1EC 3. -0x1E8 3. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 2. -0x1EC 2. -0x1E8 2. " [2] ,Data direction bit 2" "Input,Output" newline setclrfld.long 0x00 1. -0x1EC 1. -0x1E8 1. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 0. -0x1EC 0. -0x1E8 0. " [0] ,Data direction bit 0" "Input,Output" else setclrfld.long 0x00 31. -0x1EC 31. -0x1E8 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1EC 30. -0x1E8 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1EC 29. -0x1E8 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1EC 28. -0x1E8 28. " [28] ,Data direction bit 28" "Input,Output" newline setclrfld.long 0x00 27. -0x1EC 27. -0x1E8 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1EC 26. -0x1E8 26. " [26] ,Data direction bit 26" "Input,Output" setclrfld.long 0x00 25. -0x1EC 25. -0x1E8 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1EC 24. -0x1E8 24. " [24] ,Data direction bit 24" "Input,Output" newline setclrfld.long 0x00 23. -0x1EC 23. -0x1E8 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1EC 22. -0x1E8 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1EC 21. -0x1E8 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1EC 20. -0x1E8 20. " [20] ,Data direction bit 20" "Input,Output" newline setclrfld.long 0x00 19. -0x1EC 19. -0x1E8 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1EC 18. -0x1E8 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1EC 17. -0x1E8 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1EC 16. -0x1E8 16. " [16] ,Data direction bit 16" "Input,Output" newline setclrfld.long 0x00 15. -0x1EC 15. -0x1E8 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1EC 14. -0x1E8 14. " [14] ,Data direction bit 14" "Input,Output" setclrfld.long 0x00 13. -0x1EC 13. -0x1E8 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1EC 12. -0x1E8 12. " [12] ,Data direction bit 12" "Input,Output" newline setclrfld.long 0x00 11. -0x1EC 11. -0x1E8 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1EC 10. -0x1E8 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 9. -0x1EC 9. -0x1E8 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1EC 8. -0x1E8 8. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 7. -0x1EC 7. -0x1E8 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1EC 6. -0x1E8 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1EC 5. -0x1E8 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 4. -0x1EC 4. -0x1E8 4. " [4] ,Data direction bit 4" "Input,Output" newline setclrfld.long 0x00 3. -0x1EC 3. -0x1E8 3. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 2. -0x1EC 2. -0x1E8 2. " [2] ,Data direction bit 2" "Input,Output" setclrfld.long 0x00 1. -0x1EC 1. -0x1E8 1. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 0. -0x1EC 0. -0x1E8 0. " [0] ,Data direction bit 0" "Input,Output" endif sif !cpuis("S6J35??H*") group.long 0x21C++0x03 line.long 0x00 "DDR3_SET/CLR,Data Direction Set/Clear Register 3" sif cpuis("S6J342?F*") setclrfld.long 0x00 31. -0x1E4 31. -0x1E0 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 27. -0x1E4 27. -0x1E0 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 24. -0x1E4 24. -0x1E0 24. " [24] ,Data direction bit 24" "Input,Output" setclrfld.long 0x00 23. -0x1E4 23. -0x1E0 23. " [23] ,Data direction bit 23" "Input,Output" newline setclrfld.long 0x00 22. -0x1E4 22. -0x1E0 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1E4 21. -0x1E0 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 15. -0x1E4 15. -0x1E0 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1E4 14. -0x1E0 14. " [14] ,Data direction bit 14" "Input,Output" newline setclrfld.long 0x00 13. -0x1E4 13. -0x1E0 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 9. -0x1E4 9. -0x1E0 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 7. -0x1E4 7. -0x1E0 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 5. -0x1E4 5. -0x1E0 5. " [5] ,Data direction bit 5" "Input,Output" newline setclrfld.long 0x00 4. -0x1E4 4. -0x1E0 4. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 2. -0x1E4 2. -0x1E0 2. " [2] ,Data direction bit 2" "Input,Output" setclrfld.long 0x00 1. -0x1E4 1. -0x1E0 1. " [1] ,Data direction bit 1" "Input,Output" elif cpuis("S6J342?H*") setclrfld.long 0x00 31. -0x1E4 31. -0x1E0 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1E4 30. -0x1E0 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 27. -0x1E4 27. -0x1E0 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 24. -0x1E4 24. -0x1E0 24. " [24] ,Data direction bit 24" "Input,Output" newline setclrfld.long 0x00 23. -0x1E4 23. -0x1E0 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1E4 22. -0x1E0 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1E4 21. -0x1E0 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 19. -0x1E4 19. -0x1E0 19. " [19] ,Data direction bit 19" "Input,Output" newline setclrfld.long 0x00 18. -0x1E4 18. -0x1E0 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1E4 17. -0x1E0 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 15. -0x1E4 15. -0x1E0 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1E4 14. -0x1E0 14. " [14] ,Data direction bit 14" "Input,Output" newline setclrfld.long 0x00 13. -0x1E4 13. -0x1E0 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1E4 12. -0x1E0 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 9. -0x1E4 9. -0x1E0 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1E4 8. -0x1E0 8. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 7. -0x1E4 7. -0x1E0 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1E4 6. -0x1E0 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1E4 5. -0x1E0 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 4. -0x1E4 4. -0x1E0 4. " [4] ,Data direction bit 4" "Input,Output" newline setclrfld.long 0x00 2. -0x1E4 2. -0x1E0 2. " [2] ,Data direction bit 2" "Input,Output" setclrfld.long 0x00 1. -0x1E4 1. -0x1E0 1. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 0. -0x1E4 0. -0x1E0 0. " [0] ,Data direction bit 0" "Input,Output" else setclrfld.long 0x00 31. -0x1E4 31. -0x1E0 31. " DD[31] ,Data direction bit 31" "Input,Output" setclrfld.long 0x00 30. -0x1E4 30. -0x1E0 30. " [30] ,Data direction bit 30" "Input,Output" setclrfld.long 0x00 29. -0x1E4 29. -0x1E0 29. " [29] ,Data direction bit 29" "Input,Output" setclrfld.long 0x00 28. -0x1E4 28. -0x1E0 28. " [28] ,Data direction bit 28" "Input,Output" newline setclrfld.long 0x00 27. -0x1E4 27. -0x1E0 27. " [27] ,Data direction bit 27" "Input,Output" setclrfld.long 0x00 26. -0x1E4 26. -0x1E0 26. " [26] ,Data direction bit 26" "Input,Output" setclrfld.long 0x00 25. -0x1E4 25. -0x1E0 25. " [25] ,Data direction bit 25" "Input,Output" setclrfld.long 0x00 24. -0x1E4 24. -0x1E0 24. " [24] ,Data direction bit 24" "Input,Output" newline setclrfld.long 0x00 23. -0x1E4 23. -0x1E0 23. " [23] ,Data direction bit 23" "Input,Output" setclrfld.long 0x00 22. -0x1E4 22. -0x1E0 22. " [22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1E4 21. -0x1E0 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1E4 20. -0x1E0 20. " [20] ,Data direction bit 20" "Input,Output" newline setclrfld.long 0x00 19. -0x1E4 19. -0x1E0 19. " [19] ,Data direction bit 19" "Input,Output" setclrfld.long 0x00 18. -0x1E4 18. -0x1E0 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1E4 17. -0x1E0 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1E4 16. -0x1E0 16. " [16] ,Data direction bit 16" "Input,Output" newline setclrfld.long 0x00 15. -0x1E4 15. -0x1E0 15. " [15] ,Data direction bit 15" "Input,Output" setclrfld.long 0x00 14. -0x1E4 14. -0x1E0 14. " [14] ,Data direction bit 14" "Input,Output" setclrfld.long 0x00 13. -0x1E4 13. -0x1E0 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1E4 12. -0x1E0 12. " [12] ,Data direction bit 12" "Input,Output" newline setclrfld.long 0x00 11. -0x1E4 11. -0x1E0 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 10. -0x1E4 10. -0x1E0 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 9. -0x1E4 9. -0x1E0 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1E4 8. -0x1E0 8. " [8] ,Data direction bit 8" "Input,Output" newline setclrfld.long 0x00 7. -0x1E4 7. -0x1E0 7. " [7] ,Data direction bit 7" "Input,Output" setclrfld.long 0x00 6. -0x1E4 6. -0x1E0 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1E4 5. -0x1E0 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 4. -0x1E4 4. -0x1E0 4. " [4] ,Data direction bit 4" "Input,Output" newline setclrfld.long 0x00 3. -0x1E4 3. -0x1E0 3. " [3] ,Data direction bit 3" "Input,Output" setclrfld.long 0x00 2. -0x1E4 2. -0x1E0 2. " [2] ,Data direction bit 2" "Input,Output" setclrfld.long 0x00 1. -0x1E4 1. -0x1E0 1. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 0. -0x1E4 0. -0x1E0 0. " [0] ,Data direction bit 0" "Input,Output" endif endif sif !cpuis("S6J35??J*")&&!cpuis("S6J35??H*") group.long 0x224++0x03 line.long 0x00 "DDR4_SET/CLR,Data Direction Set/Clear Register 4" sif cpuis("S6J342?F*") setclrfld.long 0x00 22. -0x1DC 22. -0x1D8 22. " DD[22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 20. -0x1DC 20. -0x1D8 20. " [20] ,Data direction bit 20" "Input,Output" setclrfld.long 0x00 16. -0x1DC 16. -0x1D8 16. " [16] ,Data direction bit 16" "Input,Output" setclrfld.long 0x00 13. -0x1DC 13. -0x1D8 13. " [13] ,Data direction bit 13" "Input,Output" newline setclrfld.long 0x00 9. -0x1DC 9. -0x1D8 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 5. -0x1DC 5. -0x1D8 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 2. -0x1DC 2. -0x1D8 2. " [2] ,Data direction bit 2" "Input,Output" setclrfld.long 0x00 1. -0x1DC 1. -0x1D8 1. " [1] ,Data direction bit 1" "Input,Output" newline setclrfld.long 0x00 0. -0x1DC 0. -0x1D8 0. " [0] ,Data direction bit 0" "Input,Output" elif cpuis("S6J342?H*") setclrfld.long 0x00 22. -0x1DC 22. -0x1D8 22. " DD[22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1DC 21. -0x1D8 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1DC 20. -0x1D8 20. " [20] ,Data direction bit 20" "Input,Output" setclrfld.long 0x00 18. -0x1DC 18. -0x1D8 18. " [18] ,Data direction bit 18" "Input,Output" newline setclrfld.long 0x00 17. -0x1DC 17. -0x1D8 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1DC 16. -0x1D8 16. " [16] ,Data direction bit 16" "Input,Output" setclrfld.long 0x00 14. -0x1DC 14. -0x1D8 14. " [14] ,Data direction bit 14" "Input,Output" setclrfld.long 0x00 13. -0x1DC 13. -0x1D8 13. " [13] ,Data direction bit 13" "Input,Output" newline setclrfld.long 0x00 11. -0x1DC 11. -0x1D8 11. " [11] ,Data direction bit 11" "Input,Output" setclrfld.long 0x00 9. -0x1DC 9. -0x1D8 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1DC 8. -0x1D8 8. " [8] ,Data direction bit 8" "Input,Output" setclrfld.long 0x00 7. -0x1DC 7. -0x1D8 7. " [7] ,Data direction bit 7" "Input,Output" newline setclrfld.long 0x00 6. -0x1DC 6. -0x1D8 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1DC 5. -0x1D8 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 4. -0x1DC 4. -0x1D8 4. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 3. -0x1DC 3. -0x1D8 3. " [3] ,Data direction bit 3" "Input,Output" newline setclrfld.long 0x00 2. -0x1DC 2. -0x1D8 2. " [2] ,Data direction bit 2" "Input,Output" setclrfld.long 0x00 1. -0x1DC 1. -0x1D8 1. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 0. -0x1DC 0. -0x1D8 0. " [0] ,Data direction bit 0" "Input,Output" else setclrfld.long 0x00 22. -0x1DC 22. -0x1D8 22. " DD[22] ,Data direction bit 22" "Input,Output" setclrfld.long 0x00 21. -0x1DC 21. -0x1D8 21. " [21] ,Data direction bit 21" "Input,Output" setclrfld.long 0x00 20. -0x1DC 20. -0x1D8 20. " [20] ,Data direction bit 20" "Input,Output" setclrfld.long 0x00 19. -0x1DC 19. -0x1D8 19. " [19] ,Data direction bit 19" "Input,Output" newline setclrfld.long 0x00 18. -0x1DC 18. -0x1D8 18. " [18] ,Data direction bit 18" "Input,Output" setclrfld.long 0x00 17. -0x1DC 17. -0x1D8 17. " [17] ,Data direction bit 17" "Input,Output" setclrfld.long 0x00 16. -0x1DC 16. -0x1D8 16. " [16] ,Data direction bit 16" "Input,Output" setclrfld.long 0x00 15. -0x1DC 15. -0x1D8 15. " [15] ,Data direction bit 15" "Input,Output" newline setclrfld.long 0x00 14. -0x1DC 14. -0x1D8 14. " [14] ,Data direction bit 14" "Input,Output" setclrfld.long 0x00 13. -0x1DC 13. -0x1D8 13. " [13] ,Data direction bit 13" "Input,Output" setclrfld.long 0x00 12. -0x1DC 12. -0x1D8 12. " [12] ,Data direction bit 12" "Input,Output" setclrfld.long 0x00 11. -0x1DC 11. -0x1D8 11. " [11] ,Data direction bit 11" "Input,Output" newline setclrfld.long 0x00 10. -0x1DC 10. -0x1D8 10. " [10] ,Data direction bit 10" "Input,Output" setclrfld.long 0x00 9. -0x1DC 9. -0x1D8 9. " [9] ,Data direction bit 9" "Input,Output" setclrfld.long 0x00 8. -0x1DC 8. -0x1D8 8. " [8] ,Data direction bit 8" "Input,Output" setclrfld.long 0x00 7. -0x1DC 7. -0x1D8 7. " [7] ,Data direction bit 7" "Input,Output" newline setclrfld.long 0x00 6. -0x1DC 6. -0x1D8 6. " [6] ,Data direction bit 6" "Input,Output" setclrfld.long 0x00 5. -0x1DC 5. -0x1D8 5. " [5] ,Data direction bit 5" "Input,Output" setclrfld.long 0x00 4. -0x1DC 4. -0x1D8 4. " [4] ,Data direction bit 4" "Input,Output" setclrfld.long 0x00 3. -0x1DC 3. -0x1D8 3. " [3] ,Data direction bit 3" "Input,Output" newline setclrfld.long 0x00 2. -0x1DC 2. -0x1D8 2. " [2] ,Data direction bit 2" "Input,Output" setclrfld.long 0x00 1. -0x1DC 1. -0x1D8 1. " [1] ,Data direction bit 1" "Input,Output" setclrfld.long 0x00 0. -0x1DC 0. -0x1D8 0. " [0] ,Data direction bit 0" "Input,Output" endif endif group.long 0x200++0x03 line.long 0x00 "POR0_SET/CLR,Port Output Set/Clear Register 0" sif cpuis("S6J342?F*") setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " [28] ,Port output bit 28" "Low,High" setclrfld.long 0x00 27. -0x200 27. -0x1FC 27. " [27] ,Port output bit 27" "Low,High" newline setclrfld.long 0x00 22. -0x200 22. -0x1FC 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x200 21. -0x1FC 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x200 20. -0x1FC 20. " [20] ,Port output bit 20" "Low,High" setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " [16] ,Port output bit 16" "Low,High" newline setclrfld.long 0x00 15. -0x200 15. -0x1FC 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 13. -0x200 13. -0x1FC 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x200 12. -0x1FC 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 10. -0x200 10. -0x1FC 10. " [10] ,Port output bit 10" "Low,High" newline setclrfld.long 0x00 7. -0x200 7. -0x1FC 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x200 6. -0x1FC 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x200 5. -0x1FC 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 1. -0x200 1. -0x1FC 1. " [1] ,Port output bit 1" "Low,High" elif cpuis("S6J324?H*") setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x200 30. -0x1FC 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " [28] ,Port output bit 28" "Low,High" newline setclrfld.long 0x00 27. -0x200 27. -0x1FC 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 24. -0x200 24. -0x1FC 24. " [24] ,Port output bit 24" "Low,High" setclrfld.long 0x00 23. -0x200 23. -0x1FC 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x200 22. -0x1FC 22. " [22] ,Port output bit 22" "Low,High" newline setclrfld.long 0x00 21. -0x200 21. -0x1FC 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x200 20. -0x1FC 20. " [20] ,Port output bit 20" "Low,High" setclrfld.long 0x00 19. -0x200 19. -0x1FC 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x200 18. -0x1FC 18. " [18] ,Port output bit 18" "Low,High" newline setclrfld.long 0x00 17. -0x200 17. -0x1FC 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " [16] ,Port output bit 16" "Low,High" setclrfld.long 0x00 15. -0x200 15. -0x1FC 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 13. -0x200 13. -0x1FC 13. " [13] ,Port output bit 13" "Low,High" newline setclrfld.long 0x00 12. -0x200 12. -0x1FC 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 10. -0x200 10. -0x1FC 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 9. -0x200 9. -0x1FC 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x200 8. -0x1FC 8. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 7. -0x200 7. -0x1FC 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x200 6. -0x1FC 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x200 5. -0x1FC 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 3. -0x200 3. -0x1FC 3. " [3] ,Port output bit 3" "Low,High" newline setclrfld.long 0x00 1. -0x200 1. -0x1FC 1. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 0. -0x200 0. -0x1FC 0. " [0] ,Port output bit 0" "Low,High" else setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x200 30. -0x1FC 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " [28] ,Port output bit 28" "Low,High" newline setclrfld.long 0x00 27. -0x200 27. -0x1FC 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x200 26. -0x1FC 26. " [26] ,Port output bit 26" "Low,High" setclrfld.long 0x00 25. -0x200 25. -0x1FC 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x200 24. -0x1FC 24. " [24] ,Port output bit 24" "Low,High" newline setclrfld.long 0x00 23. -0x200 23. -0x1FC 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x200 22. -0x1FC 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x200 21. -0x1FC 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x200 20. -0x1FC 20. " [20] ,Port output bit 20" "Low,High" newline setclrfld.long 0x00 19. -0x200 19. -0x1FC 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x200 18. -0x1FC 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x200 17. -0x1FC 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " [16] ,Port output bit 16" "Low,High" newline setclrfld.long 0x00 15. -0x200 15. -0x1FC 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x200 14. -0x1FC 14. " [14] ,Port output bit 14" "Low,High" setclrfld.long 0x00 13. -0x200 13. -0x1FC 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x200 12. -0x1FC 12. " [12] ,Port output bit 12" "Low,High" newline setclrfld.long 0x00 11. -0x200 11. -0x1FC 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x200 10. -0x1FC 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 9. -0x200 9. -0x1FC 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x200 8. -0x1FC 8. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 7. -0x200 7. -0x1FC 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x200 6. -0x1FC 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x200 5. -0x1FC 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 4. -0x200 4. -0x1FC 4. " [4] ,Port output bit 4" "Low,High" newline setclrfld.long 0x00 3. -0x200 3. -0x1FC 3. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 2. -0x200 2. -0x1FC 2. " [2] ,Port output bit 2" "Low,High" setclrfld.long 0x00 1. -0x200 1. -0x1FC 1. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 0. -0x200 0. -0x1FC 0. " [0] ,Port output bit 0" "Low,High" endif group.long 0x208++0x03 line.long 0x00 "POR1_SET/CLR,Port Output Set/Clear Register 1" sif cpuis("S6J342?F*") setclrfld.long 0x00 31. -0x1F8 31. -0x1F4 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x1F8 30. -0x1F4 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 28. -0x1F8 28. -0x1F4 28. " [28] ,Port output bit 28" "Low,High" setclrfld.long 0x00 26. -0x1F8 26. -0x1F4 26. " [26] ,Port output bit 26" "Low,High" newline setclrfld.long 0x00 23. -0x1F8 23. -0x1F4 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1F8 22. -0x1F4 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 19. -0x1F8 19. -0x1F4 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 17. -0x1F8 17. -0x1F4 17. " [17] ,Port output bit 17" "Low,High" newline setclrfld.long 0x00 14. -0x1F8 14. -0x1F4 14. " [14] ,Port output bit 14" "Low,High" setclrfld.long 0x00 12. -0x1F8 12. -0x1F4 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 9. -0x1F8 9. -0x1F4 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x1F8 8. -0x1F4 8. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 7. -0x1F8 7. -0x1F4 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x1F8 6. -0x1F4 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x1F8 5. -0x1F4 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 3. -0x1F8 3. -0x1F4 3. " [3] ,Port output bit 3" "Low,High" newline setclrfld.long 0x00 0. -0x1F8 0. -0x1F4 0. " [0] ,Port output bit 0" "Low,High" elif cpuis("S6J342?H*") setclrfld.long 0x00 31. -0x1F8 31. -0x1F4 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x1F8 30. -0x1F4 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x1F8 29. -0x1F4 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1F8 28. -0x1F4 28. " [28] ,Port output bit 28" "Low,High" newline setclrfld.long 0x00 27. -0x1F8 27. -0x1F4 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1F8 26. -0x1F4 26. " [26] ,Port output bit 26" "Low,High" setclrfld.long 0x00 23. -0x1F8 23. -0x1F4 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1F8 22. -0x1F4 22. " [22] ,Port output bit 22" "Low,High" newline setclrfld.long 0x00 20. -0x1F8 20. -0x1F4 20. " [20] ,Port output bit 20" "Low,High" setclrfld.long 0x00 19. -0x1F8 19. -0x1F4 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x1F8 18. -0x1F4 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x1F8 17. -0x1F4 17. " [17] ,Port output bit 17" "Low,High" newline setclrfld.long 0x00 15. -0x1F8 15. -0x1F4 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1F8 14. -0x1F4 14. " [14] ,Port output bit 14" "Low,High" setclrfld.long 0x00 13. -0x1F8 13. -0x1F4 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1F8 12. -0x1F4 12. " [12] ,Port output bit 12" "Low,High" newline setclrfld.long 0x00 9. -0x1F8 9. -0x1F4 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x1F8 8. -0x1F4 8. " [8] ,Port output bit 8" "Low,High" setclrfld.long 0x00 7. -0x1F8 7. -0x1F4 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x1F8 6. -0x1F4 6. " [6] ,Port output bit 6" "Low,High" newline setclrfld.long 0x00 5. -0x1F8 5. -0x1F4 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 3. -0x1F8 3. -0x1F4 3. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 1. -0x1F8 1. -0x1F4 1. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 0. -0x1F8 0. -0x1F4 0. " [0] ,Port output bit 0" "Low,High" else setclrfld.long 0x00 31. -0x1F8 31. -0x1F4 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x1F8 30. -0x1F4 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x1F8 29. -0x1F4 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1F8 28. -0x1F4 28. " [28] ,Port output bit 28" "Low,High" newline setclrfld.long 0x00 27. -0x1F8 27. -0x1F4 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1F8 26. -0x1F4 26. " [26] ,Port output bit 26" "Low,High" setclrfld.long 0x00 25. -0x1F8 25. -0x1F4 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x1F8 24. -0x1F4 24. " [24] ,Port output bit 24" "Low,High" newline setclrfld.long 0x00 23. -0x1F8 23. -0x1F4 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1F8 22. -0x1F4 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1F8 21. -0x1F4 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x1F8 20. -0x1F4 20. " [20] ,Port output bit 20" "Low,High" newline setclrfld.long 0x00 19. -0x1F8 19. -0x1F4 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x1F8 18. -0x1F4 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x1F8 17. -0x1F4 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x1F8 16. -0x1F4 16. " [16] ,Port output bit 16" "Low,High" newline setclrfld.long 0x00 15. -0x1F8 15. -0x1F4 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1F8 14. -0x1F4 14. " [14] ,Port output bit 14" "Low,High" setclrfld.long 0x00 13. -0x1F8 13. -0x1F4 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1F8 12. -0x1F4 12. " [12] ,Port output bit 12" "Low,High" newline setclrfld.long 0x00 11. -0x1F8 11. -0x1F4 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x1F8 10. -0x1F4 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 9. -0x1F8 9. -0x1F4 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x1F8 8. -0x1F4 8. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 7. -0x1F8 7. -0x1F4 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x1F8 6. -0x1F4 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x1F8 5. -0x1F4 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 4. -0x1F8 4. -0x1F4 4. " [4] ,Port output bit 4" "Low,High" newline setclrfld.long 0x00 3. -0x1F8 3. -0x1F4 3. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 2. -0x1F8 2. -0x1F4 2. " [2] ,Port output bit 2" "Low,High" setclrfld.long 0x00 1. -0x1F8 1. -0x1F4 1. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 0. -0x1F8 0. -0x1F4 0. " [0] ,Port output bit 0" "Low,High" endif group.long 0x210++0x03 line.long 0x00 "POR2_SET/CLR,Port Output Set/Clear Register 2" sif cpuis("S6J342?F*") setclrfld.long 0x00 29. -0x1F0 29. -0x1EC 29. " PO[29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1F0 28. -0x1EC 28. " [28] ,Port output bit 28" "Low,High" setclrfld.long 0x00 27. -0x1F0 27. -0x1EC 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1F0 26. -0x1EC 26. " [26] ,Port output bit 26" "Low,High" newline setclrfld.long 0x00 25. -0x1F0 25. -0x1EC 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x1F0 24. -0x1EC 24. " [24] ,Port output bit 24" "Low,High" setclrfld.long 0x00 23. -0x1F0 23. -0x1EC 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1F0 22. -0x1EC 22. " [22] ,Port output bit 22" "Low,High" newline setclrfld.long 0x00 20. -0x1F0 20. -0x1EC 20. " [20] ,Port output bit 20" "Low,High" setclrfld.long 0x00 15. -0x1F0 15. -0x1EC 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1F0 14. -0x1EC 14. " [14] ,Port output bit 14" "Low,High" setclrfld.long 0x00 13. -0x1F0 13. -0x1EC 13. " [13] ,Port output bit 13" "Low,High" newline setclrfld.long 0x00 11. -0x1F0 11. -0x1EC 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 9. -0x1F0 9. -0x1EC 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 7. -0x1F0 7. -0x1EC 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 5. -0x1F0 5. -0x1EC 5. " [5] ,Port output bit 5" "Low,High" newline setclrfld.long 0x00 4. -0x1F0 4. -0x1EC 4. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 2. -0x1F0 2. -0x1EC 2. " [2] ,Port output bit 2" "Low,High" elif cpuis("S6J342?H*") setclrfld.long 0x00 31. -0x1F0 31. -0x1EC 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x1F0 30. -0x1EC 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x1F0 29. -0x1EC 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1F0 28. -0x1EC 28. " [28] ,Port output bit 28" "Low,High" newline setclrfld.long 0x00 27. -0x1F0 27. -0x1EC 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1F0 26. -0x1EC 26. " [26] ,Port output bit 26" "Low,High" setclrfld.long 0x00 25. -0x1F0 25. -0x1EC 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x1F0 24. -0x1EC 24. " [24] ,Port output bit 24" "Low,High" newline setclrfld.long 0x00 23. -0x1F0 23. -0x1EC 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1F0 22. -0x1EC 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 20. -0x1F0 20. -0x1EC 20. " [20] ,Port output bit 20" "Low,High" setclrfld.long 0x00 19. -0x1F0 19. -0x1EC 19. " [19] ,Port output bit 19" "Low,High" newline setclrfld.long 0x00 18. -0x1F0 18. -0x1EC 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 15. -0x1F0 15. -0x1EC 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1F0 14. -0x1EC 14. " [14] ,Port output bit 14" "Low,High" setclrfld.long 0x00 13. -0x1F0 13. -0x1EC 13. " [13] ,Port output bit 13" "Low,High" newline setclrfld.long 0x00 12. -0x1F0 12. -0x1EC 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 11. -0x1F0 11. -0x1EC 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x1F0 10. -0x1EC 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 9. -0x1F0 9. -0x1EC 9. " [9] ,Port output bit 9" "Low,High" newline setclrfld.long 0x00 8. -0x1F0 8. -0x1EC 8. " [8] ,Port output bit 8" "Low,High" setclrfld.long 0x00 7. -0x1F0 7. -0x1EC 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x1F0 6. -0x1EC 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x1F0 5. -0x1EC 5. " [5] ,Port output bit 5" "Low,High" newline setclrfld.long 0x00 4. -0x1F0 4. -0x1EC 4. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 3. -0x1F0 3. -0x1EC 3. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 2. -0x1F0 2. -0x1EC 2. " [2] ,Port output bit 2" "Low,High" elif cpuis("S6J35??J*")||cpuis("S6J35??H*") setclrfld.long 0x00 29. -0x1F0 29. -0x1EC 29. " PO[29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1F0 28. -0x1EC 28. " [28] ,Port output bit 28" "Low,High" setclrfld.long 0x00 27. -0x1F0 27. -0x1EC 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1F0 26. -0x1EC 26. " [26] ,Port output bit 26" "Low,High" newline setclrfld.long 0x00 25. -0x1F0 25. -0x1EC 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x1F0 24. -0x1EC 24. " [24] ,Port output bit 24" "Low,High" setclrfld.long 0x00 23. -0x1F0 23. -0x1EC 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1F0 22. -0x1EC 22. " [22] ,Port output bit 22" "Low,High" newline setclrfld.long 0x00 21. -0x1F0 21. -0x1EC 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x1F0 20. -0x1EC 20. " [20] ,Port output bit 20" "Low,High" setclrfld.long 0x00 19. -0x1F0 19. -0x1EC 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x1F0 18. -0x1EC 18. " [18] ,Port output bit 18" "Low,High" newline setclrfld.long 0x00 17. -0x1F0 17. -0x1EC 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x1F0 16. -0x1EC 16. " [16] ,Port output bit 16" "Low,High" setclrfld.long 0x00 15. -0x1F0 15. -0x1EC 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1F0 14. -0x1EC 14. " [14] ,Port output bit 14" "Low,High" newline setclrfld.long 0x00 13. -0x1F0 13. -0x1EC 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1F0 12. -0x1EC 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 11. -0x1F0 11. -0x1EC 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x1F0 10. -0x1EC 10. " [10] ,Port output bit 10" "Low,High" newline setclrfld.long 0x00 9. -0x1F0 9. -0x1EC 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x1F0 8. -0x1EC 8. " [8] ,Port output bit 8" "Low,High" setclrfld.long 0x00 7. -0x1F0 7. -0x1EC 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x1F0 6. -0x1EC 6. " [6] ,Port output bit 6" "Low,High" newline setclrfld.long 0x00 5. -0x1F0 5. -0x1EC 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 4. -0x1F0 4. -0x1EC 4. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 3. -0x1F0 3. -0x1EC 3. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 2. -0x1F0 2. -0x1EC 2. " [2] ,Port output bit 2" "Low,High" newline setclrfld.long 0x00 1. -0x1F0 1. -0x1EC 1. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 0. -0x1F0 0. -0x1EC 0. " [0] ,Port output bit 0" "Low,High" else setclrfld.long 0x00 31. -0x1F0 31. -0x1EC 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x1F0 30. -0x1EC 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x1F0 29. -0x1EC 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1F0 28. -0x1EC 28. " [28] ,Port output bit 28" "Low,High" newline setclrfld.long 0x00 27. -0x1F0 27. -0x1EC 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1F0 26. -0x1EC 26. " [26] ,Port output bit 26" "Low,High" setclrfld.long 0x00 25. -0x1F0 25. -0x1EC 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x1F0 24. -0x1EC 24. " [24] ,Port output bit 24" "Low,High" newline setclrfld.long 0x00 23. -0x1F0 23. -0x1EC 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1F0 22. -0x1EC 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1F0 21. -0x1EC 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x1F0 20. -0x1EC 20. " [20] ,Port output bit 20" "Low,High" newline setclrfld.long 0x00 19. -0x1F0 19. -0x1EC 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x1F0 18. -0x1EC 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x1F0 17. -0x1EC 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x1F0 16. -0x1EC 16. " [16] ,Port output bit 16" "Low,High" newline setclrfld.long 0x00 15. -0x1F0 15. -0x1EC 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1F0 14. -0x1EC 14. " [14] ,Port output bit 14" "Low,High" setclrfld.long 0x00 13. -0x1F0 13. -0x1EC 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1F0 12. -0x1EC 12. " [12] ,Port output bit 12" "Low,High" newline setclrfld.long 0x00 11. -0x1F0 11. -0x1EC 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x1F0 10. -0x1EC 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 9. -0x1F0 9. -0x1EC 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x1F0 8. -0x1EC 8. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 7. -0x1F0 7. -0x1EC 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x1F0 6. -0x1EC 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x1F0 5. -0x1EC 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 4. -0x1F0 4. -0x1EC 4. " [4] ,Port output bit 4" "Low,High" newline setclrfld.long 0x00 3. -0x1F0 3. -0x1EC 3. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 2. -0x1F0 2. -0x1EC 2. " [2] ,Port output bit 2" "Low,High" setclrfld.long 0x00 1. -0x1F0 1. -0x1EC 1. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 0. -0x1F0 0. -0x1EC 0. " [0] ,Port output bit 0" "Low,High" endif sif !cpuis("S6J35??H*") group.long 0x218++0x03 line.long 0x00 "POR3_SET/CLR,Port Output Set/Clear Register 3" sif cpuis("S6J342?F*") setclrfld.long 0x00 31. -0x1E8 31. -0x1E4 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 27. -0x1E8 27. -0x1E4 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 24. -0x1E8 24. -0x1E4 24. " [24] ,Port output bit 24" "Low,High" setclrfld.long 0x00 23. -0x1E8 23. -0x1E4 23. " [23] ,Port output bit 23" "Low,High" newline setclrfld.long 0x00 22. -0x1E8 22. -0x1E4 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1E8 21. -0x1E4 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 15. -0x1E8 15. -0x1E4 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1E8 14. -0x1E4 14. " [14] ,Port output bit 14" "Low,High" newline setclrfld.long 0x00 13. -0x1E8 13. -0x1E4 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 9. -0x1E8 9. -0x1E4 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 7. -0x1E8 7. -0x1E4 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 5. -0x1E8 5. -0x1E4 5. " [5] ,Port output bit 5" "Low,High" newline setclrfld.long 0x00 4. -0x1E8 4. -0x1E4 4. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 2. -0x1E8 2. -0x1E4 2. " [2] ,Port output bit 2" "Low,High" setclrfld.long 0x00 1. -0x1E8 1. -0x1E4 1. " [1] ,Port output bit 1" "Low,High" elif cpuis("S6J342?H*") setclrfld.long 0x00 31. -0x1E8 31. -0x1E4 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x1E8 30. -0x1E4 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 27. -0x1E8 27. -0x1E4 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 24. -0x1E8 24. -0x1E4 24. " [24] ,Port output bit 24" "Low,High" newline setclrfld.long 0x00 23. -0x1E8 23. -0x1E4 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1E8 22. -0x1E4 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1E8 21. -0x1E4 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 19. -0x1E8 19. -0x1E4 19. " [19] ,Port output bit 19" "Low,High" newline setclrfld.long 0x00 18. -0x1E8 18. -0x1E4 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x1E8 17. -0x1E4 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 15. -0x1E8 15. -0x1E4 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1E8 14. -0x1E4 14. " [14] ,Port output bit 14" "Low,High" newline setclrfld.long 0x00 13. -0x1E8 13. -0x1E4 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1E8 12. -0x1E4 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 9. -0x1E8 9. -0x1E4 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x1E8 8. -0x1E4 8. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 7. -0x1E8 7. -0x1E4 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x1E8 6. -0x1E4 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x1E8 5. -0x1E4 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 4. -0x1E8 4. -0x1E4 4. " [4] ,Port output bit 4" "Low,High" newline setclrfld.long 0x00 2. -0x1E8 2. -0x1E4 2. " [2] ,Port output bit 2" "Low,High" setclrfld.long 0x00 1. -0x1E8 1. -0x1E4 1. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 0. -0x1E8 0. -0x1E4 0. " [0] ,Port output bit 0" "Low,High" else setclrfld.long 0x00 31. -0x1E8 31. -0x1E4 31. " PO[31] ,Port output bit 31" "Low,High" setclrfld.long 0x00 30. -0x1E8 30. -0x1E4 30. " [30] ,Port output bit 30" "Low,High" setclrfld.long 0x00 29. -0x1E8 29. -0x1E4 29. " [29] ,Port output bit 29" "Low,High" setclrfld.long 0x00 28. -0x1E8 28. -0x1E4 28. " [28] ,Port output bit 28" "Low,High" newline setclrfld.long 0x00 27. -0x1E8 27. -0x1E4 27. " [27] ,Port output bit 27" "Low,High" setclrfld.long 0x00 26. -0x1E8 26. -0x1E4 26. " [26] ,Port output bit 26" "Low,High" setclrfld.long 0x00 25. -0x1E8 25. -0x1E4 25. " [25] ,Port output bit 25" "Low,High" setclrfld.long 0x00 24. -0x1E8 24. -0x1E4 24. " [24] ,Port output bit 24" "Low,High" newline setclrfld.long 0x00 23. -0x1E8 23. -0x1E4 23. " [23] ,Port output bit 23" "Low,High" setclrfld.long 0x00 22. -0x1E8 22. -0x1E4 22. " [22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1E8 21. -0x1E4 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x1E8 20. -0x1E4 20. " [20] ,Port output bit 20" "Low,High" newline setclrfld.long 0x00 19. -0x1E8 19. -0x1E4 19. " [19] ,Port output bit 19" "Low,High" setclrfld.long 0x00 18. -0x1E8 18. -0x1E4 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x1E8 17. -0x1E4 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x1E8 16. -0x1E4 16. " [16] ,Port output bit 16" "Low,High" newline setclrfld.long 0x00 15. -0x1E8 15. -0x1E4 15. " [15] ,Port output bit 15" "Low,High" setclrfld.long 0x00 14. -0x1E8 14. -0x1E4 14. " [14] ,Port output bit 14" "Low,High" setclrfld.long 0x00 13. -0x1E8 13. -0x1E4 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1E8 12. -0x1E4 12. " [12] ,Port output bit 12" "Low,High" newline setclrfld.long 0x00 11. -0x1E8 11. -0x1E4 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 10. -0x1E8 10. -0x1E4 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 9. -0x1E8 9. -0x1E4 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x1E8 8. -0x1E4 8. " [8] ,Port output bit 8" "Low,High" newline setclrfld.long 0x00 7. -0x1E8 7. -0x1E4 7. " [7] ,Port output bit 7" "Low,High" setclrfld.long 0x00 6. -0x1E8 6. -0x1E4 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x1E8 5. -0x1E4 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 4. -0x1E8 4. -0x1E4 4. " [4] ,Port output bit 4" "Low,High" newline setclrfld.long 0x00 3. -0x1E8 3. -0x1E4 3. " [3] ,Port output bit 3" "Low,High" setclrfld.long 0x00 2. -0x1E8 2. -0x1E4 2. " [2] ,Port output bit 2" "Low,High" setclrfld.long 0x00 1. -0x1E8 1. -0x1E4 1. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 0. -0x1E8 0. -0x1E4 0. " [0] ,Port output bit 0" "Low,High" endif endif sif !cpuis("S6J35??J*")&&!cpuis("S6J35??H*") group.long 0x220++0x03 line.long 0x00 "POR4_SET/CLR,Port Output Set/Clear Register 4" sif cpuis("S6J342?F*") setclrfld.long 0x00 22. -0x1E0 22. -0x1DC 22. " PO[22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 20. -0x1E0 20. -0x1DC 20. " [20] ,Port output bit 20" "Low,High" setclrfld.long 0x00 16. -0x1E0 16. -0x1DC 16. " [16] ,Port output bit 16" "Low,High" setclrfld.long 0x00 13. -0x1E0 13. -0x1DC 13. " [13] ,Port output bit 13" "Low,High" newline setclrfld.long 0x00 9. -0x1E0 9. -0x1DC 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 5. -0x1E0 5. -0x1DC 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 2. -0x1E0 2. -0x1DC 2. " [2] ,Port output bit 2" "Low,High" setclrfld.long 0x00 1. -0x1E0 1. -0x1DC 1. " [1] ,Port output bit 1" "Low,High" newline setclrfld.long 0x00 0. -0x1E0 0. -0x1DC 0. " [0] ,Port output bit 0" "Low,High" elif cpuis("S6J342?H*") setclrfld.long 0x00 22. -0x1E0 22. -0x1DC 22. " PO[22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1E0 21. -0x1DC 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x1E0 20. -0x1DC 20. " [20] ,Port output bit 20" "Low,High" setclrfld.long 0x00 18. -0x1E0 18. -0x1DC 18. " [18] ,Port output bit 18" "Low,High" newline setclrfld.long 0x00 17. -0x1E0 17. -0x1DC 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x1E0 16. -0x1DC 16. " [16] ,Port output bit 16" "Low,High" setclrfld.long 0x00 14. -0x1E0 14. -0x1DC 14. " [14] ,Port output bit 14" "Low,High" setclrfld.long 0x00 13. -0x1E0 13. -0x1DC 13. " [13] ,Port output bit 13" "Low,High" newline setclrfld.long 0x00 11. -0x1E0 11. -0x1DC 11. " [11] ,Port output bit 11" "Low,High" setclrfld.long 0x00 9. -0x1E0 9. -0x1DC 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x1E0 8. -0x1DC 8. " [8] ,Port output bit 8" "Low,High" setclrfld.long 0x00 7. -0x1E0 7. -0x1DC 7. " [7] ,Port output bit 7" "Low,High" newline setclrfld.long 0x00 6. -0x1E0 6. -0x1DC 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x1E0 5. -0x1DC 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 4. -0x1E0 4. -0x1DC 4. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 3. -0x1E0 3. -0x1DC 3. " [3] ,Port output bit 3" "Low,High" newline setclrfld.long 0x00 2. -0x1E0 2. -0x1DC 2. " [2] ,Port output bit 2" "Low,High" setclrfld.long 0x00 1. -0x1E0 1. -0x1DC 1. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 0. -0x1E0 0. -0x1DC 0. " [0] ,Port output bit 0" "Low,High" else setclrfld.long 0x00 22. -0x1E0 22. -0x1DC 22. " PO[22] ,Port output bit 22" "Low,High" setclrfld.long 0x00 21. -0x1E0 21. -0x1DC 21. " [21] ,Port output bit 21" "Low,High" setclrfld.long 0x00 20. -0x1E0 20. -0x1DC 20. " [20] ,Port output bit 20" "Low,High" setclrfld.long 0x00 19. -0x1E0 19. -0x1DC 19. " [19] ,Port output bit 19" "Low,High" newline setclrfld.long 0x00 18. -0x1E0 18. -0x1DC 18. " [18] ,Port output bit 18" "Low,High" setclrfld.long 0x00 17. -0x1E0 17. -0x1DC 17. " [17] ,Port output bit 17" "Low,High" setclrfld.long 0x00 16. -0x1E0 16. -0x1DC 16. " [16] ,Port output bit 16" "Low,High" setclrfld.long 0x00 15. -0x1E0 15. -0x1DC 15. " [15] ,Port output bit 15" "Low,High" newline setclrfld.long 0x00 14. -0x1E0 14. -0x1DC 14. " [14] ,Port output bit 14" "Low,High" setclrfld.long 0x00 13. -0x1E0 13. -0x1DC 13. " [13] ,Port output bit 13" "Low,High" setclrfld.long 0x00 12. -0x1E0 12. -0x1DC 12. " [12] ,Port output bit 12" "Low,High" setclrfld.long 0x00 11. -0x1E0 11. -0x1DC 11. " [11] ,Port output bit 11" "Low,High" newline setclrfld.long 0x00 10. -0x1E0 10. -0x1DC 10. " [10] ,Port output bit 10" "Low,High" setclrfld.long 0x00 9. -0x1E0 9. -0x1DC 9. " [9] ,Port output bit 9" "Low,High" setclrfld.long 0x00 8. -0x1E0 8. -0x1DC 8. " [8] ,Port output bit 8" "Low,High" setclrfld.long 0x00 7. -0x1E0 7. -0x1DC 7. " [7] ,Port output bit 7" "Low,High" newline setclrfld.long 0x00 6. -0x1E0 6. -0x1DC 6. " [6] ,Port output bit 6" "Low,High" setclrfld.long 0x00 5. -0x1E0 5. -0x1DC 5. " [5] ,Port output bit 5" "Low,High" setclrfld.long 0x00 4. -0x1E0 4. -0x1DC 4. " [4] ,Port output bit 4" "Low,High" setclrfld.long 0x00 3. -0x1E0 3. -0x1DC 3. " [3] ,Port output bit 3" "Low,High" newline setclrfld.long 0x00 2. -0x1E0 2. -0x1DC 2. " [2] ,Port output bit 2" "Low,High" setclrfld.long 0x00 1. -0x1E0 1. -0x1DC 1. " [1] ,Port output bit 1" "Low,High" setclrfld.long 0x00 0. -0x1E0 0. -0x1DC 0. " [0] ,Port output bit 0" "Low,High" endif endif newline group.long 0x400++0x03 line.long 0x00 "PORTEN,Port Input Enable Register" bitfld.long 0x00 0. " GPORTEN ,GPIO port enable bit" "Disabled,Enabled" rgroup.long 0x300++0x0B line.long 0x00 "PIDR0,Port Input Data Register 0" sif cpuis("S6J342?F*") bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x00 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port input data bit 28" "Low,High" bitfld.long 0x00 27. " [27] ,Port input data bit 27" "Low,High" newline bitfld.long 0x00 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port input data bit 20" "Low,High" bitfld.long 0x00 16. " [16] ,Port input data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x00 10. " [10] ,Port input data bit 10" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" elif cpuis("S6J342?H*") bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port input data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x00 24. " [24] ,Port input data bit 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port input data bit 22" "Low,High" newline bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port input data bit 20" "Low,High" bitfld.long 0x00 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port input data bit 18" "Low,High" newline bitfld.long 0x00 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port input data bit 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" newline bitfld.long 0x00 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x00 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 3. " [3] ,Port input data bit 3" "Low,High" newline bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port input data bit 0" "Low,High" else bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port input data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port input data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port input data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port input data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port input data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port input data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port input data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port input data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port input data bit 0" "Low,High" endif line.long 0x04 "PIDR1,Port Input Data Register 1" sif cpuis("S6J342?F*") bitfld.long 0x04 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x04 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x04 28. " [28] ,Port input data bit 28" "Low,High" bitfld.long 0x04 26. " [26] ,Port input data bit 26" "Low,High" newline bitfld.long 0x04 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x04 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x04 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x04 17. " [17] ,Port input data bit 17" "Low,High" newline bitfld.long 0x04 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x04 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x04 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x04 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x04 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x04 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x04 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x04 3. " [3] ,Port input data bit 3" "Low,High" newline bitfld.long 0x04 0. " [0] ,Port input data bit 0" "Low,High" elif cpuis("S6J342?H*") bitfld.long 0x04 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x04 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x04 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x04 28. " [28] ,Port input data bit 28" "Low,High" newline bitfld.long 0x04 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x04 26. " [26] ,Port input data bit 26" "Low,High" bitfld.long 0x04 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x04 22. " [22] ,Port input data bit 22" "Low,High" newline bitfld.long 0x04 20. " [20] ,Port input data bit 20" "Low,High" bitfld.long 0x04 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x04 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x04 17. " [17] ,Port input data bit 17" "Low,High" newline bitfld.long 0x04 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x04 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x04 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x04 12. " [12] ,Port input data bit 12" "Low,High" newline bitfld.long 0x04 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x04 8. " [8] ,Port input data bit 8" "Low,High" bitfld.long 0x04 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x04 6. " [6] ,Port input data bit 6" "Low,High" newline bitfld.long 0x04 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x04 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x04 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x04 0. " [0] ,Port input data bit 0" "Low,High" else bitfld.long 0x04 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x04 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x04 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x04 28. " [28] ,Port input data bit 28" "Low,High" newline bitfld.long 0x04 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x04 26. " [26] ,Port input data bit 26" "Low,High" bitfld.long 0x04 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x04 24. " [24] ,Port input data bit 24" "Low,High" newline bitfld.long 0x04 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x04 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x04 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x04 20. " [20] ,Port input data bit 20" "Low,High" newline bitfld.long 0x04 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x04 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x04 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x04 16. " [16] ,Port input data bit 16" "Low,High" newline bitfld.long 0x04 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x04 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x04 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x04 12. " [12] ,Port input data bit 12" "Low,High" newline bitfld.long 0x04 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x04 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x04 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x04 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x04 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x04 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x04 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x04 4. " [4] ,Port input data bit 4" "Low,High" newline bitfld.long 0x04 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x04 2. " [2] ,Port input data bit 2" "Low,High" bitfld.long 0x04 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x04 0. " [0] ,Port input data bit 0" "Low,High" endif line.long 0x08 "PIDR2,Port Input Data Register 2" sif cpuis("S6J342?F*") bitfld.long 0x08 29. " PID[29] ,Port input data bit 29" "Low,High" bitfld.long 0x08 28. " [28] ,Port input data bit 28" "Low,High" bitfld.long 0x08 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x08 26. " [26] ,Port input data bit 26" "Low,High" newline bitfld.long 0x08 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x08 24. " [24] ,Port input data bit 24" "Low,High" bitfld.long 0x08 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x08 22. " [22] ,Port input data bit 22" "Low,High" newline bitfld.long 0x08 20. " [20] ,Port input data bit 20" "Low,High" bitfld.long 0x08 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x08 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x08 13. " [13] ,Port input data bit 13" "Low,High" newline bitfld.long 0x08 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x08 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x08 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x08 5. " [5] ,Port input data bit 5" "Low,High" newline bitfld.long 0x08 4. " [4] ,Port input data bit 4" "Low,High" bitfld.long 0x08 2. " [2] ,Port input data bit 2" "Low,High" elif cpuis("S6J342?H*") bitfld.long 0x08 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x08 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x08 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x08 28. " [28] ,Port input data bit 28" "Low,High" newline bitfld.long 0x08 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x08 26. " [26] ,Port input data bit 26" "Low,High" bitfld.long 0x08 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x08 24. " [24] ,Port input data bit 24" "Low,High" newline bitfld.long 0x08 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x08 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x08 20. " [20] ,Port input data bit 20" "Low,High" bitfld.long 0x08 19. " [19] ,Port input data bit 19" "Low,High" newline bitfld.long 0x08 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x08 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x08 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x08 13. " [13] ,Port input data bit 13" "Low,High" newline bitfld.long 0x08 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x08 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x08 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x08 9. " [9] ,Port input data bit 9" "Low,High" newline bitfld.long 0x08 8. " [8] ,Port input data bit 8" "Low,High" bitfld.long 0x08 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x08 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x08 5. " [5] ,Port input data bit 5" "Low,High" newline bitfld.long 0x08 4. " [4] ,Port input data bit 4" "Low,High" bitfld.long 0x08 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x08 2. " [2] ,Port input data bit 2" "Low,High" elif cpuis("S6J35??J*")||cpuis("S6J35??H*") bitfld.long 0x08 29. " PID[29] ,Port input data bit 29" "Low,High" bitfld.long 0x08 28. " [28] ,Port input data bit 28" "Low,High" newline bitfld.long 0x08 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x08 26. " [26] ,Port input data bit 26" "Low,High" bitfld.long 0x08 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x08 24. " [24] ,Port input data bit 24" "Low,High" newline bitfld.long 0x08 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x08 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x08 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x08 20. " [20] ,Port input data bit 20" "Low,High" newline bitfld.long 0x08 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x08 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x08 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x08 16. " [16] ,Port input data bit 16" "Low,High" newline bitfld.long 0x08 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x08 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x08 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x08 12. " [12] ,Port input data bit 12" "Low,High" newline bitfld.long 0x08 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x08 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x08 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x08 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x08 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x08 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x08 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x08 4. " [4] ,Port input data bit 4" "Low,High" newline bitfld.long 0x08 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x08 2. " [2] ,Port input data bit 2" "Low,High" bitfld.long 0x08 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x08 0. " [0] ,Port input data bit 0" "Low,High" else bitfld.long 0x08 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x08 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x08 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x08 28. " [28] ,Port input data bit 28" "Low,High" newline bitfld.long 0x08 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x08 26. " [26] ,Port input data bit 26" "Low,High" bitfld.long 0x08 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x08 24. " [24] ,Port input data bit 24" "Low,High" newline bitfld.long 0x08 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x08 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x08 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x08 20. " [20] ,Port input data bit 20" "Low,High" newline bitfld.long 0x08 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x08 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x08 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x08 16. " [16] ,Port input data bit 16" "Low,High" newline bitfld.long 0x08 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x08 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x08 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x08 12. " [12] ,Port input data bit 12" "Low,High" newline bitfld.long 0x08 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x08 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x08 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x08 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x08 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x08 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x08 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x08 4. " [4] ,Port input data bit 4" "Low,High" newline bitfld.long 0x08 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x08 2. " [2] ,Port input data bit 2" "Low,High" bitfld.long 0x08 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x08 0. " [0] ,Port input data bit 0" "Low,High" endif sif !cpuis("S6J35??H*") group.long 0x30C++0x03 line.long 0x00 "PIDR3,Port Input Data Register 3" sif cpuis("S6J342?F*") bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x00 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x00 24. " [24] ,Port input data bit 24" "Low,High" bitfld.long 0x00 23. " [23] ,Port input data bit 23" "Low,High" newline bitfld.long 0x00 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port input data bit 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" newline bitfld.long 0x00 4. " [4] ,Port input data bit 4" "Low,High" bitfld.long 0x00 2. " [2] ,Port input data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" elif cpuis("S6J342?H*") bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x00 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x00 24. " [24] ,Port input data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 19. " [19] ,Port input data bit 19" "Low,High" newline bitfld.long 0x00 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x00 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port input data bit 14" "Low,High" newline bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port input data bit 4" "Low,High" newline bitfld.long 0x00 2. " [2] ,Port input data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port input data bit 0" "Low,High" else bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High" bitfld.long 0x00 30. " [30] ,Port input data bit 30" "Low,High" bitfld.long 0x00 29. " [29] ,Port input data bit 29" "Low,High" bitfld.long 0x00 28. " [28] ,Port input data bit 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,Port input data bit 27" "Low,High" bitfld.long 0x00 26. " [26] ,Port input data bit 26" "Low,High" bitfld.long 0x00 25. " [25] ,Port input data bit 25" "Low,High" bitfld.long 0x00 24. " [24] ,Port input data bit 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,Port input data bit 23" "Low,High" bitfld.long 0x00 22. " [22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port input data bit 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,Port input data bit 19" "Low,High" bitfld.long 0x00 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port input data bit 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,Port input data bit 15" "Low,High" bitfld.long 0x00 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port input data bit 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x00 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port input data bit 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" bitfld.long 0x00 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port input data bit 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,Port input data bit 3" "Low,High" bitfld.long 0x00 2. " [2] ,Port input data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port input data bit 0" "Low,High" endif endif sif !cpuis("S6J35??J*")&&!cpuis("S6J35??H*") group.long 0x310++0x03 line.long 0x00 "PIDR4,Port Input Data Register 4" sif cpuis("S6J342?F*") bitfld.long 0x00 22. " PID[22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 20. " [20] ,Port input data bit 20" "Low,High" bitfld.long 0x00 16. " [16] ,Port input data bit 16" "Low,High" bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" newline bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 2. " [2] ,Port input data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" newline bitfld.long 0x00 0. " [0] ,Port input data bit 0" "Low,High" elif cpuis("S6J342?H*") bitfld.long 0x00 22. " PID[22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port input data bit 20" "Low,High" bitfld.long 0x00 18. " [18] ,Port input data bit 18" "Low,High" newline bitfld.long 0x00 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port input data bit 16" "Low,High" bitfld.long 0x00 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" newline bitfld.long 0x00 11. " [11] ,Port input data bit 11" "Low,High" bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port input data bit 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" newline bitfld.long 0x00 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port input data bit 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port input data bit 3" "Low,High" newline bitfld.long 0x00 2. " [2] ,Port input data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port input data bit 0" "Low,High" else bitfld.long 0x00 22. " PID[22] ,Port input data bit 22" "Low,High" bitfld.long 0x00 21. " [21] ,Port input data bit 21" "Low,High" bitfld.long 0x00 20. " [20] ,Port input data bit 20" "Low,High" bitfld.long 0x00 19. " [19] ,Port input data bit 19" "Low,High" newline bitfld.long 0x00 18. " [18] ,Port input data bit 18" "Low,High" bitfld.long 0x00 17. " [17] ,Port input data bit 17" "Low,High" bitfld.long 0x00 16. " [16] ,Port input data bit 16" "Low,High" bitfld.long 0x00 15. " [15] ,Port input data bit 15" "Low,High" newline bitfld.long 0x00 14. " [14] ,Port input data bit 14" "Low,High" bitfld.long 0x00 13. " [13] ,Port input data bit 13" "Low,High" bitfld.long 0x00 12. " [12] ,Port input data bit 12" "Low,High" bitfld.long 0x00 11. " [11] ,Port input data bit 11" "Low,High" newline bitfld.long 0x00 10. " [10] ,Port input data bit 10" "Low,High" bitfld.long 0x00 9. " [9] ,Port input data bit 9" "Low,High" bitfld.long 0x00 8. " [8] ,Port input data bit 8" "Low,High" bitfld.long 0x00 7. " [7] ,Port input data bit 7" "Low,High" newline bitfld.long 0x00 6. " [6] ,Port input data bit 6" "Low,High" bitfld.long 0x00 5. " [5] ,Port input data bit 5" "Low,High" bitfld.long 0x00 4. " [4] ,Port input data bit 4" "Low,High" bitfld.long 0x00 3. " [3] ,Port input data bit 3" "Low,High" newline bitfld.long 0x00 2. " [2] ,Port input data bit 2" "Low,High" bitfld.long 0x00 1. " [1] ,Port input data bit 1" "Low,High" bitfld.long 0x00 0. " [0] ,Port input data bit 0" "Low,High" endif endif wgroup.long 0x404++0x03 line.long 0x00 "KEYCDR,GPIO Key Code Register" bitfld.long 0x00 30.--31. " KEY ,Key code bits" "1,2,3,4" bitfld.long 0x00 28.--29. " SIZE ,Access size bits" "Byte,Half-word,Word,?..." hexmask.long.word 0x00 0.--14. 0x01 " RADR ,Port address bits" width 0x0B tree.end tree "PPC" base ad:0xB4740000 width 10. sif !cpuis("S6J342?F*") group.word 0x00++0x01 line.word 0x00 "PCFGR000,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,,SOUT2,,,,TIOA63" endif group.word 0x02++0x01 line.word 0x00 "PCFGR001,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,,SCS30,SCS20,,,,TIOA54" sif !cpuis("S6J342?F*") sif !cpuis("S6J342?H*") group.word 0x04++0x01 line.word 0x00 "PCFGR002,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,TIOA0,,SCS21,?..." endif group.word 0x06++0x01 line.word 0x00 "PCFGR003,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,,SCS22,?..." sif !cpuis("S6J342?H*") group.word 0x08++0x01 line.word 0x00 "PCFGR004,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,TIOA1,,SCS23,?..." endif endif group.word 0x0A++0x05 line.word 0x00 "PCFGR005,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,,SCS83,,,,,TIOA55" line.word 0x02 "PCFGR006,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD06,,SOUT3,,,,SDA3,?..." line.word 0x04 "PCFGR007,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "POD07,,SCK3,SCK12,,,ACL3,?..." sif !cpuis("S6J342?F*") group.word 0x010++0x03 line.word 0x00 "PCFGR008,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,TIOA0,SCS30,SCS120,?..." line.word 0x02 "PCFGR009,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD09,TIOA1,?..." endif group.word 0x014++0x01 line.word 0x00 "PCFGR010,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,TIOA2,SOUT8,,,,SDA8,?..." sif !cpuis("S6J342?F*")&&!cpuis("S6J342?H*") group.word 0x016++0x01 line.word 0x00 "PCFGR011,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,TIOA2,?..." endif group.word 0x018++0x03 line.word 0x00 "PCFGR012,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,TIOA3,SCK8,,OUT5,,SCL8,?..." line.word 0x02 "PCFGR013,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD13,TIOA4,SCS80,,OUT16,?..." sif !cpuis("S6J342?F*")&&!cpuis("S6J342?H*") group.word 0x01C++0x01 line.word 0x00 "PCFGR014,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,TIOA3,,SOUT12,?..." endif group.word 0x01E++0x03 line.word 0x00 "PCFGR015,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,TIOA5,SCS81,,OUT17,TX3,?..." line.word 0x02 "PCFGR016,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD16,TIOA6,SCS82,,OUT18,?..." sif !cpuis("S6J342?F*") group.word 0x22++0x05 line.word 0x00 "PCFGR017,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,TIOA7,SCS83,,OUT19,?..." line.word 0x02 "PCFGR018,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD18,TIOA8,,,OUT20,?..." line.word 0x04 "PCFGR019,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "POD19,,,,OUT21,?..." endif group.word 0x28++0x01 line.word 0x00 "PCFGR020,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,SOUT0,,,,SDA0,?..." group.word 0x2A++0x01 line.word 0x00 "PCFGR021,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,SCK0,SCK4,OUT2,,SCL0,?..." group.word 0x2C++0x01 line.word 0x00 "PCFGR022,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,,,,OUT5,?..." sif !cpuis("S6J342?F*") group.word 0x2E++0x03 line.word 0x00 "PCFGR023,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,,SCS00,?..." line.word 0x02 "PCFGR024,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD24,,,SOUT4,?..." sif !cpuis("S6J342?H*") group.word 0x032++0x03 line.word 0x00 "PCFGR025,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,,,SCS40,?..." line.word 0x02 "PCFGR026,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD26,,,SCS41,?..." endif endif group.word 0x036++0x05 line.word 0x00 "PCFGR027,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,TIOA4,SCS00,SCS42,?..." line.word 0x02 "PCFGR028,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD28,,,,OUT0,?..." line.word 0x04 "PCFGR029,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "POD29,,SOUT1,,OUT1,,SDA1,TIOA30" sif !cpuis("S6J342?F*") group.word 0x03C++0x01 line.word 0x00 "PCFGR030,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,,,SCS43,OUT2,?..." endif group.word 0x03E++0x03 line.word 0x00 "PCFGR031,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,,SCS10,,OUT3,,,TIOA31" line.word 0x02 "PCFGR100,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD00,,SCK1,,OUT4,,SCL1,?..." sif !cpuis("S6J342?F*") group.word 0x42++0x01 line.word 0x00 "PCFGR101,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,,,,OUT5,,,TIOA56" sif !cpuis("S6J342?H*") group.word 0x44++0x01 line.word 0x00 "PCFGR102,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,,,Media LB" bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,,,,,,,TIOA57" endif endif group.word 0x46++0x01 line.word 0x00 "PCFGR103,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,,,OUT16,?..." sif !cpuis("S6J342?F*")&&!cpuis("S6J342?H*") group.word 0x48++0x01 line.word 0x00 "PCFGR104,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,?..." endif group.word 0x4A++0x9 line.word 0x00 "PCFGR105,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,TIOA9,,SCS110,OUT17,?..." line.word 0x02 "PCFGR106,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD06,,,,OUT18,TX1,?..." line.word 0x04 "PCFGR107,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "POD07,TIOA10,,,OUT19,,,TOT0" line.word 0x06 "PCFGR108,Port Setting Register" rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x06 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x06 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x06 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x06 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "POD08,TIOA11,SOUT11,,OUT20,,SDA11,?..." line.word 0x08 "PCFGR109,Port Setting Register" rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x08 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x08 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x08 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x08 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "POD09,TIOA12,SCK11,,OUT21,,SCL11,TOT1" sif !cpuis("S6J342?F*")&&!cpuis("S6J342?H*") group.word 0x054++0x03 line.word 0x00 "PCFGR110,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,,SCS110,?..." line.word 0x02 "PCFGR111,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD11,?..." endif group.word 0x058++0x01 line.word 0x00 "PCFGR112,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,TIOA13,SOUT12,,,,SDA12,?..." sif !cpuis("S6J342?F*") group.word 0x05A++0x01 line.word 0x00 "PCFGR113,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,TIOA5,SCK12,SOUT11,,,SCL12,TOT2" endif group.word 0x05C++0x01 line.word 0x00 "PCFGR114,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,TIOA6,SCS120,,,,,TIOA32" sif !cpuis("S6J342?F*") group.word 0x05E++0x01 line.word 0x00 "PCFGR115,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,,,,,,,TOT3" sif !cpuis("S6J342?H*") group.word 0x60++0x01 line.word 0x00 "PCFGR116,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,?..." endif endif group.word 0x62++0x01 line.word 0x00 "PCFGR117,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,,,SCK12,,,SCL12,?..." sif !cpuis("S6J342?F*") group.word 0x64++0x01 line.word 0x00 "PCFGR118,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,,,,,,,TOT16" endif group.word 0x66++0x01 line.word 0x00 "PCFGR119,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,,SCS60,?..." sif !cpuis("S6J342?F*") group.word 0x68++0x01 line.word 0x00 "PCFGR120,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,SCS61,,,,,TOT17" sif !cpuis("S6J342?H*") group.word 0x6A++0x01 line.word 0x00 "PCFGR121,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,TIOA14,SCS130,?..." endif endif group.word 0x6C++0x03 line.word 0x00 "PCFGR122,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,TIOA11,SCS62,?..." line.word 0x02 "PCFGR123,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD23,TIOA12,SCS63,,,,,TIOA34" sif !cpuis("S6J342?F*")&&!cpuis("S6J342?H*") group.word 0x70++0x03 line.word 0x00 "PCFGR124,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,TIOA15,?..." line.word 0x02 "PCFGR125,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD25,TIOA16,SOUT13,,,,SDA13,?..." endif group.word 0x74++0x01 line.word 0x00 "PCFGR126,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,,SCK13,,,,SCL13,TIOA35" sif !cpuis("S6J342?F*") group.word 0x76++0x01 line.word 0x00 "PCFGR127,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,?..." endif group.word 0x78++0x01 line.word 0x00 "PCFGR128,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,?..." sif !cpuis("S6J342?F*") group.word 0x7A++0x01 line.word 0x00 "PCFGR129,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,?..." endif group.word 0x7C++0x03 line.word 0x00 "PCFGR130,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,?..." line.word 0x02 "PCFGR131,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD31,,SOUT6,,,,SDA6,TIOA37" sif !cpuis("S6J342?F*")&&!cpuis("S6J342?H*") group.word 0x80++0x03 line.word 0x00 "PCFGR200,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,TIOA17,?..." line.word 0x02 "PCFGR201,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD01,TIOA18,?..." endif group.word 0x84++0x01 line.word 0x00 "PCFGR202,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,,SKC6,,,,SCL6,TIOA36" sif !cpuis("S6J342?F*") group.word 0x86++0x01 line.word 0x00 "PCFGR203,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,30mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,?..." endif group.word 0x88++0x03 line.word 0x00 "PCFGR204,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,,,,,TX4,?..." line.word 0x02 "PCFGR205,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD05,?..." sif !cpuis("S6J342?F*") group.word 0x8C++0x01 line.word 0x00 "PCFGR206,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,SCS43,?..." endif group.word 0x8E++0x01 line.word 0x00 "PCFGR207,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,SCK4,SCL4,,,,TIOA38" sif !cpuis("S6J342?F*") group.word 0x90++0x01 line.word 0x00 "PCFGR208,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,TIOA19,SCS42,?..." endif group.word 0x92++0x01 line.word 0x00 "PCFGR209,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,5mA,?..." newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,TIOA20,SOUT4,SDA4,?..." sif !cpuis("S6J342?F*") group.word 0x94++0x01 line.word 0x00 "PCFGR210,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,TIOA21,?..." endif group.word 0x96++0x01 line.word 0x00 "PCFGR211,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,TIOA22,SCS40,?..." sif !cpuis("S6J342?F*") group.word 0x98++0x01 line.word 0x00 "PCFGR212,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,TIOA13,SCS41,SCS50,?..." endif group.word 0x9A++0x05 line.word 0x00 "PCFGR213,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,TIOA14,,,,,,TIOA41" line.word 0x02 "PCFGR214,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD14,TIOA15,,SOUT5,?..." line.word 0x04 "PCFGR215,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "POD15,TIOA16,,SCK5,?..." sif !cpuis("S6J342?F*") sif !cpuis("S6J342?H*") group.word 0xA0++0x03 line.word 0x00 "PCFGR216,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,,,,,,,TIOA58" line.word 0x02 "PCFGR217,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD17,?..." endif group.word 0xA4++0x03 line.word 0x00 "PCFGR218,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,?..." line.word 0x02 "PCFGR219,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD19,?..." endif group.word 0xA8++0x01 line.word 0x00 "PCFGR220,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,SCS53,,,TX2,?..." sif !cpuis("S6J342?F*")&&!cpuis("S6J342?H*") group.word 0xAA++0x01 line.word 0x00 "PCFGR221,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,SCS52,?..." endif group.word 0xAC++0x0F line.word 0x00 "PCFGR222,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,,,,,,,TIOA39" line.word 0x02 "PCFGR223,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD23,SCS51,,,,,,TOT0" line.word 0x04 "PCFGR224,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "POD24,,SCS50,,,,,TIOA40" line.word 0x06 "PCFGR225,Port Setting Register" rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x06 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x06 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x06 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x06 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "POD25,,SOUT5,,,,SDA5,?..." line.word 0x08 "PCFGR226,Port Setting Register" rbitfld.word 0x08 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x08 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x08 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x08 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x08 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x08 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x08 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x08 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x08 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x08 0.--2. " POF ,Port output function selection bit" "POD26,TIOA17,SCK5,,,,SCL5,?..." line.word 0x0A "PCFGR227,Port Setting Register" rbitfld.word 0x0A 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x0A 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x0A 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x0A 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x0A 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x0A 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x0A 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x0A 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x0A 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x0A 0.--2. " POF ,Port output function selection bit" "POD27,TIOA23,SCK10,,,,SCL10,TOT1" line.word 0x0C "PCFGR228,Port Setting Register" rbitfld.word 0x0C 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x0C 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x0C 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x0C 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x0C 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x0C 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x0C 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x0C 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x0C 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x0C 0.--2. " POF ,Port output function selection bit" "POD28,TIOA24,SOUT10,,,TX0,SDA10,?..." line.word 0x0E "PCFGR229,Port Setting Register" rbitfld.word 0x0E 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x0E 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x0E 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x0E 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x0E 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x0E 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x0E 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x0E 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x0E 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x0E 0.--2. " POF ,Port output function selection bit" "POD29,TIOA25,,,OUT0,,,TOT2" sif !cpuis("S6J342?F*") group.word 0xB0++0x03 line.word 0x00 "PCFGR230,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,TIOA26,SCS103,,OUT1,?..." line.word 0x02 "PCFGR231,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD31,TIOA27,SCS102,,OUT2,?..." endif sif !cpuis("S6J342?F*") group.word 0xC0++0x01 line.word 0x00 "PCFGR300,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,TIOA28,SCS101,,OUT3,?..." endif group.word 0xC2++0x03 line.word 0x00 "PCFGR301,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,TIOA18,SCS100,,OUT4,DBG_TRACEDATA7,,TIOA43" line.word 0x02 "PCFGR302,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD02,TIOA19,,SCS102,ADG_TRACEDATA6,,TOT3,TIOA43" sif !cpuis("S6J342?F*")&&!cpuis("S6J342?H*") group.word 0xC6++0x01 line.word 0x00 "PCFGR303,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,?..." endif group.word 0xC8++0x03 line.word 0x00 "PCFGR304,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,TIOA20,,SCS101,DBG_TRACEDATA5,?..." line.word 0x02 "PCFGR305,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD05,TIOA29,,SCS100,DBG_TRACEDATA4,,,TOT16" sif !cpuis("S6J342?F*") group.word 0xCC++0x01 line.word 0x00 "PCFGR306,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,SCS73,,,TX0,?..." endif group.word 0xCE++0x01 line.word 0x00 "PCFGR307,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,SCS72,,DBG_TRACEDATA3,?..." sif !cpuis("S6J342?F*") group.word 0xD0++0x01 line.word 0x00 "PCFGR308,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,TIOA28,?..." endif group.word 0xD2++0x01 line.word 0x00 "PCFGR309,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,TIOA29,,,DBG_TRACEDATA2,,TOT17,TIOA44" sif !cpuis("S6J342?F*") sif !cpuis("S6J342?H*") group.word 0xD4++0x01 line.word 0x00 "PCFGR310,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,,,,,,,TIOA59" group.word 0xD6++0x01 line.word 0x00 "PCFGR311,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,?..." endif group.word 0xD8++0x01 line.word 0x00 "PCFGR312,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,,SCS71,?..." endif group.word 0xDA++0x05 line.word 0x00 "PCFGR313,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,SOUT7,SDA7,DBG_TRACEDATA1,?..." line.word 0x02 "PCFGR314,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD14,TIOA7,SCK7,SCL7,DBG_TRACEDATA0,TX8,?..." line.word 0x04 "PCFGR315,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "POD15,TIOA8,SCS70,,TRACECTL,?..." sif !cpuis("S6J342?F*") sif !cpuis("S6J342?H*") group.word 0xE0++0x01 line.word 0x00 "PCFGR316,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,TIOA21,?..." endif group.word 0xE2++0x05 line.word 0x00 "PCFGR317,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,TIOA9,,,,TX1,?..." line.word 0x02 "PCFGR318,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD18,TIOA10,?..." line.word 0x04 "PCFGR319,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "POD19,,,,,,,TIOA60" sif !cpuis("S6J342?H*") group.word 0xE8++0x01 line.word 0x00 "PCFGR320,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,,,PWUTRG0,?..." endif endif group.word 0xEA++0x07 line.word 0x00 "PCFGR321,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,,,PWUTRG1,TRACECLK,,TIOA45" line.word 0x02 "PCFGR322,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "TDO,POD22,?..." line.word 0x04 "PCFGR323,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "TDI,POD23,?..." line.word 0x06 "PCFGR324,Port Setting Register" rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x06 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x06 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x06 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "TRST,POD24,?..." sif !cpuis("S6J342?F*")&&!cpuis("S6J342?H*") group.word 0xF2++0x03 line.word 0x00 "PCFGR325,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,,,,,,,TIOA61" line.word 0x02 "PCFGR326,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD26,?..." endif group.word 0xF6++0x01 line.word 0x00 "PCFGR327,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,,,SCK6,WOT,?..." sif !cpuis("S6J342?F*") sif !cpuis("S6J342?H*") group.word 0xF8++0x03 line.word 0x00 "PCFGR328,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,,,SOUT6,?..." line.word 0x02 "PCFGR329,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD29,?..." endif group.word 0xFC++0x01 line.word 0x00 "PCFGR330,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,,,SCS60,,,,TIOA62" endif group.word 0xFE++0x07 line.word 0x00 "PCFGR331,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,,,SCS60,?..." line.word 0x02 "PCFGR400,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD00,,,SCS61,?..." line.word 0x04 "PCFGR401,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "POD01,,,SCS62,SCK9,TX1,SCL9,TIOA46" line.word 0x06 "PCFGR402,Port Setting Register" rbitfld.word 0x06 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x06 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x06 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x06 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x06 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x06 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x06 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x06 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x06 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x06 0.--2. " POF ,Port output function selection bit" "POD02,,SCS90,SCS63,SOUT9,,SDA9,TIOA47" sif !cpuis("S6J342?F*") group.word 0x0106++0x03 line.word 0x00 "PCFGR403,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,,,DBG_TRACEDATA0,?..." line.word 0x02 "PCFGR404,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD04,,,SCS90,DBG_TRACEDATA1,?..." endif group.word 0x010A++0x01 line.word 0x00 "PCFGR405,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,,,,DBG_TRACEDATA2,,,TIOA48" sif !cpuis("S6J342?F*") group.word 0x010C++0x05 line.word 0x00 "PCFGR406,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,SOUT9,SDA9,DBG_TRACEDATA3,TX2,,TIOA49" line.word 0x02 "PCFGR407,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,TTL,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD07,,SCK9,SCK7,DBG_TRACEDATA4,,SCL9,?..." line.word 0x04 "PCFGR408,Port Setting Register" rbitfld.word 0x04 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x04 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x04 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x04 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x04 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x04 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x04 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x04 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x04 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x04 0.--2. " POF ,Port output function selection bit" "POD08,,,,DBG_TRACEDATA5,?..." endif group.word 0x0112++0x01 line.word 0x00 "PCFGR409,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,TIOA24,SOUT2,SDA2,DBG_TRACEDATA6,,,TIOA50" sif !cpuis("S6J342?F*") sif !cpuis("S6J342?H*") group.word 0x0114++0x01 line.word 0x00 "PCFGR410,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,,,SCS70,,,,TIOA51" endif group.word 0x0116++0x01 line.word 0x00 "PCFGR411,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,,SCK2,SCS71,DBG_TRACEDATA7,,SCL2,?..." sif !cpuis("S6J342?H*") group.word 0x0118++0x01 line.word 0x00 "PCFGR412,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,TIOA25,,SCS72,?..." endif endif group.word 0x011A++0x01 line.word 0x00 "PCFGR413,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,SCS20,SCS73,?..." sif !cpuis("S6J342?F*") group.word 0x011C++0x01 line.word 0x00 "PCFGR414,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,,,SCS21,?..." sif !cpuis("S6J342?H*") group.word 0x011E++0x01 line.word 0x00 "PCFGR415,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,TIOA26,?..." endif endif group.word 0x0120++0x01 line.word 0x00 "PCFGR416,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,TIOA22,,,,,,TIOA52" sif !cpuis("S6J342?F*") group.word 0x0122++0x03 line.word 0x00 "PCFGR417,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,TIOA23,,SOUT7,,,,TIOA53" line.word 0x02 "PCFGR418,Port Setting Register" rbitfld.word 0x02 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x02 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x02 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x02 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x02 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x02 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x02 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x02 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x02 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x02 0.--2. " POF ,Port output function selection bit" "POD18,,,SCS22,?..." sif !cpuis("S6J342?H*") group.word 0x0126++0x01 line.word 0x00 "PCFGR419,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,TIOA27,,SCS23,?..." endif endif group.word 0x0128++0x01 line.word 0x00 "PCFGR420,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,,SCK2,TRACECLK,,,SCL2" sif !cpuis("S6J342?F*") group.word 0x012A++0x01 line.word 0x00 "PCFGR421,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,,,TRACECTL,?..." endif group.word 0x012C++0x01 line.word 0x00 "PCFGR422,Port Setting Register" rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled" rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High" rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High" bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled" newline bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..." bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled" bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "1mA,2mA,,5mA" newline bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled" bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,,,,CLK_CLKO,,,TIOA33" newline group.long 0x400++0x03 line.long 0x00 "KEYCDR,PPC Key Code Register" bitfld.long 0x00 30.--31. " KEY ,Key code bits" "1st,2nd,3rd,4th" bitfld.long 0x00 28.--29. " SIZE ,Access size bits" "Byte,Half-word,Word,?..." hexmask.long.word 0x00 0.--14. 0x01 " RADR ,Port address bits" width 0x0B tree.end tree "RIC" base ad:0xB4748000 width 10. group.word 0x04++0x07 line.word 0x00 "RESIN2,SCL0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x02 "RESIN3,SDA0 Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x04 "RESIN4,MFS0_TRIGGER Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." line.word 0x06 "RESIN5,SCS0 Resource Input Setting Register" bitfld.word 0x06 0.--3. " PORTSEL ,Resource selection bit" "P023,P027,?..." group.word 0x12++0x05 line.word 0x00 "RESIN9,SCL1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x02 "RESIN10,SDA1 Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x04 "RESIN11,MFS1_TRIGGER Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." group.word 0x1C++0x0B line.word 0x00 "RESIN14,SIN2 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P408,P421,P416,?..." line.word 0x02 "RESIN15,SCK2 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P411,P420,?..." line.word 0x04 "RESIN16,SCL2 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." bitfld.word 0x04 8.--11. " PORTSEL ,Resource selection bit" "P411,P420,?..." line.word 0x06 "RESIN17,SDA2 Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x08 "RESIN18,MFS2_TRIGGER Resource Input Setting Register" bitfld.word 0x08 8.--11. " PORTSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." line.word 0x0A "RESIN19,SCS20 Resource Input Setting Register" bitfld.word 0x0A 8.--11. " PORTSEL ,Resource selection bit" "P413,P001,?..." group.word 0x2E++0x07 line.word 0x00 "RESIN23,SCL3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x02 "RESIN24,SDA3 Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x04 "RESIN25,MFS3_TRIGGER Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." line.word 0x06 "RESIN26,SCS30 Resource Input Setting Register" bitfld.word 0x06 8.--11. " PORTSEL ,Resource selection bit" "P008,P001,?..." group.word 0x38++0x0B line.word 0x00 "RESIN28,SIN4 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P210,P023,P205,?..." line.word 0x02 "RESIN29,SCK4 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P207,P021,?..." line.word 0x04 "RESIN30,SCL4 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x06 "RESIN31,SDA4 Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x08 "RESIN32,MFS4_TRIGGER Resource Input Setting Register" bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." line.word 0x0A "RESIN33,SCS40 Resource Input Setting Register" bitfld.word 0x0A 8.--11. " PORTSEL ,Resource selection bit" "P211,P025,?..." group.word 0x46++0x0B line.word 0x00 "RESIN35,SIN5 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P222,P213,?..." line.word 0x02 "RESIN36,SCK5 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P226,P215,?..." line.word 0x04 "RESIN37,SCL5 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x06 "RESIN38,SDA5 Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x08 "RESIN39,MFS5_TRIGGER Resource Input Setting Register" bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." line.word 0x0A "RESIN40,SCS50 Resource Input Setting Register" bitfld.word 0x0A 8.--11. " PORTSEL ,Resource selection bit" "P224,P212,?..." group.word 0x54++0x0B line.word 0x00 "RESIN42,SIN6 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P130,P329,?..." line.word 0x02 "RESIN43,SCK6 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P202,P327,?..." line.word 0x04 "RESIN44,SCL6 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x06 "RESIN45,SDA6 Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x08 "RESIN46,MFS6_TRIGGER Resource Input Setting Register" bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." line.word 0x0A "RESIN47,SCS60 Resource Input Setting Register" bitfld.word 0x0A 8.--11. " PORTSEL ,Resource selection bit" "P119,P331,P330,?..." group.word 0x62++0x0B line.word 0x00 "RESIN49,SIN7 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P319,P416,P317,P309,?..." line.word 0x02 "RESIN50,SCK7 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P314,P407,?..." line.word 0x04 "RESIN51,SCL7 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x06 "RESIN52,SDA7 Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x08 "RESIN53,MFS7_TRIGGER Resource Input Setting Register" bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "TOT0,TOT1,TOT2,TOT3,?..." line.word 0x0A "RESIN54,SCS70 Resource Input Setting Register" bitfld.word 0x0A 8.--11. " PORTSEL ,Resource selection bit" "P315,P410,?..." group.word 0x70++0x01 line.word 0x00 "RESIN56,SIN8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P009,P006,P016,?..." group.word 0x74++0x05 line.word 0x00 "RESIN58,SCL8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x02 "RESIN59,SDA8 Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x04 "RESIN60,MFS8_TRIGGER Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." group.word 0x80++0x09 line.word 0x00 "RESIN64,SCK9 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P407,P401,?..." line.word 0x02 "RESIN65,SCL9 Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P407,P401,?..." line.word 0x04 "RESIN66,SDA9 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." bitfld.word 0x04 8.--11. " PORTSEL ,Resource selection bit" "P406,P402,?..." line.word 0x06 "RESIN67,MFS9_TRIGGER Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." line.word 0x08 "RESIN68,SCS90 Resource Input Setting Register" bitfld.word 0x08 8.--11. " PORTSEL ,Resource selection bit" "P402,P404,?..." group.word 0x90++0x07 line.word 0x00 "RESIN72,SCL10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x02 "RESIN73,SDA10 Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x04 "RESIN74,MFS10_TRIGGER Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." line.word 0x06 "RESIN75,SCS100 Resource Input Setting Register" bitfld.word 0x06 8.--11. " PORTSEL ,Resource selection bit" "P301,P305,?..." group.word 0x9A++0x01 line.word 0x00 "RESIN77,SIN11 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P107,P109,?..." group.word 0x9E++0x07 line.word 0x00 "RESIN79,SCL11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x02 "RESIN80,SDA11 Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x04 "RESIN81,MFS11_TRIGGER Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." line.word 0x06 "RESIN82,SCS110 Resource Input Setting Register" bitfld.word 0x06 8.--11. " PORTSEL ,Resource selection bit" "P110,P105,?..." group.word 0xA8++0x0B line.word 0x00 "RESIN84,SIN12 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P111,P011,P422,?..." line.word 0x02 "RESIN85,SCK12 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P113,P007,P117,?..." line.word 0x04 "RESIN87,SCL12 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." bitfld.word 0x04 8.--11. " PORTSEL ,Resource selection bit" "P113,P117,?..." line.word 0x06 "RESIN87,SDA12 Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x08 "RESIN88,MFS12_TRIGGER Resource Input Setting Register" bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." line.word 0x0A "RESIN89,SCS120 Resource Input Setting Register" bitfld.word 0x0A 8.--11. " PORTSEL ,Resource selection bit" "P114,P008,?..." group.word 0xBA++0x05 line.word 0x00 "RESIN93,SCL13 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x02 "RESIN94,SDA13 Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "80ns noise filter disable,80ns noise filter enable,?..." line.word 0x04 "RESIN95,MFS13_TRIGGER Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "TOT16,TOT17,?..." group.word 0x1A4++0x09 line.word 0x00 "RESIN210,RX0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN0_PIN_AND_TX,?..." bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P307,P229,P225,?..." line.word 0x02 "RESIN211,RX1 Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN1_PIN_AND_TX,?..." bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P402,P318,P107,?..." line.word 0x04 "RESIN212,RX2 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN2_PIN_AND_TX,?..." bitfld.word 0x04 8.--11. " PORTSEL ,Resource selection bit" "P222,P405,?..." line.word 0x06 "RESIN213,RX3 Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN3_PIN_AND_TX,?..." line.word 0x08 "RESIN214,RX4 Resource Input Setting Register" bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN4_PIN_AND_TX,?..." group.word 0x1B4++0x09 line.word 0x00 "RESIN218,RX8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,CAN8_PIN_AND_TX,?..." line.word 0x02 "RESIN219,TIN0 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P106,P220,?..." bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT3,RLT3_UFSET,TOT1,TIOA0,?..." line.word 0x04 "RESIN220,TIN1 Resource Input Setting Register" bitfld.word 0x04 8.--11. " PORTSEL ,Resource selection bit" "P108,P226,?..." bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,TIOA2,?..." line.word 0x06 "RESIN221,TIN2 Resource Input Setting Register" bitfld.word 0x06 8.--11. " PORTSEL ,Resource selection bit" "P112,P228,?..." bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT1,RLT1_UFSET,TOT3,TIOA4,?..." line.word 0x08 "RESIN222,TIN3 Resource Input Setting Register" bitfld.word 0x08 8.--11. " PORTSEL ,Resource selection bit" "P114,P301,?..." bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT2,RLT2_UFSET,TOT0,TIOA6,?..." group.word 0x1D6++0x03 line.word 0x00 "RESIN235,TIN16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P117,P304,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT17,RLT17_UFSET,,TIOA8,?..." line.word 0x02 "RESIN236,TIN17 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P119,P307,?..." bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,,TIOA10,?..." group.word 0x1F6++0x29 line.word 0x00 "RESIN251,INT0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P225,P009,P001,?..." line.word 0x02 "RESIN252,INT1 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P307,P027,P011,?..." line.word 0x04 "RESIN253,INT2 Resource Input Setting Register" bitfld.word 0x04 8.--11. " PORTSEL ,Resource selection bit" "P402,P107,P013,?..." line.word 0x06 "RESIN254,INT3 Resource Input Setting Register" bitfld.word 0x06 8.--11. " PORTSEL ,Resource selection bit" "P022,P108,?..." line.word 0x08 "RESIN255,INT4 Resource Input Setting Register" bitfld.word 0x08 8.--11. " PORTSEL ,Resource selection bit" "P028,P117,P017,?..." line.word 0x0A "RESIN256,INT5 Resource Input Setting Register" bitfld.word 0x0A 8.--11. " PORTSEL ,Resource selection bit" "P130,P118,P127,?..." line.word 0x0C "RESIN257,INT6 Resource Input Setting Register" bitfld.word 0x0C 8.--11. " PORTSEL ,Resource selection bit" "P210,P202,?..." line.word 0x0E "RESIN258,INT7 Resource Input Setting Register" bitfld.word 0x0E 8.--11. " PORTSEL ,Resource selection bit" "P222,P207,?..." line.word 0x10 "RESIN259,INT8 Resource Input Setting Register" bitfld.word 0x10 8.--11. " PORTSEL ,Resource selection bit" "P229,P213,P020,?..." line.word 0x12 "RESIN260,INT9 Resource Input Setting Register" bitfld.word 0x12 8.--11. " PORTSEL ,Resource selection bit" "P318,P215,?..." line.word 0x14 "RESIN261,INT10 Resource Input Setting Register" bitfld.word 0x14 8.--11. " PORTSEL ,Resource selection bit" "P325,P313,?..." line.word 0x16 "RESIN262,INT11 Resource Input Setting Register" bitfld.word 0x16 8.--11. " PORTSEL ,Resource selection bit" "P405,P317,P030,?..." line.word 0x18 "RESIN263,INT12 Resource Input Setting Register" bitfld.word 0x18 8.--11. " PORTSEL ,Resource selection bit" "P408,P319,P421,P105,?..." line.word 0x1A "RESIN264,INT13 Resource Input Setting Register" bitfld.word 0x1A 8.--11. " PORTSEL ,Resource selection bit" "P415,P511,P114,?..." line.word 0x1C "RESIN265,INT14 Resource Input Setting Register" bitfld.word 0x1C 8.--11. " PORTSEL ,Resource selection bit" "P418,P413,?..." line.word 0x1E "RESIN266,INT15 Resource Input Setting Register" bitfld.word 0x1E 8.--11. " PORTSEL ,Resource selection bit" "P310,P417,P123,?..." line.word 0x20 "RESIN267,INT16 Resource Input Setting Register" bitfld.word 0x20 8.--11. " PORTSEL ,Resource selection bit" "P005,P203,?..." line.word 0x22 "RESIN268,INT17 Resource Input Setting Register" bitfld.word 0x22 8.--11. " PORTSEL ,Resource selection bit" "P016,P214,?..." line.word 0x24 "RESIN269,INT18 Resource Input Setting Register" bitfld.word 0x24 8.--11. " PORTSEL ,Resource selection bit" "P103,P006,?..." line.word 0x26 "RESIN270,INT19 Resource Input Setting Register" bitfld.word 0x26 8.--11. " PORTSEL ,Resource selection bit" "P109,P230,?..." line.word 0x28 "RESIN271,INT20 Resource Input Setting Register" bitfld.word 0x28 8.--11. " PORTSEL ,Resource selection bit" "P422,P300,?..." group.word 0x222++0x0D line.word 0x00 "RESIN273,INT22 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P128,P023,?..." line.word 0x02 "RESIN274,INT23 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P204,P111,?..." line.word 0x04 "RESIN275,INT24 Resource Input Setting Register" bitfld.word 0x04 8.--11. " PORTSEL ,Resource selection bit" "P205,P304,?..." line.word 0x06 "RESIN276,INT25 Resource Input Setting Register" bitfld.word 0x06 8.--11. " PORTSEL ,Resource selection bit" "P220,P124,?..." line.word 0x08 "RESIN277,INT26 Resource Input Setting Register" bitfld.word 0x08 8.--11. " PORTSEL ,Resource selection bit" "P302,P329,?..." line.word 0x0A "RESIN278,INT27 Resource Input Setting Register" bitfld.word 0x0A 8.--11. " PORTSEL ,Resource selection bit" "P309,P308,?..." line.word 0x0C "RESIN279,INT28 Resource Input Setting Register" bitfld.word 0x0C 8.--11. " PORTSEL ,Resource selection bit" "P315,P321,?..." group.word 0x232++0x0D line.word 0x00 "RESIN281,INT30 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P416,P409,?..." line.word 0x02 "RESIN282,INT31 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P420,P421,?..." line.word 0x04 "RESIN283,TEXT0 Resource Input Setting Register" bitfld.word 0x04 8.--11. " PORTSEL ,Resource selection bit" "P019,P027,?..." bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT1,TIOA1,?..." line.word 0x06 "RESIN284,TEXT1 Resource Input Setting Register" bitfld.word 0x06 8.--11. " PORTSEL ,Resource selection bit" "P020,P127,?..." bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT2,TIOA3,?..." line.word 0x08 "RESIN285,TEXT2 Resource Input Setting Register" bitfld.word 0x08 8.--11. " PORTSEL ,Resource selection bit" "P218,P128,?..." bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT3,TIOA5,?..." line.word 0x0A "RESIN286,TEXT3 Resource Input Setting Register" bitfld.word 0x0A 8.--11. " PORTSEL ,Resource selection bit" "P219,P205,?..." bitfld.word 0x0A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT1,TIOA7,?..." line.word 0x0C "RESIN287,TEXT4 Resource Input Setting Register" bitfld.word 0x0C 8.--11. " PORTSEL ,Resource selection bit" "P304,P206,?..." bitfld.word 0x0C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TOT2,TIOA9,?..." group.word 0x246++0x05 line.word 0x00 "RESIN291,TEXT8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P305,P207,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,TIOA17,?..." line.word 0x02 "RESIN292,TEXT9 Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT2_UFSET,TIOA19,?..." line.word 0x04 "RESIN293,TEXT10 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT3_UFSET,TIOA21,?..." group.word 0x256++0x11 line.word 0x00 "RESIN299,OCU0/OCU1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,?..." line.word 0x02 "RESIN300,OCU0_MOD Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." line.word 0x04 "RESIN301,OCU1_MOD Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." line.word 0x06 "RESIN302,OCU2/OCU3 Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,FRT0,?..." line.word 0x08 "RESIN303,OCU2_MOD Resource Input Setting Register" bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." line.word 0x0A "RESIN304,OCU3_MOD Resource Input Setting Register" bitfld.word 0x0A 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." line.word 0x0C "RESIN305,OCU4/OCU5 Resource Input Setting Register" bitfld.word 0x0C 0.--3. " RESSEL ,Resource selection bit" "FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,FRT0,FRT1,?..." line.word 0x0E "RESIN306,OCU4_MOD Resource Input Setting Register" bitfld.word 0x0E 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." line.word 0x10 "RESIN307,OCU5_MOD Resource Input Setting Register" bitfld.word 0x10 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x286++0x11 line.word 0x00 "RESIN323,OCU16/OCU17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,?..." line.word 0x02 "RESIN324,OCU16_MOD Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." line.word 0x04 "RESIN325,OCU17_MOD Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." line.word 0x06 "RESIN323,OCU18/OCU19 Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "FRT9,FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,?..." line.word 0x08 "RESIN324,OCU18_MOD Resource Input Setting Register" bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." line.word 0x0A "RESIN328,OCU19_MOD Resource Input Setting Register" bitfld.word 0x0A 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." line.word 0x0C "RESIN329,OCU20/OCU21 Resource Input Setting Register" bitfld.word 0x0C 0.--3. " RESSEL ,Resource selection bit" "FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,?..." line.word 0x0E "RESIN330,OCU20_MOD Resource Input Setting Register" bitfld.word 0x0E 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." line.word 0x10 "RESIN331,OCU21_MOD Resource Input Setting Register" bitfld.word 0x10 0.--3. " RESSEL ,Resource selection bit" "Set 1,Set 0,?..." group.word 0x2B6++0x11 line.word 0x00 "RESIN347,IN0 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P401,P308,P210,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS0_LSYN,,TOT0,TOT1,?..." line.word 0x02 "RESIN348,IN1 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P402,P309,P211,?..." bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS0_LSYN,,TOT0,TOT2,?..." line.word 0x04 "RESIN349,ICU0/ICU1 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,?..." line.word 0x06 "RESIN350,IN2 Resource Input Setting Register" bitfld.word 0x06 8.--11. " PORTSEL ,Resource selection bit" "P403,P312,P212,,P409,?..." bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS2_LSYN,,TOT0,TOT3,?..." line.word 0x08 "RESIN351,IN3 Resource Input Setting Register" bitfld.word 0x08 8.--11. " PORTSEL ,Resource selection bit" "P404,P313,P213,?..." bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS3_LSYN,,TOT0,TOT1,?..." line.word 0x0A "RESIN352,ICU2/ICU3 Resource Input Setting Register" bitfld.word 0x0A 0.--3. " RESSEL ,Resource selection bit" "FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,FRT0,?..." line.word 0x0C "RESIN353,IN4 Resource Input Setting Register" bitfld.word 0x0C 8.--11. " PORTSEL ,Resource selection bit" "P405,P314,P214,?..." bitfld.word 0x0C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS4_LSYN,,TOT0,TOT2,?..." line.word 0x0E "RESIN354,IN5 Resource Input Setting Register" bitfld.word 0x0E 8.--11. " PORTSEL ,Resource selection bit" "P416,P315,P215,?..." bitfld.word 0x0E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS5_LSYN,,TOT0,TOT3,?..." line.word 0x10 "RESIN355,ICU4/ICU5 Resource Input Setting Register" bitfld.word 0x10 0.--3. " RESSEL ,Resource selection bit" "FRT2,FRT3,FRT4,FRT8,FRT9,FRT10,FRT0,FRT1,?..." group.word 0x2E6++0x11 line.word 0x00 "RESIN371,IN16 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P005,P129,P220,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS6_LSYN,,TOT0,TOT1,?..." line.word 0x02 "RESIN372,IN17 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P006,P130,P222,?..." bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS7_LSYN,,TOT0,TOT2,?..." line.word 0x04 "RESIN373,ICU16/ICU17 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "FRT8,FRT9,FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,?..." line.word 0x06 "RESIN374,IN18 Resource Input Setting Register" bitfld.word 0x06 8.--11. " PORTSEL ,Resource selection bit" "P007,P131,P223,?..." bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS8_LSYN,MFS12_LSYN,TOT0,TOT1,?..." line.word 0x08 "RESIN375,IN19 Resource Input Setting Register" bitfld.word 0x08 8.--11. " PORTSEL ,Resource selection bit" "P008,P202,P224,?..." bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS9_LSYN,MFS13_LSYN,TOT0,TOT2,?..." line.word 0x0A "RESIN376,ICU18/ICU19 Resource Input Setting Register" bitfld.word 0x0A 0.--3. " RESSEL ,Resource selection bit" "FRT9,FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,?..." line.word 0x0C "RESIN377,IN20 Resource Input Setting Register" bitfld.word 0x0C 8.--11. " PORTSEL ,Resource selection bit" "P009,P203,P225,?..." bitfld.word 0x0C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS10_LSYN,,TOT0,TOT2,?..." line.word 0x0E "RESIN378,IN21 Resource Input Setting Register" bitfld.word 0x0E 8.--11. " PORTSEL ,Resource selection bit" "P010,P204,P226,?..." bitfld.word 0x0E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,MFS11_LSYN,,TOT0,TOT3,?..." line.word 0x10 "RESIN379,ICU20/ICU21 Resource Input Setting Register" bitfld.word 0x10 0.--3. " RESSEL ,Resource selection bit" "FRT10,FRT0,FRT1,FRT2,FRT3,FRT4,FRT8,FRT9,?..." group.word 0x346++0x0B line.word 0x00 "RESIN419,AIN8 Resource Input Setting Register" bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P000,P203,P010,?..." bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,TIOA0,TIOA1,TIOA2,?..." line.word 0x02 "RESIN420,BIN8 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P001,P204,P012,?..." bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT1,TIOA1,TIOA2,TIOA0,?..." line.word 0x04 "RESIN421,ZIN8 Resource Input Setting Register" bitfld.word 0x04 8.--11. " PORTSEL ,Resource selection bit" "P003,P205,P013,?..." bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT2,TIOA2,TIOA0,TIOA1,?..." line.word 0x06 "RESIN422,AIN9 Resource Input Setting Register" bitfld.word 0x06 8.--11. " PORTSEL ,Resource selection bit" "P005,P223,?..." bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT1,TIOA3,TIOA4,TIOA5,?..." line.word 0x08 "RESIN423,BIN9 Resource Input Setting Register" bitfld.word 0x08 8.--11. " PORTSEL ,Resource selection bit" "P006,P224,?..." bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT2,TIOA4,TIOA5,TIOA3,?..." line.word 0x0A "RESIN424,ZIN9 Resource Input Setting Register" bitfld.word 0x0A 8.--11. " PORTSEL ,Resource selection bit" "P007,P225,?..." bitfld.word 0x0A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT3,TIOA5,TIOA3,TIOA4,?..." group.word 0x376++0xC3 line.word 0x00 "RESIN443,TIOB0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT0_MTSF,OUT0,?..." line.word 0x02 "RESIN444,TIOA1 Resource Input Setting Register" bitfld.word 0x02 8.--11. " PORTSEL ,Resource selection bit" "P009,P004,?..." bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT0_MTSF,OUT0,?..." line.word 0x04 "RESIN445,TIOB1 Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT0_MTSF,OUT0,?..." line.word 0x06 "RESIN446,TIOB2 Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT1_MTSF,OUT1,?..." line.word 0x08 "RESIN447,TIOA3 Resource Input Setting Register" bitfld.word 0x08 8.--11. " PORTSEL ,Resource selection bit" "P012,P014,?..." bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT1_MTSF,OUT1,?..." line.word 0x0A "RESIN448,TIOB3 Resource Input Setting Register" bitfld.word 0x0A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT1_MTSF,OUT1,?..." line.word 0x0C "RESIN449,TIOB4 Resource Input Setting Register" bitfld.word 0x0C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT2_MTSF,OUT2,?..." line.word 0x0E "RESIN450,TIOA5 Resource Input Setting Register" bitfld.word 0x0E 8.--11. " PORTSEL ,Resource selection bit" "P015,P113,?..." bitfld.word 0x0E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT2_MTSF,OUT2,?..." line.word 0x10 "RESIN451,TIOB5 Resource Input Setting Register" bitfld.word 0x10 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT2_MTSF,OUT2,?..." line.word 0x12 "RESIN452,TIOB6 Resource Input Setting Register" bitfld.word 0x12 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT3_MTSF,OUT3,?..." line.word 0x14 "RESIN453,TIOA7 Resource Input Setting Register" bitfld.word 0x14 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT3_MTSF,OUT3,?..." line.word 0x16 "RESIN454,TIOB7 Resource Input Setting Register" bitfld.word 0x16 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT3_MTSF,OUT3,?..." line.word 0x18 "RESIN455,TIOB8 Resource Input Setting Register" bitfld.word 0x18 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT4_MTSF,OUT4,?..." line.word 0x1A "RESIN456,TIOA9 Resource Input Setting Register" bitfld.word 0x1A 8.--11. " PORTSEL ,Resource selection bit" "P105,P317,?..." bitfld.word 0x1A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT4_MTSF,OUT4,?..." line.word 0x1C "RESIN457,TIOB9 Resource Input Setting Register" bitfld.word 0x1C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT4_MTSF,OUT4,?..." line.word 0x1E "RESIN458,TIOB10 Resource Input Setting Register" bitfld.word 0x1E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT0_MTSF,OUT5,?..." line.word 0x20 "RESIN459,TIOB11 Resource Input Setting Register" bitfld.word 0x20 8.--11. " PORTSEL ,Resource selection bit" "P108,P122,?..." bitfld.word 0x20 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT0_MTSF,OUT5,?..." line.word 0x22 "RESIN460,TIOB11 Resource Input Setting Register" bitfld.word 0x22 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT0_MTSF,OUT5,?..." line.word 0x24 "RESIN461,TIOB12 Resource Input Setting Register" bitfld.word 0x24 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT1,RLT1_UFSET,FRT8_MTSF,OUT0,?..." line.word 0x26 "RESIN462,TIOA13 Resource Input Setting Register" bitfld.word 0x26 8.--11. " PORTSEL ,Resource selection bit" "P112,P212,?..." bitfld.word 0x26 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT1,RLT1_UFSET,FRT8_MTSF,OUT0,?..." line.word 0x28 "RESIN463,TIOB13 Resource Input Setting Register" bitfld.word 0x28 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT1,RLT1_UFSET,FRT8_MTSF,OUT0,?..." line.word 0x2A "RESIN464,TIOB14 Resource Input Setting Register" bitfld.word 0x2A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT2,RLT1_UFSET,FRT9_MTSF,OUT1,?..." line.word 0x2C "RESIN465,TIOA15 Resource Input Setting Register" bitfld.word 0x2C 8.--11. " PORTSEL ,Resource selection bit" "P124,P214,?..." bitfld.word 0x2C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT2,RLT2_UFSET,FRT9_MTSF,OUT1,?..." line.word 0x2E "RESIN466,TIOB15 Resource Input Setting Register" bitfld.word 0x2E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT2,RLT2_UFSET,FRT9_MTSF,OUT1,?..." line.word 0x30 "RESIN467,TIOB16 Resource Input Setting Register" bitfld.word 0x30 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT3,RLT3_UFSET,FRT10_MTSF,OUT16,?..." line.word 0x32 "RESIN468,TIOA17 Resource Input Setting Register" bitfld.word 0x32 8.--11. " PORTSEL ,Resource selection bit" "P200,P226,?..." bitfld.word 0x32 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT3,RLT3_UFSET,FRT10_MTSF,OUT16,?..." line.word 0x34 "RESIN469,TIOB17 Resource Input Setting Register" bitfld.word 0x34 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT3,RLT3_UFSET,FRT10_MTSF,OUT16,?..." line.word 0x36 "RESIN470,TIOB18 Resource Input Setting Register" bitfld.word 0x36 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT17,RLT17_UFSET,FRT8_MTSF,OUT17,?..." line.word 0x38 "RESIN471,TIOA19 Resource Input Setting Register" bitfld.word 0x38 8.--11. " PORTSEL ,Resource selection bit" "P208,P302,?..." bitfld.word 0x38 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT17,RLT17_UFSET,FRT8_MTSF,OUT17,?..." line.word 0x3A "RESIN472,TIOB19 Resource Input Setting Register" bitfld.word 0x3A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT17,RLT17_UFSET,FRT8_MTSF,OUT17,?..." line.word 0x3C "RESIN473,TIOB20 Resource Input Setting Register" bitfld.word 0x3C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT9_MTSF,OUT18,?..." line.word 0x3E "RESIN474,TIOA21 Resource Input Setting Register" bitfld.word 0x3E 8.--11. " PORTSEL ,Resource selection bit" "P210,P316,?..." bitfld.word 0x3E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT9_MTSF,OUT18,?..." line.word 0x40 "RESIN475,TIOB21 Resource Input Setting Register" bitfld.word 0x40 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT9_MTSF,OUT18,?..." line.word 0x42 "RESIN476,TIOB22 Resource Input Setting Register" bitfld.word 0x42 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT10_MTSF,OUT19,?..." line.word 0x44 "RESIN477,TIOA23 Resource Input Setting Register" bitfld.word 0x44 8.--11. " PORTSEL ,Resource selection bit" "P227,P417,?..." bitfld.word 0x44 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT10_MTSF,OUT19,?..." line.word 0x46 "RESIN478,TIOB23 Resource Input Setting Register" bitfld.word 0x46 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT10_MTSF,OUT19,?..." line.word 0x48 "RESIN479,TIOA23 Resource Input Setting Register" bitfld.word 0x48 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT10_MTSF,OUT20,?..." line.word 0x4A "RESIN480,TIOA25 Resource Input Setting Register" bitfld.word 0x4A 8.--11. " PORTSEL ,Resource selection bit" "P229,P412,?..." bitfld.word 0x4A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT0_MTSF,OUT20,?..." line.word 0x4C "RESIN481,TIOB25 Resource Input Setting Register" bitfld.word 0x4C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT0_MTSF,OUT20,?..." line.word 0x4E "RESIN482,TIOB26 Resource Input Setting Register" bitfld.word 0x4E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT1_MTSF,OUT21,?..." line.word 0x50 "RESIN483,TIOA27 Resource Input Setting Register" bitfld.word 0x50 8.--11. " PORTSEL ,Resource selection bit" "P231,P419,?..." bitfld.word 0x50 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT1_MTSF,OUT21,?..." line.word 0x52 "RESIN484,TIOB27 Resource Input Setting Register" bitfld.word 0x52 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT1_MTSF,OUT21,?..." line.word 0x54 "RESIN485,TIOB28 Resource Input Setting Register" bitfld.word 0x54 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT2_MTSF,OUT0,?..." line.word 0x56 "RESIN486,TIOA29 Resource Input Setting Register" bitfld.word 0x56 8.--11. " PORTSEL ,Resource selection bit" "P305,P309,?..." bitfld.word 0x56 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT2_MTSF,OUT0,?..." line.word 0x58 "RESIN487,TIOB29 Resource Input Setting Register" bitfld.word 0x58 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT2_MTSF,OUT0,?..." line.word 0x5A "RESIN488,TIOB30 Resource Input Setting Register" bitfld.word 0x5A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT3_MTSF,OUT1,?..." line.word 0x5C "RESIN489,TIOA31 Resource Input Setting Register" bitfld.word 0x5C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT3_MTSF,OUT1,?..." line.word 0x5E "RESIN490,TIOB31 Resource Input Setting Register" bitfld.word 0x5E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT3_MTSF,OUT1,?..." line.word 0x60 "RESIN491,TIOB32 Resource Input Setting Register" bitfld.word 0x60 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT1,RLT1_UFSET,FRT4_MTSF,OUT2,?..." line.word 0x62 "RESIN492,TIOA33 Resource Input Setting Register" bitfld.word 0x62 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT1,RLT1_UFSET,FRT4_MTSF,OUT2,?..." line.word 0x64 "RESIN493,TIOB33 Resource Input Setting Register" bitfld.word 0x64 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT1,RLT1_UFSET,FRT4_MTSF,OUT2,?..." line.word 0x66 "RESIN494,TIOB34 Resource Input Setting Register" bitfld.word 0x66 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT2,RLT2_UFSET,FRT0_MTSF,OUT3,?..." line.word 0x68 "RESIN495,TIOA35 Resource Input Setting Register" bitfld.word 0x68 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT2,RLT2_UFSET,FRT0_MTSF,OUT3,?..." line.word 0x6A "RESIN496,TIOB35 Resource Input Setting Register" bitfld.word 0x6A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT2,RLT2_UFSET,FRT0_MTSF,OUT3,?..." line.word 0x6C "RESIN497,TIOB36 Resource Input Setting Register" bitfld.word 0x6C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT3,RLT3_UFSET,FRT8_MTSF,OUT4,?..." line.word 0x6E "RESIN498,TIOA37 Resource Input Setting Register" bitfld.word 0x6E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT3,RLT3_UFSET,FRT8_MTSF,OUT4,?..." line.word 0x70 "RESIN499,TIOB37 Resource Input Setting Register" bitfld.word 0x70 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT3,RLT3_UFSET,FRT8_MTSF,OUT4,?..." line.word 0x72 "RESIN500,TIOB38 Resource Input Setting Register" bitfld.word 0x72 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT17,RLT17_UFSET,FRT9_MTSF,OUT5,?..." line.word 0x74 "RESIN501,TIOA39 Resource Input Setting Register" bitfld.word 0x74 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT17,RLT17_UFSET,FRT9_MTSF,OUT5,?..." line.word 0x76 "RESIN502,TIOB39 Resource Input Setting Register" bitfld.word 0x76 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT10_MTSF,OUT0,?..." line.word 0x78 "RESIN503,TIOB40 Resource Input Setting Register" bitfld.word 0x78 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT10_MTSF,OUT0,?..." line.word 0x7A "RESIN504,TIOA41 Resource Input Setting Register" bitfld.word 0x7A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT10_MTSF,OUT0,?..." line.word 0x7C "RESIN505,TIOB41 Resource Input Setting Register" bitfld.word 0x7C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT10_MTSF,OUT0,?..." line.word 0x7E "RESIN506,TIOB42 Resource Input Setting Register" bitfld.word 0x7E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT8_MTSF,OUT1,?..." line.word 0x80 "RESIN507,TIOA43 Resource Input Setting Register" bitfld.word 0x80 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT8_MTSF,OUT1,?..." line.word 0x82 "RESIN508,TIOB43 Resource Input Setting Register" bitfld.word 0x82 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT8_MTSF,OUT1,?..." line.word 0x84 "RESIN509,TIOB44 Resource Input Setting Register" bitfld.word 0x84 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT9_MTSF,OUT16,?..." line.word 0x86 "RESIN510,TIOA45 Resource Input Setting Register" bitfld.word 0x86 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT9_MTSF,OUT16,?..." line.word 0x88 "RESIN511,TIOB45 Resource Input Setting Register" bitfld.word 0x88 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT3,RLT3_UFSET,FRT9_MTSF,OUT16,?..." line.word 0x8A "RESIN512,TIOB46 Resource Input Setting Register" bitfld.word 0x8A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT10_MTSF,OUT17,?..." line.word 0x8C "RESIN513,TIOA47 Resource Input Setting Register" bitfld.word 0x8C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT10_MTSF,OUT17,?..." line.word 0x8E "RESIN514,TIOB47 Resource Input Setting Register" bitfld.word 0x8E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT16,RLT16_UFSET,FRT10_MTSF,OUT17,?..." line.word 0x90 "RESIN515,TIOB48 Resource Input Setting Register" bitfld.word 0x90 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT0_MTSF,OUT18,?..." line.word 0x92 "RESIN516,TIOA49 Resource Input Setting Register" bitfld.word 0x92 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT0_MTSF,OUT18,?..." line.word 0x94 "RESIN517,TIOB49 Resource Input Setting Register" bitfld.word 0x94 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT17,RLT17_UFSET,FRT0_MTSF,OUT18,?..." line.word 0x96 "RESIN518,TIOB50 Resource Input Setting Register" bitfld.word 0x96 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT1_MTSF,OUT19,?..." line.word 0x98 "RESIN519,TIOA51 Resource Input Setting Register" bitfld.word 0x98 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT1_MTSF,OUT19,?..." line.word 0x9A "RESIN520,TIOB51 Resource Input Setting Register" bitfld.word 0x9A 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT0,RLT0_UFSET,FRT1_MTSF,OUT19,?..." line.word 0x9C "RESIN521,TIOB52 Resource Input Setting Register" bitfld.word 0x9C 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT1,RLT1_UFSET,FRT2_MTSF,OUT20,?..." line.word 0x9E "RESIN522,TIOA53 Resource Input Setting Register" bitfld.word 0x9E 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT1,RLT1_UFSET,FRT2_MTSF,OUT20,?..." line.word 0xA0 "RESIN523,TIOB53 Resource Input Setting Register" bitfld.word 0xA0 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT1,RLT1_UFSET,FRT2_MTSF,OUT20,?..." line.word 0xA2 "RESIN524,TIOB54 Resource Input Setting Register" bitfld.word 0xA2 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT2,RLT2_UFSET,FRT3_MTSF,OUT21,?..." line.word 0xA4 "RESIN525,TIOA55 Resource Input Setting Register" bitfld.word 0xA4 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT2,RLT2_UFSET,FRT3_MTSF,OUT21,?..." line.word 0xA6 "RESIN526,TIOB55 Resource Input Setting Register" bitfld.word 0xA6 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT2,RLT2_UFSET,FRT3_MTSF,OUT21,?..." line.word 0xA8 "RESIN527,TIOB56 Resource Input Setting Register" bitfld.word 0xA8 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT3,RLT3_UFSET,FRT4_MTSF,OUT0,?..." line.word 0xAA "RESIN528,TIOA57 Resource Input Setting Register" bitfld.word 0xAA 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT3,RLT3_UFSET,FRT4_MTSF,OUT0,?..." line.word 0xAC "RESIN529,TIOB57 Resource Input Setting Register" bitfld.word 0xAC 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT3,RLT3_UFSET,FRT4_MTSF,OUT0,?..." line.word 0xAE "RESIN530,TIOB58 Resource Input Setting Register" bitfld.word 0xAE 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT17,RLT17_UFSET,FRT0_MTSF,OUT1,?..." line.word 0xB0 "RESIN531,TIOA59 Resource Input Setting Register" bitfld.word 0xB0 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT17,RLT17_UFSET,FRT0_MTSF,OUT1,?..." line.word 0xB2 "RESIN532,TIOB59 Resource Input Setting Register" bitfld.word 0xB2 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT16,RLT16_UFSET,TOT17,RLT17_UFSET,FRT0_MTSF,OUT1,?..." line.word 0xB4 "RESIN533,TIOB60 Resource Input Setting Register" bitfld.word 0xB4 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT8_MTSF,OUT2,?..." line.word 0xB6 "RESIN534,TIOA61 Resource Input Setting Register" bitfld.word 0xB6 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT8_MTSF,OUT2,?..." line.word 0xB8 "RESIN535,TIOB61 Resource Input Setting Register" bitfld.word 0xB8 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT1,RLT1_UFSET,FRT8_MTSF,OUT2,?..." line.word 0xBA "RESIN536,TIOB62 Resource Input Setting Register" bitfld.word 0xBA 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT9_MTSF,OUT3,?..." line.word 0xBC "RESIN537,TIOA63 Resource Input Setting Register" bitfld.word 0xBC 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT9_MTSF,OUT3,?..." line.word 0xBE "RESIN538,TIOB63 Resource Input Setting Register" bitfld.word 0xBE 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,TOT0,RLT0_UFSET,TOT2,RLT2_UFSET,FRT9_MTSF,OUT3,?..." line.word 0xC0 "RESIN539,ADTG0 Resource Input Setting Register" bitfld.word 0xC0 8.--11. " PORTSEL ,Resource selection bit" "P214,P211,?..." line.word 0xC2 "RESIN540,ADTG1 Resource Input Setting Register" bitfld.word 0xC2 8.--11. " PORTSEL ,Resource selection bit" "P215,P128,?..." width 10. group.word 0x43A++0x01 line.word 0x00 "RESIN541,ADC0_HWTRG0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT0,OUT1,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x43C++0x01 line.word 0x00 "RESIN542,BT_ADTO_0A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x43E++0x01 line.word 0x00 "RESIN543,BT_ADTO_0B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x440++0x01 line.word 0x00 "RESIN544,BT_ADTO_0C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x442++0x01 line.word 0x00 "RESIN545,BT_ADTO_0D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x444++0x01 line.word 0x00 "RESIN546,ADC0_HWTRG1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT1,OUT2,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x446++0x01 line.word 0x00 "RESIN547,BT_ADTO_1A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x448++0x01 line.word 0x00 "RESIN548,BT_ADTO_1B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x44A++0x01 line.word 0x00 "RESIN549,BT_ADTO_1C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x44C++0x01 line.word 0x00 "RESIN550,BT_ADTO_1D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x44E++0x01 line.word 0x00 "RESIN551,ADC0_HWTRG2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT2_UFSET,RLT3_UFSET,OUT2,OUT3,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x450++0x01 line.word 0x00 "RESIN552,BT_ADTO_2A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x452++0x01 line.word 0x00 "RESIN553,BT_ADTO_2B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x454++0x01 line.word 0x00 "RESIN554,BT_ADTO_2C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x456++0x01 line.word 0x00 "RESIN555,BT_ADTO_2D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x458++0x01 line.word 0x00 "RESIN556,ADC0_HWTRG3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT3_UFSET,RLT16_UFSET,OUT3,OUT4,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x45A++0x01 line.word 0x00 "RESIN557,BT_ADTO_3A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x45C++0x01 line.word 0x00 "RESIN558,BT_ADTO_3B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x45E++0x01 line.word 0x00 "RESIN559,BT_ADTO_3C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x460++0x01 line.word 0x00 "RESIN560,BT_ADTO_3D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x462++0x01 line.word 0x00 "RESIN561,ADC0_HWTRG4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OUT4,OUT5,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x464++0x01 line.word 0x00 "RESIN562,BT_ADTO_4A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x466++0x01 line.word 0x00 "RESIN563,BT_ADTO_4B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x468++0x01 line.word 0x00 "RESIN564,BT_ADTO_4C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x46A++0x01 line.word 0x00 "RESIN565,BT_ADTO_4D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x46C++0x01 line.word 0x00 "RESIN566,ADC0_HWTRG5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OUT5,OUT0,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x46E++0x01 line.word 0x00 "RESIN567,BT_ADTO_5A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x470++0x01 line.word 0x00 "RESIN568,BT_ADTO_5B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x472++0x01 line.word 0x00 "RESIN569,BT_ADTO_5C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x474++0x01 line.word 0x00 "RESIN570,BT_ADTO_5D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x476++0x01 line.word 0x00 "RESIN571,ADC0_HWTRG6 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT0,OUT1,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x478++0x01 line.word 0x00 "RESIN572,BT_ADTO_6A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x47A++0x01 line.word 0x00 "RESIN573,BT_ADTO_6B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x47C++0x01 line.word 0x00 "RESIN574,BT_ADTO_6C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x47E++0x01 line.word 0x00 "RESIN575,BT_ADTO_6D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x480++0x01 line.word 0x00 "RESIN576,ADC0_HWTRG7 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT1,OUT16,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x482++0x01 line.word 0x00 "RESIN577,BT_ADTO_7A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x484++0x01 line.word 0x00 "RESIN578,BT_ADTO_7B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x486++0x01 line.word 0x00 "RESIN579,BT_ADTO_7C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x488++0x01 line.word 0x00 "RESIN580,BT_ADTO_7D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x48A++0x01 line.word 0x00 "RESIN581,ADC0_HWTRG8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT2_UFSET,RLT3_UFSET,OUT16,OUT17,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x48C++0x01 line.word 0x00 "RESIN582,BT_ADTO_8A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x48E++0x01 line.word 0x00 "RESIN583,BT_ADTO_8B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x490++0x01 line.word 0x00 "RESIN584,BT_ADTO_8C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x492++0x01 line.word 0x00 "RESIN585,BT_ADTO_8D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x494++0x01 line.word 0x00 "RESIN586,ADC0_HWTRG9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT3_UFSET,RLT16_UFSET,OUT17,OUT18,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x496++0x01 line.word 0x00 "RESIN587,BT_ADTO_9A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x498++0x01 line.word 0x00 "RESIN588,BT_ADTO_9B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x49A++0x01 line.word 0x00 "RESIN589,BT_ADTO_9C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x49C++0x01 line.word 0x00 "RESIN590,BT_ADTO_9D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x49E++0x01 line.word 0x00 "RESIN591,ADC0_HWTRG10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OUT18,OUT19,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x4A0++0x01 line.word 0x00 "RESIN592,BT_ADTO_10A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4A2++0x01 line.word 0x00 "RESIN593,BT_ADTO_10B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4A4++0x01 line.word 0x00 "RESIN594,BT_ADTO_10C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x4A6++0x01 line.word 0x00 "RESIN595,BT_ADTO_10D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x4A8++0x01 line.word 0x00 "RESIN596,ADC0_HWTRG11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OUT19,OUT20,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x4AA++0x01 line.word 0x00 "RESIN597,BT_ADTO_11A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4AC++0x01 line.word 0x00 "RESIN598,BT_ADTO_11B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4AE++0x01 line.word 0x00 "RESIN599,BT_ADTO_11C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x4B0++0x01 line.word 0x00 "RESIN600,BT_ADTO_11D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x4B2++0x01 line.word 0x00 "RESIN601,ADC0_HWTRG12 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT20,OUT21,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x4B4++0x01 line.word 0x00 "RESIN602,BT_ADTO_12A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4B6++0x01 line.word 0x00 "RESIN603,BT_ADTO_12B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4B8++0x01 line.word 0x00 "RESIN604,BT_ADTO_12C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x4BA++0x01 line.word 0x00 "RESIN605,BT_ADTO_12D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x4BC++0x01 line.word 0x00 "RESIN606,ADC0_HWTRG13 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT21,OUT0,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x4BE++0x01 line.word 0x00 "RESIN607,BT_ADTO_13A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4C0++0x01 line.word 0x00 "RESIN608,BT_ADTO_13B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4C2++0x01 line.word 0x00 "RESIN609,BT_ADTO_13C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x4C4++0x01 line.word 0x00 "RESIN610,BT_ADTO_13D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x4C6++0x01 line.word 0x00 "RESIN611,ADC0_HWTRG14 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT2_UFSET,RLT3_UFSET,OUT0,OUT1,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x4C8++0x01 line.word 0x00 "RESIN612,BT_ADTO_14A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4CA++0x01 line.word 0x00 "RESIN613,BT_ADTO_14B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4CC++0x01 line.word 0x00 "RESIN614,BT_ADTO_14C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x4CE++0x01 line.word 0x00 "RESIN615,BT_ADTO_14D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x4D0++0x01 line.word 0x00 "RESIN616,ADC0_HWTRG15 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT3_UFSET,RLT16_UFSET,OUT1,OUT2,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x4D2++0x01 line.word 0x00 "RESIN617,BT_ADTO_15A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4D4++0x01 line.word 0x00 "RESIN618,BT_ADTO_15B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4D6++0x01 line.word 0x00 "RESIN619,BT_ADTO_15C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x4D8++0x01 line.word 0x00 "RESIN620,BT_ADTO_15D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x4DA++0x01 line.word 0x00 "RESIN621,ADC0_HWTRG16 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OUT2,OUT3,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x4DC++0x01 line.word 0x00 "RESIN622,BT_ADTO_16A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4DE++0x01 line.word 0x00 "RESIN623,BT_ADTO_16B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4E0++0x01 line.word 0x00 "RESIN624,BT_ADTO_16C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x4E2++0x01 line.word 0x00 "RESIN625,BT_ADTO_16D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x4E4++0x01 line.word 0x00 "RESIN626,ADC0_HWTRG17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OUT3,OUT4,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x4E6++0x01 line.word 0x00 "RESIN627,BT_ADTO_17A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4E8++0x01 line.word 0x00 "RESIN628,BT_ADTO_17B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4EA++0x01 line.word 0x00 "RESIN629,BT_ADTO_17C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x4EC++0x01 line.word 0x00 "RESIN630,BT_ADTO_17D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x4EE++0x01 line.word 0x00 "RESIN631,ADC0_HWTRG18 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT4,OUT5,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x4F0++0x01 line.word 0x00 "RESIN632,BT_ADTO_18A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4F2++0x01 line.word 0x00 "RESIN633,BT_ADTO_18B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4F4++0x01 line.word 0x00 "RESIN634,BT_ADTO_18C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x4F6++0x01 line.word 0x00 "RESIN635,BT_ADTO_18D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x4F8++0x01 line.word 0x00 "RESIN636,ADC0_HWTRG19 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT5,OUT0,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x4FA++0x01 line.word 0x00 "RESIN637,BT_ADTO_19A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x4FC++0x01 line.word 0x00 "RESIN638,BT_ADTO_19B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x4FE++0x01 line.word 0x00 "RESIN639,BT_ADTO_19C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x500++0x01 line.word 0x00 "RESIN640,BT_ADTO_19D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x502++0x01 line.word 0x00 "RESIN641,ADC0_HWTRG20 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT2_UFSET,RLT3_UFSET,OUT0,OUT1,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x504++0x01 line.word 0x00 "RESIN642,BT_ADTO_20A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x506++0x01 line.word 0x00 "RESIN643,BT_ADTO_20B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x508++0x01 line.word 0x00 "RESIN644,BT_ADTO_20C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x50A++0x01 line.word 0x00 "RESIN645,BT_ADTO_20D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x50C++0x01 line.word 0x00 "RESIN646,ADC0_HWTRG21 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT3_UFSET,RLT16_UFSET,OUT1,OUT16,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x50E++0x01 line.word 0x00 "RESIN647,BT_ADTO_21A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x510++0x01 line.word 0x00 "RESIN648,BT_ADTO_21B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x512++0x01 line.word 0x00 "RESIN649,BT_ADTO_21C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x514++0x01 line.word 0x00 "RESIN650,BT_ADTO_21D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x516++0x01 line.word 0x00 "RESIN651,ADC0_HWTRG22 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OUT16,OUT17,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x518++0x01 line.word 0x00 "RESIN652,BT_ADTO_22A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x51A++0x01 line.word 0x00 "RESIN653,BT_ADTO_22B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x51C++0x01 line.word 0x00 "RESIN654,BT_ADTO_22C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x51E++0x01 line.word 0x00 "RESIN655,BT_ADTO_22D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x520++0x01 line.word 0x00 "RESIN656,ADC0_HWTRG23 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OUT17,OUT18,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x522++0x01 line.word 0x00 "RESIN657,BT_ADTO_23A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x524++0x01 line.word 0x00 "RESIN658,BT_ADTO_23B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x526++0x01 line.word 0x00 "RESIN659,BT_ADTO_23C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x528++0x01 line.word 0x00 "RESIN660,BT_ADTO_23D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x52A++0x01 line.word 0x00 "RESIN661,ADC0_HWTRG24 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT18,OUT19,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x52C++0x01 line.word 0x00 "RESIN662,BT_ADTO_24A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x52E++0x01 line.word 0x00 "RESIN663,BT_ADTO_24B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x530++0x01 line.word 0x00 "RESIN664,BT_ADTO_24C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x532++0x01 line.word 0x00 "RESIN665,BT_ADTO_24D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x534++0x01 line.word 0x00 "RESIN666,ADC0_HWTRG25 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT19,OUT20,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x536++0x01 line.word 0x00 "RESIN667,BT_ADTO_25A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x538++0x01 line.word 0x00 "RESIN668,BT_ADTO_25B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x53A++0x01 line.word 0x00 "RESIN669,BT_ADTO_25C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x53C++0x01 line.word 0x00 "RESIN670,BT_ADTO_25D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x53E++0x01 line.word 0x00 "RESIN671,ADC0_HWTRG26 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT2_UFSET,RLT3_UFSET,OUT20,OUT21,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x540++0x01 line.word 0x00 "RESIN672,BT_ADTO_26A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x542++0x01 line.word 0x00 "RESIN673,BT_ADTO_26B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x544++0x01 line.word 0x00 "RESIN674,BT_ADTO_26C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x546++0x01 line.word 0x00 "RESIN675,BT_ADTO_26D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x548++0x01 line.word 0x00 "RESIN676,ADC0_HWTRG27 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT3_UFSET,RLT16_UFSET,OUT21,OUT0,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x54A++0x01 line.word 0x00 "RESIN677,BT_ADTO_27A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x54C++0x01 line.word 0x00 "RESIN678,BT_ADTO_27B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x54E++0x01 line.word 0x00 "RESIN679,BT_ADTO_27C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x550++0x01 line.word 0x00 "RESIN680,BT_ADTO_27D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x552++0x01 line.word 0x00 "RESIN681,ADC0_HWTRG28 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OUT0,OUT1,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x554++0x01 line.word 0x00 "RESIN682,BT_ADTO_28A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x556++0x01 line.word 0x00 "RESIN683,BT_ADTO_28B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x558++0x01 line.word 0x00 "RESIN684,BT_ADTO_28C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x55A++0x01 line.word 0x00 "RESIN685,BT_ADTO_28D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x55C++0x01 line.word 0x00 "RESIN686,ADC0_HWTRG29 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OUT1,OUT2,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x55E++0x01 line.word 0x00 "RESIN687,BT_ADTO_29A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x560++0x01 line.word 0x00 "RESIN688,BT_ADTO_29B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x562++0x01 line.word 0x00 "RESIN689,BT_ADTO_29C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x564++0x01 line.word 0x00 "RESIN690,BT_ADTO_29D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x566++0x01 line.word 0x00 "RESIN691,ADC0_HWTRG30 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT2,OUT3,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x568++0x01 line.word 0x00 "RESIN692,BT_ADTO_30A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x56A++0x01 line.word 0x00 "RESIN693,BT_ADTO_30B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x56C++0x01 line.word 0x00 "RESIN694,BT_ADTO_30C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x56E++0x01 line.word 0x00 "RESIN695,BT_ADTO_30D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x570++0x01 line.word 0x00 "RESIN696,ADC0_HWTRG31 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT3,OUT4,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x572++0x01 line.word 0x00 "RESIN697,BT_ADTO_31A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x574++0x01 line.word 0x00 "RESIN698,BT_ADTO_31B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x576++0x01 line.word 0x00 "RESIN699,BT_ADTO_31C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x578++0x01 line.word 0x00 "RESIN700,BT_ADTO_31D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x57A++0x01 line.word 0x00 "RESIN701,ADC1_HWTRG0 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT4,OUT5,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x57C++0x01 line.word 0x00 "RESIN702,BT_ADTO_0A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x57E++0x01 line.word 0x00 "RESIN703,BT_ADTO_0B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x580++0x01 line.word 0x00 "RESIN704,BT_ADTO_0C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x582++0x01 line.word 0x00 "RESIN705,BT_ADTO_0D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x584++0x01 line.word 0x00 "RESIN706,ADC1_HWTRG1 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT5,OUT0,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x586++0x01 line.word 0x00 "RESIN707,BT_ADTO_1A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x588++0x01 line.word 0x00 "RESIN708,BT_ADTO_1B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x58A++0x01 line.word 0x00 "RESIN709,BT_ADTO_1C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x58C++0x01 line.word 0x00 "RESIN710,BT_ADTO_1D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x58E++0x01 line.word 0x00 "RESIN711,ADC1_HWTRG2 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT2_UFSET,RLT3_UFSET,OUT0,OUT1,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x590++0x01 line.word 0x00 "RESIN712,BT_ADTO_2A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x592++0x01 line.word 0x00 "RESIN713,BT_ADTO_2B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x594++0x01 line.word 0x00 "RESIN714,BT_ADTO_2C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x596++0x01 line.word 0x00 "RESIN715,BT_ADTO_2D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x598++0x01 line.word 0x00 "RESIN716,ADC1_HWTRG3 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT3_UFSET,RLT16_UFSET,OUT1,OUT16,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x59A++0x01 line.word 0x00 "RESIN717,BT_ADTO_3A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x59C++0x01 line.word 0x00 "RESIN718,BT_ADTO_3B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x59E++0x01 line.word 0x00 "RESIN719,BT_ADTO_3C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x5A0++0x01 line.word 0x00 "RESIN720,BT_ADTO_3D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x5A2++0x01 line.word 0x00 "RESIN721,ADC1_HWTRG4 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OUT16,OUT17,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x5A4++0x01 line.word 0x00 "RESIN722,BT_ADTO_4A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5A6++0x01 line.word 0x00 "RESIN723,BT_ADTO_4B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5A8++0x01 line.word 0x00 "RESIN724,BT_ADTO_4C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x5AA++0x01 line.word 0x00 "RESIN725,BT_ADTO_4D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x5AC++0x01 line.word 0x00 "RESIN726,ADC1_HWTRG5 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OUT17,OUT18,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x5AE++0x01 line.word 0x00 "RESIN727,BT_ADTO_5A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5B0++0x01 line.word 0x00 "RESIN728,BT_ADTO_5B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5B2++0x01 line.word 0x00 "RESIN729,BT_ADTO_5C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x5B4++0x01 line.word 0x00 "RESIN730,BT_ADTO_5D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x5B6++0x01 line.word 0x00 "RESIN731,ADC1_HWTRG6 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT18,OUT19,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x5B8++0x01 line.word 0x00 "RESIN732,BT_ADTO_6A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5BA++0x01 line.word 0x00 "RESIN733,BT_ADTO_6B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5BC++0x01 line.word 0x00 "RESIN734,BT_ADTO_6C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x5BE++0x01 line.word 0x00 "RESIN735,BT_ADTO_6D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x5C0++0x01 line.word 0x00 "RESIN736,ADC1_HWTRG7 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT19,OUT20,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x5C2++0x01 line.word 0x00 "RESIN737,BT_ADTO_7A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5C4++0x01 line.word 0x00 "RESIN738,BT_ADTO_7B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5C6++0x01 line.word 0x00 "RESIN739,BT_ADTO_7C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x5C8++0x01 line.word 0x00 "RESIN740,BT_ADTO_7D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x5CA++0x01 line.word 0x00 "RESIN741,ADC1_HWTRG8 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT2_UFSET,RLT3_UFSET,OUT20,OUT21,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x5CC++0x01 line.word 0x00 "RESIN742,BT_ADTO_8A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5CE++0x01 line.word 0x00 "RESIN743,BT_ADTO_8B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5D0++0x01 line.word 0x00 "RESIN744,BT_ADTO_8C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x5D2++0x01 line.word 0x00 "RESIN745,BT_ADTO_8D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x5D4++0x01 line.word 0x00 "RESIN746,ADC1_HWTRG9 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT3_UFSET,RLT16_UFSET,OUT21,OUT0,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x5D6++0x01 line.word 0x00 "RESIN747,BT_ADTO_9A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5D8++0x01 line.word 0x00 "RESIN748,BT_ADTO_9B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5DA++0x01 line.word 0x00 "RESIN749,BT_ADTO_9C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x5DC++0x01 line.word 0x00 "RESIN750,BT_ADTO_9D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x5DE++0x01 line.word 0x00 "RESIN751,ADC1_HWTRG10 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OUT0,OUT1,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x5E0++0x01 line.word 0x00 "RESIN752,BT_ADTO_10A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5E2++0x01 line.word 0x00 "RESIN753,BT_ADTO_10B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5E4++0x01 line.word 0x00 "RESIN754,BT_ADTO_10C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x5E6++0x01 line.word 0x00 "RESIN755,BT_ADTO_10D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x5E8++0x01 line.word 0x00 "RESIN756,ADC1_HWTRG11 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OUT1,OUT2,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x5EA++0x01 line.word 0x00 "RESIN757,BT_ADTO_11A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5EC++0x01 line.word 0x00 "RESIN758,BT_ADTO_11B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5EE++0x01 line.word 0x00 "RESIN759,BT_ADTO_11C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x5F0++0x01 line.word 0x00 "RESIN760,BT_ADTO_11D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x5F2++0x01 line.word 0x00 "RESIN761,ADC1_HWTRG12 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT2,OUT3,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x5F4++0x01 line.word 0x00 "RESIN762,BT_ADTO_12A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x5F6++0x01 line.word 0x00 "RESIN763,BT_ADTO_12B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x5F8++0x01 line.word 0x00 "RESIN764,BT_ADTO_12C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x5FA++0x01 line.word 0x00 "RESIN765,BT_ADTO_12D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x5FC++0x01 line.word 0x00 "RESIN766,ADC1_HWTRG13 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT3,OUT4,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x5FE++0x01 line.word 0x00 "RESIN767,BT_ADTO_13A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x600++0x01 line.word 0x00 "RESIN768,BT_ADTO_13B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x602++0x01 line.word 0x00 "RESIN769,BT_ADTO_13C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x604++0x01 line.word 0x00 "RESIN770,BT_ADTO_13D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x606++0x01 line.word 0x00 "RESIN771,ADC1_HWTRG14 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT2_UFSET,RLT3_UFSET,OUT4,OUT5,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x608++0x01 line.word 0x00 "RESIN772,BT_ADTO_14A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x60A++0x01 line.word 0x00 "RESIN773,BT_ADTO_14B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x60C++0x01 line.word 0x00 "RESIN774,BT_ADTO_14C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x60E++0x01 line.word 0x00 "RESIN775,BT_ADTO_14D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x610++0x01 line.word 0x00 "RESIN776,ADC1_HWTRG15 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT3_UFSET,RLT16_UFSET,OUT5,OUT0,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x612++0x01 line.word 0x00 "RESIN777,BT_ADTO_15A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x614++0x01 line.word 0x00 "RESIN778,BT_ADTO_15B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x616++0x01 line.word 0x00 "RESIN779,BT_ADTO_15C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x618++0x01 line.word 0x00 "RESIN780,BT_ADTO_15D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x61A++0x01 line.word 0x00 "RESIN781,ADC1_HWTRG16 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OUT0,OUT1,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x61C++0x01 line.word 0x00 "RESIN782,BT_ADTO_16A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x61E++0x01 line.word 0x00 "RESIN783,BT_ADTO_16B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x620++0x01 line.word 0x00 "RESIN784,BT_ADTO_16C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x622++0x01 line.word 0x00 "RESIN785,BT_ADTO_16D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x624++0x01 line.word 0x00 "RESIN786,ADC1_HWTRG17 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OUT1,OUT16,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x626++0x01 line.word 0x00 "RESIN787,BT_ADTO_17A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x628++0x01 line.word 0x00 "RESIN788,BT_ADTO_17B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x62A++0x01 line.word 0x00 "RESIN789,BT_ADTO_17C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x62C++0x01 line.word 0x00 "RESIN790,BT_ADTO_17D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x62E++0x01 line.word 0x00 "RESIN791,ADC1_HWTRG18 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT16,OUT17,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x630++0x01 line.word 0x00 "RESIN792,BT_ADTO_18A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x632++0x01 line.word 0x00 "RESIN793,BT_ADTO_18B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x634++0x01 line.word 0x00 "RESIN794,BT_ADTO_18C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x636++0x01 line.word 0x00 "RESIN795,BT_ADTO_18D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x638++0x01 line.word 0x00 "RESIN796,ADC1_HWTRG19 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT17,OUT18,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x63A++0x01 line.word 0x00 "RESIN797,BT_ADTO_19A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x63C++0x01 line.word 0x00 "RESIN798,BT_ADTO_19B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x63E++0x01 line.word 0x00 "RESIN799,BT_ADTO_19C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x640++0x01 line.word 0x00 "RESIN800,BT_ADTO_19D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x642++0x01 line.word 0x00 "RESIN801,ADC1_HWTRG20 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT2_UFSET,RLT3_UFSET,OUT18,OUT19,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x644++0x01 line.word 0x00 "RESIN802,BT_ADTO_20A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x646++0x01 line.word 0x00 "RESIN803,BT_ADTO_20B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x648++0x01 line.word 0x00 "RESIN804,BT_ADTO_20C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x64A++0x01 line.word 0x00 "RESIN805,BT_ADTO_20D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x64C++0x01 line.word 0x00 "RESIN806,ADC1_HWTRG21 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT3_UFSET,RLT16_UFSET,OUT19,OUT20,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x64E++0x01 line.word 0x00 "RESIN807,BT_ADTO_21A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x650++0x01 line.word 0x00 "RESIN808,BT_ADTO_21B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x652++0x01 line.word 0x00 "RESIN809,BT_ADTO_21C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x654++0x01 line.word 0x00 "RESIN810,BT_ADTO_21D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x656++0x01 line.word 0x00 "RESIN811,ADC1_HWTRG22 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OUT20,OUT21,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x658++0x01 line.word 0x00 "RESIN812,BT_ADTO_22A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x65A++0x01 line.word 0x00 "RESIN813,BT_ADTO_22B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x65C++0x01 line.word 0x00 "RESIN814,BT_ADTO_22C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x65E++0x01 line.word 0x00 "RESIN815,BT_ADTO_22D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x660++0x01 line.word 0x00 "RESIN816,ADC1_HWTRG23 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OUT21,OUT0,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x662++0x01 line.word 0x00 "RESIN817,BT_ADTO_23A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x664++0x01 line.word 0x00 "RESIN818,BT_ADTO_23B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x666++0x01 line.word 0x00 "RESIN819,BT_ADTO_23C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x668++0x01 line.word 0x00 "RESIN820,BT_ADTO_23D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x66A++0x01 line.word 0x00 "RESIN821,ADC1_HWTRG24 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT0,OUT1,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x66C++0x01 line.word 0x00 "RESIN822,BT_ADTO_24A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x66E++0x01 line.word 0x00 "RESIN823,BT_ADTO_24B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x670++0x01 line.word 0x00 "RESIN824,BT_ADTO_24C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x672++0x01 line.word 0x00 "RESIN825,BT_ADTO_24D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x674++0x01 line.word 0x00 "RESIN826,ADC1_HWTRG25 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT1,OUT2,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x676++0x01 line.word 0x00 "RESIN827,BT_ADTO_25A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x678++0x01 line.word 0x00 "RESIN828,BT_ADTO_25B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x67A++0x01 line.word 0x00 "RESIN829,BT_ADTO_25C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x67C++0x01 line.word 0x00 "RESIN830,BT_ADTO_25D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x67E++0x01 line.word 0x00 "RESIN831,ADC1_HWTRG26 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT2_UFSET,RLT3_UFSET,OUT2,OUT3,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x680++0x01 line.word 0x00 "RESIN832,BT_ADTO_26A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x682++0x01 line.word 0x00 "RESIN833,BT_ADTO_26B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x684++0x01 line.word 0x00 "RESIN834,BT_ADTO_26C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x686++0x01 line.word 0x00 "RESIN835,BT_ADTO_26D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x688++0x01 line.word 0x00 "RESIN836,ADC1_HWTRG27 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT3_UFSET,RLT16_UFSET,OUT3,OUT4,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x68A++0x01 line.word 0x00 "RESIN837,BT_ADTO_27A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x68C++0x01 line.word 0x00 "RESIN838,BT_ADTO_27B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x68E++0x01 line.word 0x00 "RESIN839,BT_ADTO_27C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x690++0x01 line.word 0x00 "RESIN840,BT_ADTO_27D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x692++0x01 line.word 0x00 "RESIN841,ADC1_HWTRG28 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT16_UFSET,RLT17_UFSET,OUT4,OUT5,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x694++0x01 line.word 0x00 "RESIN842,BT_ADTO_28A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x696++0x01 line.word 0x00 "RESIN843,BT_ADTO_28B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x698++0x01 line.word 0x00 "RESIN844,BT_ADTO_28C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x69A++0x01 line.word 0x00 "RESIN845,BT_ADTO_28D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x69C++0x01 line.word 0x00 "RESIN846,ADC1_HWTRG29 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT17_UFSET,RLT0_UFSET,OUT5,OUT0,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x69E++0x01 line.word 0x00 "RESIN847,BT_ADTO_29A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x6A0++0x01 line.word 0x00 "RESIN848,BT_ADTO_29B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x6A2++0x01 line.word 0x00 "RESIN849,BT_ADTO_29C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x6A4++0x01 line.word 0x00 "RESIN850,BT_ADTO_29D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x6A6++0x01 line.word 0x00 "RESIN851,ADC1_HWTRG30 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT0_UFSET,RLT1_UFSET,OUT0,OUT1,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x6A8++0x01 line.word 0x00 "RESIN852,BT_ADTO_30A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x6AA++0x01 line.word 0x00 "RESIN853,BT_ADTO_30B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x6AC++0x01 line.word 0x00 "RESIN854,BT_ADTO_30C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x6AE++0x01 line.word 0x00 "RESIN855,BT_ADTO_30D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x6B0++0x01 line.word 0x00 "RESIN856,ADC1_HWTRG31 Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "PORT_PIN,RLT1_UFSET,RLT2_UFSET,OUT1,OUT16,BT_ADTO_A,BT_ADTO_B,BT_ADTO_C,BT_ADTO_D,?..." group.word 0x6B2++0x01 line.word 0x00 "RESIN857,BT_ADTO_31A Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_ADTO,BT1_ADTO,BT2_ADTO,BT3_ADTO,BT4_ADTO,BT5_ADTO,BT6_ADTO,BT7_ADTO,BT8_ADTO,BT9_ADTO,BT10_ADTO,BT11_ADTO,BT12_ADTO,BT13_ADTO,BT14_ADTO,BT15_ADTO" group.word 0x6B4++0x01 line.word 0x00 "RESIN858,BT_ADTO_31B Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_ADTO,BT17_ADTO,BT18_ADTO,BT19_ADTO,BT20_ADTO,BT21_ADTO,BT22_ADTO,BT23_ADTO,BT24_ADTO,BT25_ADTO,BT26_ADTO,BT27_ADTO,BT28_ADTO,BT29_ADTO,BT30_ADTO,BT31_ADTO" group.word 0x6B6++0x01 line.word 0x00 "RESIN859,BT_ADTO_31C Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT32_ADTO,BT33_ADTO,BT34_ADTO,BT35_ADTO,BT36_ADTO,BT37_ADTO,BT38_ADTO,BT39_ADTO,BT40_ADTO,BT41_ADTO,BT42_ADTO,BT43_ADTO,BT44_ADTO,BT45_ADTO,BT46_ADTO,BT47_ADTO" group.word 0x6B8++0x01 line.word 0x00 "RESIN860,BT_ADTO_31D Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT48_ADTO,BT49_ADTO,BT50_ADTO,BT51_ADTO,BT52_ADTO,BT53_ADTO,BT54_ADTO,BT55_ADTO,BT56_ADTO,BT57_ADTO,BT58_ADTO,BT59_ADTO,BT60_ADTO,BT61_ADTO,BT62_ADTO,BT63_ADTO" width 0x0B width 10. group.word 0x6BA++0x01 line.word 0x00 "RESIN861,DMA[0] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Ext_IRQ_0 ,Ext_IRQ_8,Ext_IRQ_16,Ext_IRQ_24,?..." group.word 0x6BC++0x01 line.word 0x00 "RESIN862,DMA[1] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Ext_IRQ_1 ,Ext_IRQ_9,Ext_IRQ_17,Ext_IRQ_25,?..." group.word 0x6BE++0x01 line.word 0x00 "RESIN863,DMA[2] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Ext_IRQ_2 ,Ext_IRQ_10,Ext_IRQ_18,Ext_IRQ_26,?..." group.word 0x6C0++0x01 line.word 0x00 "RESIN864,DMA[3] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Ext_IRQ_3 ,Ext_IRQ_11,Ext_IRQ_19,Ext_IRQ_27,?..." group.word 0x6C2++0x01 line.word 0x00 "RESIN865,DMA[4] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Ext_IRQ_4 ,Ext_IRQ_12,Ext_IRQ_20,Ext_IRQ_28,?..." group.word 0x6C4++0x01 line.word 0x00 "RESIN866,DMA[5] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Ext_IRQ_5 ,Ext_IRQ_13,Ext_IRQ_21,Ext_IRQ_29,?..." group.word 0x6C6++0x01 line.word 0x00 "RESIN867,DMA[6] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Ext_IRQ_6 ,Ext_IRQ_14,Ext_IRQ_22,Ext_IRQ_30,?..." group.word 0x6C8++0x01 line.word 0x00 "RESIN868,DMA[7] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "Ext_IRQ_7 ,Ext_IRQ_15,Ext_IRQ_23,Ext_IRQ_31,?..." group.word 0x6CA++0x01 line.word 0x00 "RESIN869,DMA[56] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT0_IRQ-0,BT0-IRQ-1,BT24_IRQ-0,BT24_IRQ-1,BT48_IRQ-0,BT48_IRQ-1,?..." group.word 0x6CC++0x01 line.word 0x00 "RESIN870,DMA[57] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT1_IRQ-0,BT1-IRQ-1,BT25_IRQ-0,BT25_IRQ-1,BT49_IRQ-0,BT49_IRQ-1,?..." group.word 0x6CE++0x01 line.word 0x00 "RESIN871,DMA[58] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT2_IRQ-0,BT2-IRQ-1,BT26_IRQ-0,BT26_IRQ-1,BT50_IRQ-0,BT50_IRQ-1,?..." group.word 0x6D0++0x01 line.word 0x00 "RESIN872,DMA[59] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT3_IRQ-0,BT3-IRQ-1,BT27_IRQ-0,BT27_IRQ-1,BT51_IRQ-0,BT51_IRQ-1,?..." group.word 0x6D2++0x01 line.word 0x00 "RESIN873,DMA[60] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT4_IRQ-0,BT4-IRQ-1,BT28_IRQ-0,BT28_IRQ-1,BT52_IRQ-0,BT52_IRQ-1,?..." group.word 0x6D4++0x01 line.word 0x00 "RESIN874,DMA[61] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT5_IRQ-0,BT5-IRQ-1,BT29_IRQ-0,BT29_IRQ-1,BT53_IRQ-0,BT53_IRQ-1,?..." group.word 0x6D6++0x01 line.word 0x00 "RESIN875,DMA[62] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT6_IRQ-0,BT6-IRQ-1,BT30_IRQ-0,BT30_IRQ-1,BT54_IRQ-0,BT54_IRQ-1,?..." group.word 0x6D8++0x01 line.word 0x00 "RESIN876,DMA[63] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT7_IRQ-0,BT7-IRQ-1,BT31_IRQ-0,BT31_IRQ-1,BT55_IRQ-0,BT55_IRQ-1,?..." group.word 0x6DA++0x01 line.word 0x00 "RESIN877,DMA[64] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT8_IRQ-0,BT8-IRQ-1,BT32_IRQ-0,BT32_IRQ-1,BT56_IRQ-0,BT56_IRQ-1,?..." group.word 0x6DC++0x01 line.word 0x00 "RESIN878,DMA[65] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT9_IRQ-0,BT9-IRQ-1,BT33_IRQ-0,BT33_IRQ-1,BT57_IRQ-0,BT57_IRQ-1,?..." group.word 0x6DE++0x01 line.word 0x00 "RESIN879,DMA[66] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT10_IRQ-0,BT10-IRQ-1,BT34_IRQ-0,BT34_IRQ-1,BT58_IRQ-0,BT58_IRQ-1,?..." group.word 0x6E0++0x01 line.word 0x00 "RESIN880,DMA[67] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT11_IRQ-0,BT11-IRQ-1,BT35_IRQ-0,BT35_IRQ-1,BT59_IRQ-0,BT59_IRQ-1,?..." group.word 0x6E2++0x01 line.word 0x00 "RESIN881,DMA[68] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT12_IRQ-0,BT12-IRQ-1,BT36_IRQ-0,BT36_IRQ-1,BT60_IRQ-0,BT60_IRQ-1,?..." group.word 0x6E4++0x01 line.word 0x00 "RESIN882,DMA[69] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT13_IRQ-0,BT13-IRQ-1,BT37_IRQ-0,BT37_IRQ-1,BT61_IRQ-0,BT61_IRQ-1,?..." group.word 0x6E6++0x01 line.word 0x00 "RESIN883,DMA[70] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT14_IRQ-0,BT14-IRQ-1,BT38_IRQ-0,BT38_IRQ-1,BT62_IRQ-0,BT62_IRQ-1,?..." group.word 0x6E8++0x01 line.word 0x00 "RESIN884,DMA[71] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT15_IRQ-0,BT15-IRQ-1,BT39_IRQ-0,BT39_IRQ-1,BT63_IRQ-0,BT63_IRQ-1,?..." group.word 0x6EA++0x01 line.word 0x00 "RESIN885,DMA[72] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT16_IRQ-0,BT16-IRQ-1,BT40_IRQ-0,BT40_IRQ-1,?..." group.word 0x6EC++0x01 line.word 0x00 "RESIN886,DMA[73] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT17_IRQ-0,BT17-IRQ-1,BT41_IRQ-0,BT41_IRQ-1,?..." group.word 0x6EE++0x01 line.word 0x00 "RESIN887,DMA[74] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT18_IRQ-0,BT18-IRQ-1,BT42_IRQ-0,BT42_IRQ-1,?..." group.word 0x6F0++0x01 line.word 0x00 "RESIN888,DMA[75] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT19_IRQ-0,BT19-IRQ-1,BT43_IRQ-0,BT43_IRQ-1,?..." group.word 0x6F2++0x01 line.word 0x00 "RESIN889,DMA[76] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT20_IRQ-0,BT20-IRQ-1,BT44_IRQ-0,BT44_IRQ-1,?..." group.word 0x6F4++0x01 line.word 0x00 "RESIN890,DMA[77] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT21_IRQ-0,BT21-IRQ-1,BT45_IRQ-0,BT45_IRQ-1,?..." group.word 0x6F6++0x01 line.word 0x00 "RESIN891,DMA[78] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT22_IRQ-0,BT22-IRQ-1,BT46_IRQ-0,BT46_IRQ-1,?..." group.word 0x6F8++0x01 line.word 0x00 "RESIN892,DMA[79] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "BT23_IRQ-0,BT23-IRQ-1,BT47_IRQ-0,BT47_IRQ-1,?..." group.word 0x6FA++0x1D line.word 0x00 "RESIN893,DMA[80] Resource Input Setting Register" bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0_Match,FRT0_Zero,FRT2_Match,FRT2_Zero,FRT4_Match,FRT4_Zero,?..." line.word 0x02 "RESIN894,DMA[81] Resource Input Setting Register" bitfld.word 0x02 0.--3. " RESSEL ,Resource selection bit" "FRT1_Match,FRT1_Zero,FRT3_Match,FRT3_Zero,?..." line.word 0x04 "RESIN895,DMA[82] Resource Input Setting Register" bitfld.word 0x04 0.--3. " RESSEL ,Resource selection bit" "FRT8_Match,FRT8_Zero,FRT10_Match,FRT10_Zero,?..." line.word 0x06 "RESIN896,DMA[83] Resource Input Setting Register" bitfld.word 0x06 0.--3. " RESSEL ,Resource selection bit" "FRT9_Match,FRT9_Zero,?..." line.word 0x08 "RESIN897,DMA[84] Resource Input Setting Register" bitfld.word 0x08 0.--3. " RESSEL ,Resource selection bit" "ICU_IRQ0,ICU2_IRQ0,ICU4_IRQ0,?..." line.word 0x0A "RESIN898,DMA[84] Resource Input Setting Register" bitfld.word 0x0A 0.--3. " RESSEL ,Resource selection bit" "ICU16_IRQ0,ICU18_IRQ0,ICU20_IRQ0,?..." line.word 0x0C "RESIN899,DMA[86] Resource Input Setting Register" bitfld.word 0x0C 0.--3. " RESSEL ,Resource selection bit" "ICU1_IRQ0,ICU3_IRQ0,ICU5_IR0Q,?..." line.word 0x0E "RESIN900,DMA[87] Resource Input Setting Register" bitfld.word 0x0E 0.--3. " RESSEL ,Resource selection bit" "ICU17_IRQ1,ICU19_IRQ1,ICU21_IRQ1,?..." line.word 0x10 "RESIN901,DMA[88] Resource Input Setting Register" bitfld.word 0x10 0.--3. " RESSEL ,Resource selection bit" "OCU0_IRQ0,OCU2_IRQ0,OCU4_IRQ0,?..." line.word 0x12 "RESIN902,DMA[89] Resource Input Setting Register" bitfld.word 0x12 0.--3. " RESSEL ,Resource selection bit" "OCU16_IRQ0,OCU18_IRQ0,OCU20_IRQ0,?..." line.word 0x14 "RESIN903,DMA[90] Resource Input Setting Register" bitfld.word 0x14 0.--3. " RESSEL ,Resource selection bit" "OCU1_IRQ0,OCU3_IRQ0,OCU5_IRQ0,?..." line.word 0x16 "RESIN904,DMA[91] Resource Input Setting Register" bitfld.word 0x16 0.--3. " RESSEL ,Resource selection bit" "OCU17_IRQ0,OCU19_IRQ0,OCU21_IRQ0,?..." line.word 0x18 "RESIN905,DMA[92] Resource Input Setting Register" bitfld.word 0x18 0.--3. " RESSEL ,Resource selection bit" "RLT0_IRQ,RLT2_IRQ,RLT16_IRQ,?..." line.word 0x1A "RESIN906,DMA[93] Resource Input Setting Register" bitfld.word 0x1A 0.--3. " RESSEL ,Resource selection bit" "RLT1_IRQ,RLT3_IRQ,RLT17_IRQ,?..." line.word 0x1C "RESIN907,DMA[94] Resource Input Setting Register" bitfld.word 0x1C 0.--3. " RESSEL ,Resource selection bit" "DMAC_RLT0,DMAC_RLT1,DMAC_RLT2,DMAC_RLT3,?..." width 0x0B tree.end tree.end tree "PPU (Peripheral Protection Unit)" base ad:0xB4750000 width 8. group.long 0x00++0x03 line.long 0x00 "CR,Control Register" bitfld.long 0x00 29. " MODE ,PPU mode bit" "R/W,R/A" bitfld.long 0x00 23. " VCLR ,PPU violation information clear" "No effect,Cleared" bitfld.long 0x00 9. " FPQSET ,PPU privilege mode forced change function quick set" "No effect,Set" bitfld.long 0x00 8. " FPQCLR ,PPU privilege mode forced change function quick clear" "No effect,Cleared" rgroup.long 0x04++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 23. " VD ,Violation detection bit" "Not generated,Generated" bitfld.long 0x00 22. " VP ,Violation privileged level bit" "User,Privilege" bitfld.long 0x00 21. " VW ,Violation write access bit" "Read,Write" bitfld.long 0x00 16.--20. " VL ,Violation location" ",MCU config,SYSC1,Memory config/Scratch pad RAM,CPERI0,CPERI1,CPERI2,EBI,SHE,DDRHSSPI,Application specific area 0,Application specific area 1,Application specific area 2,Application specific area 3,Application specific area 4,Application specific area 5,Application specific area 6,?..." newline bitfld.long 0x00 0. " LST ,Lock status bit" "Unlocked,Locked" group.long 0x08++0x03 line.long 0x00 "UNLOCK,Unlock Register" if ((per.l(ad:0xB4750000+0x04)&0x01)==0x00) group.long 0x0C++0x0F line.long 0x00 "WPQCLR,Privileged Write Attribute Quick Clear Register" bitfld.long 0x00 0. " WPQCLR ,PPU privileged write attribute quick clear" "No effect,Clear" line.long 0x04 "WUQCLR,User Write Attribute Quick Clear Register" bitfld.long 0x04 0. " WUQCLR ,PPU user write attribute quick clear" "No effect,Clear" line.long 0x08 "RPQCLR,Privileged Read Attribute Quick Clear Register" bitfld.long 0x08 0. " RPQCLR ,PPU privileged read attribute quick clear" "No effect,Clear" line.long 0x0C "RUQCLR,User Read Attribute Quick Clear Register" bitfld.long 0x0C 0. " RUQCLR ,PPU user read attribute quick clear" "No effect,Clear" newline group.long 0x80++0x03 line.long 0x00 "PPR0,Privileged Read Attribute Register 0" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x84++0x03 line.long 0x00 "PPR1,Privileged Read Attribute Register 1" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x88++0x03 line.long 0x00 "PPR2,Privileged Read Attribute Register 2" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x8C++0x03 line.long 0x00 "PPR3,Privileged Read Attribute Register 3" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x90++0x03 line.long 0x00 "PPR4,Privileged Read Attribute Register 4" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x94++0x03 line.long 0x00 "PPR5,Privileged Read Attribute Register 5" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "PPR6,Privileged Read Attribute Register 6" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x9C++0x03 line.long 0x00 "PPR7,Privileged Read Attribute Register 7" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xA0++0x03 line.long 0x00 "PPR8,Privileged Read Attribute Register 8" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xA4++0x03 line.long 0x00 "PPR9,Privileged Read Attribute Register 9" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xA8++0x03 line.long 0x00 "PPR10,Privileged Read Attribute Register 10" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xAC++0x03 line.long 0x00 "PPR11,Privileged Read Attribute Register 11" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xB0++0x03 line.long 0x00 "PPR12,Privileged Read Attribute Register 12" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xB4++0x03 line.long 0x00 "PPR13,Privileged Read Attribute Register 13" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xB8++0x03 line.long 0x00 "PPR14,Privileged Read Attribute Register 14" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xBC++0x03 line.long 0x00 "PPR15,Privileged Read Attribute Register 15" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xC0++0x03 line.long 0x00 "PPR16,Privileged Read Attribute Register 16" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xC4++0x03 line.long 0x00 "PPR17,Privileged Read Attribute Register 17" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xC8++0x03 line.long 0x00 "PPR18,Privileged Read Attribute Register 18" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xCC++0x03 line.long 0x00 "PPR19,Privileged Read Attribute Register 19" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xD0++0x03 line.long 0x00 "PPR20,Privileged Read Attribute Register 20" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xD4++0x03 line.long 0x00 "PPR21,Privileged Read Attribute Register 21" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xD8++0x03 line.long 0x00 "PPR22,Privileged Read Attribute Register 22" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xDC++0x03 line.long 0x00 "PPR23,Privileged Read Attribute Register 23" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xE0++0x03 line.long 0x00 "PPR24,Privileged Read Attribute Register 24" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xE4++0x03 line.long 0x00 "PPR25,Privileged Read Attribute Register 25" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xE8++0x03 line.long 0x00 "PPR26,Privileged Read Attribute Register 26" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xEC++0x03 line.long 0x00 "PPR27,Privileged Read Attribute Register 27" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xF0++0x03 line.long 0x00 "PPR28,Privileged Read Attribute Register 28" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0xF4++0x03 line.long 0x00 "PPR29,Privileged Read Attribute Register 29" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" group.long 0x100++0x03 line.long 0x00 "PUR0,User Read Attribute Register 0" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x104++0x03 line.long 0x00 "PUR1,User Read Attribute Register 1" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x108++0x03 line.long 0x00 "PUR2,User Read Attribute Register 2" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x10C++0x03 line.long 0x00 "PUR3,User Read Attribute Register 3" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x110++0x03 line.long 0x00 "PUR4,User Read Attribute Register 4" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x114++0x03 line.long 0x00 "PUR5,User Read Attribute Register 5" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x118++0x03 line.long 0x00 "PUR6,User Read Attribute Register 6" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x11C++0x03 line.long 0x00 "PUR7,User Read Attribute Register 7" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "PUR8,User Read Attribute Register 8" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x124++0x03 line.long 0x00 "PUR9,User Read Attribute Register 9" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x128++0x03 line.long 0x00 "PUR10,User Read Attribute Register 10" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x12C++0x03 line.long 0x00 "PUR11,User Read Attribute Register 11" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x130++0x03 line.long 0x00 "PUR12,User Read Attribute Register 12" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x134++0x03 line.long 0x00 "PUR13,User Read Attribute Register 13" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x138++0x03 line.long 0x00 "PUR14,User Read Attribute Register 14" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x13C++0x03 line.long 0x00 "PUR15,User Read Attribute Register 15" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x140++0x03 line.long 0x00 "PUR16,User Read Attribute Register 16" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x144++0x03 line.long 0x00 "PUR17,User Read Attribute Register 17" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x148++0x03 line.long 0x00 "PUR18,User Read Attribute Register 18" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "PUR19,User Read Attribute Register 19" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x150++0x03 line.long 0x00 "PUR20,User Read Attribute Register 20" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x154++0x03 line.long 0x00 "PUR21,User Read Attribute Register 21" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x158++0x03 line.long 0x00 "PUR22,User Read Attribute Register 22" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x15C++0x03 line.long 0x00 "PUR23,User Read Attribute Register 23" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x160++0x03 line.long 0x00 "PUR24,User Read Attribute Register 24" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x164++0x03 line.long 0x00 "PUR25,User Read Attribute Register 25" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x168++0x03 line.long 0x00 "PUR26,User Read Attribute Register 26" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x16C++0x03 line.long 0x00 "PUR27,User Read Attribute Register 27" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x170++0x03 line.long 0x00 "PUR28,User Read Attribute Register 28" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" group.long 0x174++0x03 line.long 0x00 "PUR29,User Read Attribute Register 29" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" newline group.long 0x180++0x03 line.long 0x00 "PPWA0,Privileged Write Or Access Attribute Register 0" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x184++0x03 line.long 0x00 "PPWA1,Privileged Write Or Access Attribute Register 1" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x188++0x03 line.long 0x00 "PPWA2,Privileged Write Or Access Attribute Register 2" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x18C++0x03 line.long 0x00 "PPWA3,Privileged Write Or Access Attribute Register 3" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x190++0x03 line.long 0x00 "PPWA4,Privileged Write Or Access Attribute Register 4" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x194++0x03 line.long 0x00 "PPWA5,Privileged Write Or Access Attribute Register 5" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x198++0x03 line.long 0x00 "PPWA6,Privileged Write Or Access Attribute Register 6" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x19C++0x03 line.long 0x00 "PPWA7,Privileged Write Or Access Attribute Register 7" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1A0++0x03 line.long 0x00 "PPWA8,Privileged Write Or Access Attribute Register 8" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1A4++0x03 line.long 0x00 "PPWA9,Privileged Write Or Access Attribute Register 9" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1A8++0x03 line.long 0x00 "PPWA10,Privileged Write Or Access Attribute Register 10" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1AC++0x03 line.long 0x00 "PPWA11,Privileged Write Or Access Attribute Register 11" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1B0++0x03 line.long 0x00 "PPWA12,Privileged Write Or Access Attribute Register 12" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1B4++0x03 line.long 0x00 "PPWA13,Privileged Write Or Access Attribute Register 13" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1B8++0x03 line.long 0x00 "PPWA14,Privileged Write Or Access Attribute Register 14" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1BC++0x03 line.long 0x00 "PPWA15,Privileged Write Or Access Attribute Register 15" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1C0++0x03 line.long 0x00 "PPWA16,Privileged Write Or Access Attribute Register 16" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1C4++0x03 line.long 0x00 "PPWA17,Privileged Write Or Access Attribute Register 17" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1C8++0x03 line.long 0x00 "PPWA18,Privileged Write Or Access Attribute Register 18" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1CC++0x03 line.long 0x00 "PPWA19,Privileged Write Or Access Attribute Register 19" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1D0++0x03 line.long 0x00 "PPWA20,Privileged Write Or Access Attribute Register 20" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1D4++0x03 line.long 0x00 "PPWA21,Privileged Write Or Access Attribute Register 21" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1D8++0x03 line.long 0x00 "PPWA22,Privileged Write Or Access Attribute Register 22" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1DC++0x03 line.long 0x00 "PPWA23,Privileged Write Or Access Attribute Register 23" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1E0++0x03 line.long 0x00 "PPWA24,Privileged Write Or Access Attribute Register 24" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1E4++0x03 line.long 0x00 "PPWA25,Privileged Write Or Access Attribute Register 25" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1E8++0x03 line.long 0x00 "PPWA26,Privileged Write Or Access Attribute Register 26" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1EC++0x03 line.long 0x00 "PPWA27,Privileged Write Or Access Attribute Register 27" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1F0++0x03 line.long 0x00 "PPWA28,Privileged Write Or Access Attribute Register 28" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x1F4++0x03 line.long 0x00 "PPWA29,Privileged Write Or Access Attribute Register 29" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" group.long 0x200++0x03 line.long 0x00 "PUWA0,User Write Or Access Attribute Register 0" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x204++0x03 line.long 0x00 "PUWA1,User Write Or Access Attribute Register 1" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x208++0x03 line.long 0x00 "PUWA2,User Write Or Access Attribute Register 2" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x20C++0x03 line.long 0x00 "PUWA3,User Write Or Access Attribute Register 3" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x210++0x03 line.long 0x00 "PUWA4,User Write Or Access Attribute Register 4" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x214++0x03 line.long 0x00 "PUWA5,User Write Or Access Attribute Register 5" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x218++0x03 line.long 0x00 "PUWA6,User Write Or Access Attribute Register 6" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x21C++0x03 line.long 0x00 "PUWA7,User Write Or Access Attribute Register 7" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x220++0x03 line.long 0x00 "PUWA8,User Write Or Access Attribute Register 8" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x224++0x03 line.long 0x00 "PUWA9,User Write Or Access Attribute Register 9" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x228++0x03 line.long 0x00 "PUWA10,User Write Or Access Attribute Register 10" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x22C++0x03 line.long 0x00 "PUWA11,User Write Or Access Attribute Register 11" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x230++0x03 line.long 0x00 "PUWA12,User Write Or Access Attribute Register 12" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x234++0x03 line.long 0x00 "PUWA13,User Write Or Access Attribute Register 13" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x238++0x03 line.long 0x00 "PUWA14,User Write Or Access Attribute Register 14" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x23C++0x03 line.long 0x00 "PUWA15,User Write Or Access Attribute Register 15" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x240++0x03 line.long 0x00 "PUWA16,User Write Or Access Attribute Register 16" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x244++0x03 line.long 0x00 "PUWA17,User Write Or Access Attribute Register 17" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x248++0x03 line.long 0x00 "PUWA18,User Write Or Access Attribute Register 18" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x24C++0x03 line.long 0x00 "PUWA19,User Write Or Access Attribute Register 19" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x250++0x03 line.long 0x00 "PUWA20,User Write Or Access Attribute Register 20" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x254++0x03 line.long 0x00 "PUWA21,User Write Or Access Attribute Register 21" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x258++0x03 line.long 0x00 "PUWA22,User Write Or Access Attribute Register 22" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x25C++0x03 line.long 0x00 "PUWA23,User Write Or Access Attribute Register 23" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x260++0x03 line.long 0x00 "PUWA24,User Write Or Access Attribute Register 24" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x264++0x03 line.long 0x00 "PUWA25,User Write Or Access Attribute Register 25" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x268++0x03 line.long 0x00 "PUWA26,User Write Or Access Attribute Register 26" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x26C++0x03 line.long 0x00 "PUWA27,User Write Or Access Attribute Register 27" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x270++0x03 line.long 0x00 "PUWA28,User Write Or Access Attribute Register 28" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" group.long 0x274++0x03 line.long 0x00 "PUWA29,User Write Or Access Attribute Register 29" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" else rgroup.long 0x0C++0x0F line.long 0x00 "WPQCLR,Privileged Write Attribute Quick Clear Register" line.long 0x04 "WUQCLR,User Write Attribute Quick Clear Register" line.long 0x08 "RPQCLR,Privileged Read Attribute Quick Clear Register" line.long 0x0C "RUQCLR,User Read Attribute Quick Clear Register" rgroup.long 0x80++0x03 line.long 0x00 "PPR0,Privileged Read Attribute Register 0" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x84++0x03 line.long 0x00 "PPR1,Privileged Read Attribute Register 1" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x88++0x03 line.long 0x00 "PPR2,Privileged Read Attribute Register 2" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x8C++0x03 line.long 0x00 "PPR3,Privileged Read Attribute Register 3" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x90++0x03 line.long 0x00 "PPR4,Privileged Read Attribute Register 4" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x94++0x03 line.long 0x00 "PPR5,Privileged Read Attribute Register 5" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x98++0x03 line.long 0x00 "PPR6,Privileged Read Attribute Register 6" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x9C++0x03 line.long 0x00 "PPR7,Privileged Read Attribute Register 7" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xA0++0x03 line.long 0x00 "PPR8,Privileged Read Attribute Register 8" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xA4++0x03 line.long 0x00 "PPR9,Privileged Read Attribute Register 9" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xA8++0x03 line.long 0x00 "PPR10,Privileged Read Attribute Register 10" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xAC++0x03 line.long 0x00 "PPR11,Privileged Read Attribute Register 11" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xB0++0x03 line.long 0x00 "PPR12,Privileged Read Attribute Register 12" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xB4++0x03 line.long 0x00 "PPR13,Privileged Read Attribute Register 13" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xB8++0x03 line.long 0x00 "PPR14,Privileged Read Attribute Register 14" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xBC++0x03 line.long 0x00 "PPR15,Privileged Read Attribute Register 15" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xC0++0x03 line.long 0x00 "PPR16,Privileged Read Attribute Register 16" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xC4++0x03 line.long 0x00 "PPR17,Privileged Read Attribute Register 17" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xC8++0x03 line.long 0x00 "PPR18,Privileged Read Attribute Register 18" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xCC++0x03 line.long 0x00 "PPR19,Privileged Read Attribute Register 19" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xD0++0x03 line.long 0x00 "PPR20,Privileged Read Attribute Register 20" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xD4++0x03 line.long 0x00 "PPR21,Privileged Read Attribute Register 21" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xD8++0x03 line.long 0x00 "PPR22,Privileged Read Attribute Register 22" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xDC++0x03 line.long 0x00 "PPR23,Privileged Read Attribute Register 23" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xE0++0x03 line.long 0x00 "PPR24,Privileged Read Attribute Register 24" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xE4++0x03 line.long 0x00 "PPR25,Privileged Read Attribute Register 25" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xE8++0x03 line.long 0x00 "PPR26,Privileged Read Attribute Register 26" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xEC++0x03 line.long 0x00 "PPR27,Privileged Read Attribute Register 27" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xF0++0x03 line.long 0x00 "PPR28,Privileged Read Attribute Register 28" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0xF4++0x03 line.long 0x00 "PPR29,Privileged Read Attribute Register 29" bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x100++0x03 line.long 0x00 "PUR0,User Read Attribute Register 0" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x104++0x03 line.long 0x00 "PUR1,User Read Attribute Register 1" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x108++0x03 line.long 0x00 "PUR2,User Read Attribute Register 2" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x10C++0x03 line.long 0x00 "PUR3,User Read Attribute Register 3" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x110++0x03 line.long 0x00 "PUR4,User Read Attribute Register 4" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x114++0x03 line.long 0x00 "PUR5,User Read Attribute Register 5" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x118++0x03 line.long 0x00 "PUR6,User Read Attribute Register 6" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x11C++0x03 line.long 0x00 "PUR7,User Read Attribute Register 7" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x120++0x03 line.long 0x00 "PUR8,User Read Attribute Register 8" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x124++0x03 line.long 0x00 "PUR9,User Read Attribute Register 9" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x128++0x03 line.long 0x00 "PUR10,User Read Attribute Register 10" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x12C++0x03 line.long 0x00 "PUR11,User Read Attribute Register 11" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x130++0x03 line.long 0x00 "PUR12,User Read Attribute Register 12" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x134++0x03 line.long 0x00 "PUR13,User Read Attribute Register 13" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x138++0x03 line.long 0x00 "PUR14,User Read Attribute Register 14" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x13C++0x03 line.long 0x00 "PUR15,User Read Attribute Register 15" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x140++0x03 line.long 0x00 "PUR16,User Read Attribute Register 16" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x144++0x03 line.long 0x00 "PUR17,User Read Attribute Register 17" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x148++0x03 line.long 0x00 "PUR18,User Read Attribute Register 18" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x14C++0x03 line.long 0x00 "PUR19,User Read Attribute Register 19" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x150++0x03 line.long 0x00 "PUR20,User Read Attribute Register 20" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x154++0x03 line.long 0x00 "PUR21,User Read Attribute Register 21" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x158++0x03 line.long 0x00 "PUR22,User Read Attribute Register 22" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x15C++0x03 line.long 0x00 "PUR23,User Read Attribute Register 23" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x160++0x03 line.long 0x00 "PUR24,User Read Attribute Register 24" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x164++0x03 line.long 0x00 "PUR25,User Read Attribute Register 25" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x168++0x03 line.long 0x00 "PUR26,User Read Attribute Register 26" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x16C++0x03 line.long 0x00 "PUR27,User Read Attribute Register 27" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x170++0x03 line.long 0x00 "PUR28,User Read Attribute Register 28" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" rgroup.long 0x174++0x03 line.long 0x00 "PUR29,User Read Attribute Register 29" bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled" newline rgroup.long 0x180++0x03 line.long 0x00 "PPWA0,Privileged Write Or Access Attribute Register 0" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x184++0x03 line.long 0x00 "PPWA1,Privileged Write Or Access Attribute Register 1" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x188++0x03 line.long 0x00 "PPWA2,Privileged Write Or Access Attribute Register 2" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x18C++0x03 line.long 0x00 "PPWA3,Privileged Write Or Access Attribute Register 3" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x190++0x03 line.long 0x00 "PPWA4,Privileged Write Or Access Attribute Register 4" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x194++0x03 line.long 0x00 "PPWA5,Privileged Write Or Access Attribute Register 5" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x198++0x03 line.long 0x00 "PPWA6,Privileged Write Or Access Attribute Register 6" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x19C++0x03 line.long 0x00 "PPWA7,Privileged Write Or Access Attribute Register 7" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1A0++0x03 line.long 0x00 "PPWA8,Privileged Write Or Access Attribute Register 8" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1A4++0x03 line.long 0x00 "PPWA9,Privileged Write Or Access Attribute Register 9" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1A8++0x03 line.long 0x00 "PPWA10,Privileged Write Or Access Attribute Register 10" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1AC++0x03 line.long 0x00 "PPWA11,Privileged Write Or Access Attribute Register 11" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1B0++0x03 line.long 0x00 "PPWA12,Privileged Write Or Access Attribute Register 12" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1B4++0x03 line.long 0x00 "PPWA13,Privileged Write Or Access Attribute Register 13" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1B8++0x03 line.long 0x00 "PPWA14,Privileged Write Or Access Attribute Register 14" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1BC++0x03 line.long 0x00 "PPWA15,Privileged Write Or Access Attribute Register 15" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1C0++0x03 line.long 0x00 "PPWA16,Privileged Write Or Access Attribute Register 16" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1C4++0x03 line.long 0x00 "PPWA17,Privileged Write Or Access Attribute Register 17" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1C8++0x03 line.long 0x00 "PPWA18,Privileged Write Or Access Attribute Register 18" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1CC++0x03 line.long 0x00 "PPWA19,Privileged Write Or Access Attribute Register 19" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1D0++0x03 line.long 0x00 "PPWA20,Privileged Write Or Access Attribute Register 20" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1D4++0x03 line.long 0x00 "PPWA21,Privileged Write Or Access Attribute Register 21" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1D8++0x03 line.long 0x00 "PPWA22,Privileged Write Or Access Attribute Register 22" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1DC++0x03 line.long 0x00 "PPWA23,Privileged Write Or Access Attribute Register 23" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1E0++0x03 line.long 0x00 "PPWA24,Privileged Write Or Access Attribute Register 24" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1E4++0x03 line.long 0x00 "PPWA25,Privileged Write Or Access Attribute Register 25" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1E8++0x03 line.long 0x00 "PPWA26,Privileged Write Or Access Attribute Register 26" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1EC++0x03 line.long 0x00 "PPWA27,Privileged Write Or Access Attribute Register 27" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1F0++0x03 line.long 0x00 "PPWA28,Privileged Write Or Access Attribute Register 28" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x1F4++0x03 line.long 0x00 "PPWA29,Privileged Write Or Access Attribute Register 29" bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x200++0x03 line.long 0x00 "PUWA0,User Write Or Access Attribute Register 0" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x204++0x03 line.long 0x00 "PUWA1,User Write Or Access Attribute Register 1" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x208++0x03 line.long 0x00 "PUWA2,User Write Or Access Attribute Register 2" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x20C++0x03 line.long 0x00 "PUWA3,User Write Or Access Attribute Register 3" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x210++0x03 line.long 0x00 "PUWA4,User Write Or Access Attribute Register 4" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x214++0x03 line.long 0x00 "PUWA5,User Write Or Access Attribute Register 5" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x218++0x03 line.long 0x00 "PUWA6,User Write Or Access Attribute Register 6" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x21C++0x03 line.long 0x00 "PUWA7,User Write Or Access Attribute Register 7" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x220++0x03 line.long 0x00 "PUWA8,User Write Or Access Attribute Register 8" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x224++0x03 line.long 0x00 "PUWA9,User Write Or Access Attribute Register 9" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x228++0x03 line.long 0x00 "PUWA10,User Write Or Access Attribute Register 10" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x22C++0x03 line.long 0x00 "PUWA11,User Write Or Access Attribute Register 11" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x230++0x03 line.long 0x00 "PUWA12,User Write Or Access Attribute Register 12" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x234++0x03 line.long 0x00 "PUWA13,User Write Or Access Attribute Register 13" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x238++0x03 line.long 0x00 "PUWA14,User Write Or Access Attribute Register 14" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x23C++0x03 line.long 0x00 "PUWA15,User Write Or Access Attribute Register 15" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x240++0x03 line.long 0x00 "PUWA16,User Write Or Access Attribute Register 16" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x244++0x03 line.long 0x00 "PUWA17,User Write Or Access Attribute Register 17" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x248++0x03 line.long 0x00 "PUWA18,User Write Or Access Attribute Register 18" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x24C++0x03 line.long 0x00 "PUWA19,User Write Or Access Attribute Register 19" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x250++0x03 line.long 0x00 "PUWA20,User Write Or Access Attribute Register 20" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x254++0x03 line.long 0x00 "PUWA21,User Write Or Access Attribute Register 21" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x258++0x03 line.long 0x00 "PUWA22,User Write Or Access Attribute Register 22" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x25C++0x03 line.long 0x00 "PUWA23,User Write Or Access Attribute Register 23" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x260++0x03 line.long 0x00 "PUWA24,User Write Or Access Attribute Register 24" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x264++0x03 line.long 0x00 "PUWA25,User Write Or Access Attribute Register 25" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x268++0x03 line.long 0x00 "PUWA26,User Write Or Access Attribute Register 26" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x26C++0x03 line.long 0x00 "PUWA27,User Write Or Access Attribute Register 27" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x270++0x03 line.long 0x00 "PUWA28,User Write Or Access Attribute Register 28" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" rgroup.long 0x274++0x03 line.long 0x00 "PUWA29,User Write Or Access Attribute Register 29" bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled" endif group.long 0xF8++0x03 line.long 0x00 "LOCK0,Lock Register 0" group.long 0x178++0x03 line.long 0x00 "LOCK1,Lock Register 1" group.long 0x1F8++0x03 line.long 0x00 "LOCK2,Lock Register 2" group.long 0x278++0x03 line.long 0x00 "LOCK3,Lock Register 3" group.long 0x2F8++0x03 line.long 0x00 "LOCK4,Lock Register 4" if ((per.l(ad:0xB4750000+0x04)&0x01)==0x00) group.long 0x280++0x03 line.long 0x00 "PFEN0,Privilege Mode Forced Change Function Enable Register 0" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x284++0x03 line.long 0x00 "PFEN1,Privilege Mode Forced Change Function Enable Register 1" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x288++0x03 line.long 0x00 "PFEN2,Privilege Mode Forced Change Function Enable Register 2" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x28C++0x03 line.long 0x00 "PFEN3,Privilege Mode Forced Change Function Enable Register 3" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x290++0x03 line.long 0x00 "PFEN4,Privilege Mode Forced Change Function Enable Register 4" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x294++0x03 line.long 0x00 "PFEN5,Privilege Mode Forced Change Function Enable Register 5" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x298++0x03 line.long 0x00 "PFEN6,Privilege Mode Forced Change Function Enable Register 6" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x29C++0x03 line.long 0x00 "PFEN7,Privilege Mode Forced Change Function Enable Register 7" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2A0++0x03 line.long 0x00 "PFEN8,Privilege Mode Forced Change Function Enable Register 8" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2A4++0x03 line.long 0x00 "PFEN9,Privilege Mode Forced Change Function Enable Register 9" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2A8++0x03 line.long 0x00 "PFEN10,Privilege Mode Forced Change Function Enable Register 10" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2AC++0x03 line.long 0x00 "PFEN11,Privilege Mode Forced Change Function Enable Register 11" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2B0++0x03 line.long 0x00 "PFEN12,Privilege Mode Forced Change Function Enable Register 12" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2B4++0x03 line.long 0x00 "PFEN13,Privilege Mode Forced Change Function Enable Register 13" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2B8++0x03 line.long 0x00 "PFEN14,Privilege Mode Forced Change Function Enable Register 14" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2BC++0x03 line.long 0x00 "PFEN15,Privilege Mode Forced Change Function Enable Register 15" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2C0++0x03 line.long 0x00 "PFEN16,Privilege Mode Forced Change Function Enable Register 16" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2C4++0x03 line.long 0x00 "PFEN17,Privilege Mode Forced Change Function Enable Register 17" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2C8++0x03 line.long 0x00 "PFEN18,Privilege Mode Forced Change Function Enable Register 18" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2CC++0x03 line.long 0x00 "PFEN19,Privilege Mode Forced Change Function Enable Register 19" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2D0++0x03 line.long 0x00 "PFEN20,Privilege Mode Forced Change Function Enable Register 20" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2D4++0x03 line.long 0x00 "PFEN21,Privilege Mode Forced Change Function Enable Register 21" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2D8++0x03 line.long 0x00 "PFEN22,Privilege Mode Forced Change Function Enable Register 22" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2DC++0x03 line.long 0x00 "PFEN23,Privilege Mode Forced Change Function Enable Register 23" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2E0++0x03 line.long 0x00 "PFEN24,Privilege Mode Forced Change Function Enable Register 24" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2E4++0x03 line.long 0x00 "PFEN25,Privilege Mode Forced Change Function Enable Register 25" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2E8++0x03 line.long 0x00 "PFEN26,Privilege Mode Forced Change Function Enable Register 26" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2EC++0x03 line.long 0x00 "PFEN27,Privilege Mode Forced Change Function Enable Register 27" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2F0++0x03 line.long 0x00 "PFEN28,Privilege Mode Forced Change Function Enable Register 28" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" group.long 0x2F4++0x03 line.long 0x00 "PFEN29,Privilege Mode Forced Change Function Enable Register 29" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" else rgroup.long 0x280++0x03 line.long 0x00 "PFEN0,Privilege Mode Forced Change Function Enable Register 0" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x284++0x03 line.long 0x00 "PFEN1,Privilege Mode Forced Change Function Enable Register 1" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x288++0x03 line.long 0x00 "PFEN2,Privilege Mode Forced Change Function Enable Register 2" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x28C++0x03 line.long 0x00 "PFEN3,Privilege Mode Forced Change Function Enable Register 3" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x290++0x03 line.long 0x00 "PFEN4,Privilege Mode Forced Change Function Enable Register 4" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x294++0x03 line.long 0x00 "PFEN5,Privilege Mode Forced Change Function Enable Register 5" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x298++0x03 line.long 0x00 "PFEN6,Privilege Mode Forced Change Function Enable Register 6" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x29C++0x03 line.long 0x00 "PFEN7,Privilege Mode Forced Change Function Enable Register 7" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2A0++0x03 line.long 0x00 "PFEN8,Privilege Mode Forced Change Function Enable Register 8" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2A4++0x03 line.long 0x00 "PFEN9,Privilege Mode Forced Change Function Enable Register 9" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2A8++0x03 line.long 0x00 "PFEN10,Privilege Mode Forced Change Function Enable Register 10" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2AC++0x03 line.long 0x00 "PFEN11,Privilege Mode Forced Change Function Enable Register 11" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2B0++0x03 line.long 0x00 "PFEN12,Privilege Mode Forced Change Function Enable Register 12" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2B4++0x03 line.long 0x00 "PFEN13,Privilege Mode Forced Change Function Enable Register 13" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2B8++0x03 line.long 0x00 "PFEN14,Privilege Mode Forced Change Function Enable Register 14" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2BC++0x03 line.long 0x00 "PFEN15,Privilege Mode Forced Change Function Enable Register 15" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2C0++0x03 line.long 0x00 "PFEN16,Privilege Mode Forced Change Function Enable Register 16" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2C4++0x03 line.long 0x00 "PFEN17,Privilege Mode Forced Change Function Enable Register 17" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2C8++0x03 line.long 0x00 "PFEN18,Privilege Mode Forced Change Function Enable Register 18" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2CC++0x03 line.long 0x00 "PFEN19,Privilege Mode Forced Change Function Enable Register 19" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2D0++0x03 line.long 0x00 "PFEN20,Privilege Mode Forced Change Function Enable Register 20" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2D4++0x03 line.long 0x00 "PFEN21,Privilege Mode Forced Change Function Enable Register 21" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2D8++0x03 line.long 0x00 "PFEN22,Privilege Mode Forced Change Function Enable Register 22" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2DC++0x03 line.long 0x00 "PFEN23,Privilege Mode Forced Change Function Enable Register 23" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2E0++0x03 line.long 0x00 "PFEN24,Privilege Mode Forced Change Function Enable Register 24" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2E4++0x03 line.long 0x00 "PFEN25,Privilege Mode Forced Change Function Enable Register 25" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2E8++0x03 line.long 0x00 "PFEN26,Privilege Mode Forced Change Function Enable Register 26" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2EC++0x03 line.long 0x00 "PFEN27,Privilege Mode Forced Change Function Enable Register 27" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2F0++0x03 line.long 0x00 "PFEN28,Privilege Mode Forced Change Function Enable Register 28" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" rgroup.long 0x2F4++0x03 line.long 0x00 "PFEN29,Privilege Mode Forced Change Function Enable Register 29" bitfld.long 0x00 31. " PFEN_[31] ,PPU privilege mode forced change function enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,PPU privilege mode forced change function enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,PPU privilege mode forced change function enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,PPU privilege mode forced change function enable bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,PPU privilege mode forced change function enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,PPU privilege mode forced change function enable bit 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,PPU privilege mode forced change function enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,PPU privilege mode forced change function enable bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,PPU privilege mode forced change function enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,PPU privilege mode forced change function enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,PPU privilege mode forced change function enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,PPU privilege mode forced change function enable bit 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,PPU privilege mode forced change function enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,PPU privilege mode forced change function enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,PPU privilege mode forced change function enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,PPU privilege mode forced change function enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,PPU privilege mode forced change function enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,PPU privilege mode forced change function enable bit 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,PPU privilege mode forced change function enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,PPU privilege mode forced change function enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,PPU privilege mode forced change function enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,PPU privilege mode forced change function enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,PPU privilege mode forced change function enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,PPU privilege mode forced change function enable bit 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,PPU privilege mode forced change function enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PPU privilege mode forced change function enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PPU privilege mode forced change function enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PPU privilege mode forced change function enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,PPU privilege mode forced change function enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PPU privilege mode forced change function enable bit 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,PPU privilege mode forced change function enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PPU privilege mode forced change function enable bit 0" "Disabled,Enabled" endif width 0x0B tree.end ; tree "DDRHSSPI (DDR High Speed SPI Controller)" ; base ad:0x00 ; %include s6j34x/ddrhsspi.ph ad:0x00 ; tree.end ; tree "EBI (External Bus Interface)" ; base ad:0x00 ; %include s6j34x/ebi.ph ; tree.end tree "SRAM_IF (System SRAM Module)" base ad:0xB0108000 width 8. if (((per.l(ad:0xB0108000+0x18))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "CFG0,SRAM_IF Configuration Register 0" bitfld.long 0x00 24.--25. " RDWAIT ,Read data wait state value" "0,1,2,3" bitfld.long 0x00 16.--17. " WRWAIT ,Write data wait state value" "0,1,2,3" rbitfld.long 0x00 8. " LOCK_STATUS ,SRAM_IF lock status" "Unlocked,Locked" hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC ERRBIT value" sif cpuis("S6J34*")||cpuis("S6J35*") group.long 0x04++0x03 line.long 0x00 "CFG1,SRAM_IF Configuration Register 1" bitfld.long 0x00 31. " ERRBIT[31] ,Emulated bit-flip 31 value" "Not flipped,Flipped" bitfld.long 0x00 30. " [30] ,Emulated bit-flip 30 value" "Not flipped,Flipped" bitfld.long 0x00 29. " [29] ,Emulated bit-flip 29 value" "Not flipped,Flipped" bitfld.long 0x00 28. " [28] ,Emulated bit-flip 28 value" "Not flipped,Flipped" newline bitfld.long 0x00 27. " [27] ,Emulated bit-flip 27 value" "Not flipped,Flipped" bitfld.long 0x00 26. " [26] ,Emulated bit-flip 26 value" "Not flipped,Flipped" bitfld.long 0x00 25. " [25] ,Emulated bit-flip 25 value" "Not flipped,Flipped" bitfld.long 0x00 24. " [24] ,Emulated bit-flip 24 value" "Not flipped,Flipped" newline bitfld.long 0x00 23. " [23] ,Emulated bit-flip 23 value" "Not flipped,Flipped" bitfld.long 0x00 22. " [22] ,Emulated bit-flip 22 value" "Not flipped,Flipped" bitfld.long 0x00 21. " [21] ,Emulated bit-flip 21 value" "Not flipped,Flipped" bitfld.long 0x00 20. " [20] ,Emulated bit-flip 20 value" "Not flipped,Flipped" newline bitfld.long 0x00 19. " [19] ,Emulated bit-flip 19 value" "Not flipped,Flipped" bitfld.long 0x00 18. " [18] ,Emulated bit-flip 18 value" "Not flipped,Flipped" bitfld.long 0x00 17. " [17] ,Emulated bit-flip 17 value" "Not flipped,Flipped" bitfld.long 0x00 16. " [16] ,Emulated bit-flip 16 value" "Not flipped,Flipped" newline bitfld.long 0x00 15. " [15] ,Emulated bit-flip 15 value" "Not flipped,Flipped" bitfld.long 0x00 14. " [14] ,Emulated bit-flip 14 value" "Not flipped,Flipped" bitfld.long 0x00 13. " [13] ,Emulated bit-flip 13 value" "Not flipped,Flipped" bitfld.long 0x00 12. " [12] ,Emulated bit-flip 12 value" "Not flipped,Flipped" newline bitfld.long 0x00 11. " [11] ,Emulated bit-flip 11 value" "Not flipped,Flipped" bitfld.long 0x00 10. " [10] ,Emulated bit-flip 10 value" "Not flipped,Flipped" bitfld.long 0x00 9. " [9] ,Emulated bit-flip 9 value" "Not flipped,Flipped" bitfld.long 0x00 8. " [8] ,Emulated bit-flip 8 value" "Not flipped,Flipped" newline bitfld.long 0x00 7. " [7] ,Emulated bit-flip 7 value" "Not flipped,Flipped" bitfld.long 0x00 6. " [6] ,Emulated bit-flip 6 value" "Not flipped,Flipped" bitfld.long 0x00 5. " [5] ,Emulated bit-flip 5 value" "Not flipped,Flipped" bitfld.long 0x00 4. " [4] ,Emulated bit-flip 4 value" "Not flipped,Flipped" newline bitfld.long 0x00 3. " [3] ,Emulated bit-flip 3 value" "Not flipped,Flipped" bitfld.long 0x00 2. " [2] ,Emulated bit-flip 2 value" "Not flipped,Flipped" bitfld.long 0x00 1. " [1] ,Emulated bit-flip 1 value" "Not flipped,Flipped" bitfld.long 0x00 0. " [0] ,Emulated bit-flip 0 value" "Not flipped,Flipped" else group.long 0x04++0x03 line.long 0x00 "CFG1,SRAM_IF Configuration Register 1" endif else group.long 0x00++0x03 line.long 0x00 "CFG0,SRAM_IF Configuration Register 0" bitfld.long 0x00 24.--25. " RDWAIT ,Read data wait state value" "0,1,2,3" bitfld.long 0x00 16.--17. " WRWAIT ,Write data wait state value" "0,1,2,3" rbitfld.long 0x00 8. " LOCK_STATUS ,SRAM_IF lock status" "Unlocked,Locked" hgroup.long 0x04++0x03 hide.long 0x00 "CFG1,SRAM_IF Configuration Register 1" endif group.long 0x08++0x13 line.long 0x00 "CFG2,SRAM_IF Configuration Register 2" bitfld.long 0x00 0. " BYPASSEN ,RDB bypass disable or enable" "Disabled,Enabled" line.long 0x04 "KEY,SRAM_IF Unlock/Lock Key Register" line.long 0x08 "ERRFLG,SRAM_IF Error Flag Register" bitfld.long 0x08 8. " SECCLR ,Single-bit error flag clear" "Not effect,Clear" rbitfld.long 0x08 0. " SECFLG ,Single-bit error detection flag" "No error,Error" line.long 0x0C "INTE,SRAM_IF Interrupt Enable Register" bitfld.long 0x0C 0. " SEC_INT_EN ,Single-bit error interrupt enable bit" "No interrupt,Interrupt" line.long 0x10 "ECCE,SRAM_IF ECC Enable Register" bitfld.long 0x10 0. " ECCEN ,ECCEN value" "Disabled,Enabled" rgroup.long 0x20++0x07 line.long 0x00 "ERRADR,SRAM_IF Error Address Register" line.long 0x04 "MID,SRAM_IF Module Identification Register" width 0x0B tree.end tree.open "ADC12B (Analog/Digital Converter)" tree "ADC12B0" base ad:0xB48C0000 sif (cpuis("S6J342?H*")) width 11. tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "CHCTRL0,Channel Control Register 0" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x100++0x01 line.word 0x00 "CHSTAT0,Channel Status Register 0" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x100+0x80)++0x01 hide.word 0x00 "CD0,Conversion Data Register 0" in group.long (0x0+0x100)++0x03 line.long 0x00 "PCCTRL0,Pulse Counter Control Register 0" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 1" group.long 0x4++0x03 line.long 0x00 "CHCTRL1,Channel Control Register 1" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x102++0x01 line.word 0x00 "CHSTAT1,Channel Status Register 1" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x102+0x80)++0x01 hide.word 0x00 "CD1,Conversion Data Register 1" in group.long (0x4+0x100)++0x03 line.long 0x00 "PCCTRL1,Pulse Counter Control Register 1" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 2" group.long 0x8++0x03 line.long 0x00 "CHCTRL2,Channel Control Register 2" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x104++0x01 line.word 0x00 "CHSTAT2,Channel Status Register 2" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x104+0x80)++0x01 hide.word 0x00 "CD2,Conversion Data Register 2" in group.long (0x8+0x100)++0x03 line.long 0x00 "PCCTRL2,Pulse Counter Control Register 2" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 3" group.long 0xC++0x03 line.long 0x00 "CHCTRL3,Channel Control Register 3" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x106++0x01 line.word 0x00 "CHSTAT3,Channel Status Register 3" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x106+0x80)++0x01 hide.word 0x00 "CD3,Conversion Data Register 3" in group.long (0xC+0x100)++0x03 line.long 0x00 "PCCTRL3,Pulse Counter Control Register 3" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 4" group.long 0x10++0x03 line.long 0x00 "CHCTRL4,Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x108++0x01 line.word 0x00 "CHSTAT4,Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x108+0x80)++0x01 hide.word 0x00 "CD4,Conversion Data Register 4" in group.long (0x10+0x100)++0x03 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 5" group.long 0x14++0x03 line.long 0x00 "CHCTRL5,Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10A++0x01 line.word 0x00 "CHSTAT5,Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10A+0x80)++0x01 hide.word 0x00 "CD5,Conversion Data Register 5" in group.long (0x14+0x100)++0x03 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 6" group.long 0x18++0x03 line.long 0x00 "CHCTRL6,Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10C++0x01 line.word 0x00 "CHSTAT6,Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10C+0x80)++0x01 hide.word 0x00 "CD6,Conversion Data Register 6" in group.long (0x18+0x100)++0x03 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 7" group.long 0x1C++0x03 line.long 0x00 "CHCTRL7,Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10E++0x01 line.word 0x00 "CHSTAT7,Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10E+0x80)++0x01 hide.word 0x00 "CD7,Conversion Data Register 7" in group.long (0x1C+0x100)++0x03 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 8" group.long 0x20++0x03 line.long 0x00 "CHCTRL8,Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x110++0x01 line.word 0x00 "CHSTAT8,Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x110+0x80)++0x01 hide.word 0x00 "CD8,Conversion Data Register 8" in group.long (0x20+0x100)++0x03 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 9" group.long 0x24++0x03 line.long 0x00 "CHCTRL9,Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x112++0x01 line.word 0x00 "CHSTAT9,Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x112+0x80)++0x01 hide.word 0x00 "CD9,Conversion Data Register 9" in group.long (0x24+0x100)++0x03 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 10" group.long 0x28++0x03 line.long 0x00 "CHCTRL10,Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x114++0x01 line.word 0x00 "CHSTAT10,Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x114+0x80)++0x01 hide.word 0x00 "CD10,Conversion Data Register 10" in group.long (0x28+0x100)++0x03 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 11" group.long 0x2C++0x03 line.long 0x00 "CHCTRL11,Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x116++0x01 line.word 0x00 "CHSTAT11,Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x116+0x80)++0x01 hide.word 0x00 "CD11,Conversion Data Register 11" in group.long (0x2C+0x100)++0x03 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 12" group.long 0x30++0x03 line.long 0x00 "CHCTRL12,Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x118++0x01 line.word 0x00 "CHSTAT12,Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x118+0x80)++0x01 hide.word 0x00 "CD12,Conversion Data Register 12" in group.long (0x30+0x100)++0x03 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 13" group.long 0x34++0x03 line.long 0x00 "CHCTRL13,Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11A++0x01 line.word 0x00 "CHSTAT13,Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11A+0x80)++0x01 hide.word 0x00 "CD13,Conversion Data Register 13" in group.long (0x34+0x100)++0x03 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 14" group.long 0x38++0x03 line.long 0x00 "CHCTRL14,Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11C++0x01 line.word 0x00 "CHSTAT14,Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11C+0x80)++0x01 hide.word 0x00 "CD14,Conversion Data Register 14" in group.long (0x38+0x100)++0x03 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 15" group.long 0x3C++0x03 line.long 0x00 "CHCTRL15,Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11E++0x01 line.word 0x00 "CHSTAT15,Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11E+0x80)++0x01 hide.word 0x00 "CD15,Conversion Data Register 15" in group.long (0x3C+0x100)++0x03 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 16" group.long 0x40++0x03 line.long 0x00 "CHCTRL16,Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x120++0x01 line.word 0x00 "CHSTAT16,Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x120+0x80)++0x01 hide.word 0x00 "CD16,Conversion Data Register 16" in group.long (0x40+0x100)++0x03 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 17" group.long 0x44++0x03 line.long 0x00 "CHCTRL17,Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x122++0x01 line.word 0x00 "CHSTAT17,Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x122+0x80)++0x01 hide.word 0x00 "CD17,Conversion Data Register 17" in group.long (0x44+0x100)++0x03 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 18" group.long 0x48++0x03 line.long 0x00 "CHCTRL18,Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x124++0x01 line.word 0x00 "CHSTAT18,Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x124+0x80)++0x01 hide.word 0x00 "CD18,Conversion Data Register 18" in group.long (0x48+0x100)++0x03 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 19" group.long 0x4C++0x03 line.long 0x00 "CHCTRL19,Channel Control Register 19" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x126++0x01 line.word 0x00 "CHSTAT19,Channel Status Register 19" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x126+0x80)++0x01 hide.word 0x00 "CD19,Conversion Data Register 19" in group.long (0x4C+0x100)++0x03 line.long 0x00 "PCCTRL19,Pulse Counter Control Register 19" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 20" group.long 0x50++0x03 line.long 0x00 "CHCTRL20,Channel Control Register 20" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x128++0x01 line.word 0x00 "CHSTAT20,Channel Status Register 20" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x128+0x80)++0x01 hide.word 0x00 "CD20,Conversion Data Register 20" in group.long (0x50+0x100)++0x03 line.long 0x00 "PCCTRL20,Pulse Counter Control Register 20" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 21" group.long 0x54++0x03 line.long 0x00 "CHCTRL21,Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12A++0x01 line.word 0x00 "CHSTAT21,Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12A+0x80)++0x01 hide.word 0x00 "CD21,Conversion Data Register 21" in group.long (0x54+0x100)++0x03 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 22" group.long 0x58++0x03 line.long 0x00 "CHCTRL22,Channel Control Register 22" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12C++0x01 line.word 0x00 "CHSTAT22,Channel Status Register 22" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12C+0x80)++0x01 hide.word 0x00 "CD22,Conversion Data Register 22" in group.long (0x58+0x100)++0x03 line.long 0x00 "PCCTRL22,Pulse Counter Control Register 22" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 23" group.long 0x5C++0x03 line.long 0x00 "CHCTRL23,Channel Control Register 23" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12E++0x01 line.word 0x00 "CHSTAT23,Channel Status Register 23" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12E+0x80)++0x01 hide.word 0x00 "CD23,Conversion Data Register 23" in group.long (0x5C+0x100)++0x03 line.long 0x00 "PCCTRL23,Pulse Counter Control Register 23" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 24" group.long 0x60++0x03 line.long 0x00 "CHCTRL24,Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x130++0x01 line.word 0x00 "CHSTAT24,Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x130+0x80)++0x01 hide.word 0x00 "CD24,Conversion Data Register 24" in group.long (0x60+0x100)++0x03 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 25" group.long 0x64++0x03 line.long 0x00 "CHCTRL25,Channel Control Register 25" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x132++0x01 line.word 0x00 "CHSTAT25,Channel Status Register 25" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x132+0x80)++0x01 hide.word 0x00 "CD25,Conversion Data Register 25" in group.long (0x64+0x100)++0x03 line.long 0x00 "PCCTRL25,Pulse Counter Control Register 25" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 26" group.long 0x68++0x03 line.long 0x00 "CHCTRL26,Channel Control Register 26" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x134++0x01 line.word 0x00 "CHSTAT26,Channel Status Register 26" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x134+0x80)++0x01 hide.word 0x00 "CD26,Conversion Data Register 26" in group.long (0x68+0x100)++0x03 line.long 0x00 "PCCTRL26,Pulse Counter Control Register 26" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 27" group.long 0x6C++0x03 line.long 0x00 "CHCTRL27,Channel Control Register 27" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x136++0x01 line.word 0x00 "CHSTAT27,Channel Status Register 27" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x136+0x80)++0x01 hide.word 0x00 "CD27,Conversion Data Register 27" in group.long (0x6C+0x100)++0x03 line.long 0x00 "PCCTRL27,Pulse Counter Control Register 27" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 28" group.long 0x70++0x03 line.long 0x00 "CHCTRL28,Channel Control Register 28" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x138++0x01 line.word 0x00 "CHSTAT28,Channel Status Register 28" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x138+0x80)++0x01 hide.word 0x00 "CD28,Conversion Data Register 28" in group.long (0x70+0x100)++0x03 line.long 0x00 "PCCTRL28,Pulse Counter Control Register 28" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 29" group.long 0x74++0x03 line.long 0x00 "CHCTRL29,Channel Control Register 29" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x13A++0x01 line.word 0x00 "CHSTAT29,Channel Status Register 29" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x13A+0x80)++0x01 hide.word 0x00 "CD29,Conversion Data Register 29" in group.long (0x74+0x100)++0x03 line.long 0x00 "PCCTRL29,Pulse Counter Control Register 29" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 30" group.long 0x78++0x03 line.long 0x00 "CHCTRL30,Channel Control Register 30" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x13C++0x01 line.word 0x00 "CHSTAT30,Channel Status Register 30" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x13C+0x80)++0x01 hide.word 0x00 "CD30,Conversion Data Register 30" in group.long (0x78+0x100)++0x03 line.long 0x00 "PCCTRL30,Pulse Counter Control Register 30" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 31" group.long 0x7C++0x03 line.long 0x00 "CHCTRL31,Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x13E++0x01 line.word 0x00 "CHSTAT31,Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x13E+0x80)++0x01 hide.word 0x00 "CD31,Conversion Data Register 31" in group.long (0x7C+0x100)++0x03 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end newline rgroup.long 0x300++0x03 line.long 0x00 "CDONEIRQ,A/D Conversion Done Interrupt Flag Register" bitfld.long 0x00 31. " CDONEIRQ[31] ,Conversion done interrupt flag 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Conversion done interrupt flag 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Conversion done interrupt flag 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Conversion done interrupt flag 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Conversion done interrupt flag 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Conversion done interrupt flag 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Conversion done interrupt flag 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Conversion done interrupt flag 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Conversion done interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Conversion done interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Conversion done interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Conversion done interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Conversion done interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Conversion done interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Conversion done interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Conversion done interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Conversion done interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Conversion done interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Conversion done interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Conversion done interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Conversion done interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Conversion done interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Conversion done interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Conversion done interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Conversion done interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Conversion done interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Conversion done interrupt flag 0" "No interrupt,Interrupt" group.long 0x308++0x03 line.long 0x00 "CDONEIRQE,A/D Conversion Done Interrupt Enable Register" bitfld.long 0x00 31. " CDONEIRQE[31] ,Conversion done interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Conversion done interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Conversion done interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Conversion done interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Conversion done interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Conversion done interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Conversion done interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Conversion done interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Conversion done interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Conversion done interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Conversion done interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Conversion done interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Conversion done interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Conversion done interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Conversion done interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Conversion done interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Conversion done interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Conversion done interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Conversion done interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Conversion done interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Conversion done interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Conversion done interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Conversion done interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Conversion done interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Conversion done interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Conversion done interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Conversion done interrupt enable 0" "Disabled,Enabled" group.long 0x310++0x03 line.long 0x00 "CDONEIRQC,A/D Conversion Done Interrupt Clear Register" bitfld.long 0x00 31. " CDONEIRQC[31] ,Conversion done interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Conversion done interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Conversion done interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Conversion done interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Conversion done interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Conversion done interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Conversion done interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Conversion done interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Conversion done interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Conversion done interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Conversion done interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Conversion done interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Conversion done interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Conversion done interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Conversion done interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Conversion done interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Conversion done interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Conversion done interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Conversion done interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Conversion done interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Conversion done interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Conversion done interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Conversion done interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Conversion done interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Conversion done interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Conversion done interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Conversion done interrupt clear 0" "No clear,Clear" rgroup.long 0x318++0x03 line.long 0x00 "GRPIRQ,Group Interrupted Interrupt Flag Register" bitfld.long 0x00 31. " GRPIRQ[31] ,Group interrupted interrupt flag 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Group interrupted interrupt flag 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Group interrupted interrupt flag 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Group interrupted interrupt flag 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Group interrupted interrupt flag 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Group interrupted interrupt flag 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Group interrupted interrupt flag 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Group interrupted interrupt flag 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Group interrupted interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt flag 0" "No interrupt,Interrupt" group.long 0x320++0x03 line.long 0x00 "GRPIRQE,Group Interrupted Interrupt Enable Register" bitfld.long 0x00 31. " GRPIRQE[31] ,Group interrupted interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Group interrupted interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Group interrupted interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Group interrupted interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Group interrupted interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Group interrupted interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Group interrupted interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Group interrupted interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Group interrupted interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt enable 0" "Disabled,Enabled" group.long 0x328++0x03 line.long 0x00 "GRPIRQC,Group Interrupted Interrupt Clear Register" bitfld.long 0x00 31. " GRPIRQC[31] ,Group interrupted interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Group interrupted interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Group interrupted interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Group interrupted interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Group interrupted interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Group interrupted interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Group interrupted interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Group interrupted interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Group interrupted interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt clear 0" "No clear,Clear" rgroup.long 0x330++0x03 line.long 0x00 "RCIRQ,Range Comparator Interrupt Flag Register" bitfld.long 0x00 31. " RCIRQ[31] ,Range comparator interrupt flag 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Range comparator interrupt flag 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Range comparator interrupt flag 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Range comparator interrupt flag 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Range comparator interrupt flag 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Range comparator interrupt flag 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Range comparator interrupt flag 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Range comparator interrupt flag 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Range comparator interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Range comparator interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Range comparator interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Range comparator interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Range comparator interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Range comparator interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Range comparator interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Range comparator interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Range comparator interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Range comparator interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Range comparator interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Range comparator interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Range comparator interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Range comparator interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Range comparator interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Range comparator interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Range comparator interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Range comparator interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Range comparator interrupt flag 0" "No interrupt,Interrupt" group.long 0x338++0x03 line.long 0x00 "RCIRQE,Range Comparator Interrupt Enable Register" bitfld.long 0x00 31. " RCIRQE[31] ,Range comparator interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Range comparator interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Range comparator interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Range comparator interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Range comparator interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Range comparator interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Range comparator interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Range comparator interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Range comparator interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Range comparator interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Range comparator interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Range comparator interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Range comparator interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Range comparator interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Range comparator interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Range comparator interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Range comparator interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Range comparator interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Range comparator interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Range comparator interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Range comparator interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Range comparator interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Range comparator interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Range comparator interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Range comparator interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Range comparator interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Range comparator interrupt enable 0" "Disabled,Enabled" group.long 0x340++0x03 line.long 0x00 "RCIRQC,Range Comparator Interrupt Clear Register" bitfld.long 0x00 31. " RCIRQC[31] ,Range comparator interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Range comparator interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Range comparator interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Range comparator interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Range comparator interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Range comparator interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Range comparator interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Range comparator interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Range comparator interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Range comparator interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Range comparator interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Range comparator interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Range comparator interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Range comparator interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Range comparator interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Range comparator interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Range comparator interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Range comparator interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Range comparator interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Range comparator interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Range comparator interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Range comparator interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Range comparator interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Range comparator interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Range comparator interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Range comparator interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Range comparator interrupt clear 0" "No clear,Clear" rgroup.long 0x348++0x03 line.long 0x00 "PCIRQ,Pulse Counter Interrupt Flag Register" bitfld.long 0x00 31. " PCIRQ[31] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" group.long 0x350++0x03 line.long 0x00 "PCIRQE,Pulse Counter Interrupt Enable Register" bitfld.long 0x00 31. " PCIRQE[31] ,Pulse counter interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Pulse counter interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Pulse counter interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Pulse counter interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Pulse counter interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Pulse counter interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Pulse counter interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Pulse counter interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Pulse counter interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt enable 0" "Disabled,Enabled" group.long 0x358++0x03 line.long 0x00 "PCIRQC,Pulse Counter Interrupt Clear Register" bitfld.long 0x00 31. " PCIRQC[31] ,Pulse counter interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Pulse counter interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Pulse counter interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Pulse counter interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Pulse counter interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Pulse counter interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Pulse counter interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Pulse counter interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Pulse counter interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt clear 0" "No clear,Clear" rgroup.long 0x360++0x03 line.long 0x00 "TRGST,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST[31] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 25. " [25] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 1. " [1] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,A/D channel trigger status flag" "Not requested,Requested" group.long 0x368++0x03 line.long 0x00 "TRGCL,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL[31] ,A/D channel trigger status clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,A/D channel trigger status clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,A/D channel trigger status clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,A/D channel trigger status clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger status clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,A/D channel trigger status clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,A/D channel trigger status clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,A/D channel trigger status clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger status clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,A/D channel trigger status clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,A/D channel trigger status clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,A/D channel trigger status clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger status clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,A/D channel trigger status clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,A/D channel trigger status clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,A/D channel trigger status clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger status clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,A/D channel trigger status clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger status clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger status clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger status clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger status clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,A/D channel trigger status clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger status clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,A/D channel trigger status clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger status clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger status clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,A/D channel trigger status clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger status clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger status clear 0" "No clear,Clear" rgroup.long 0x378++0x03 line.long 0x00 "TRGOR,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR[31] ,A/D channel trigger overrun flag 31" "No overrun,Overrun" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun flag 30" "No overrun,Overrun" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun flag 29" "No overrun,Overrun" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun flag 28" "No overrun,Overrun" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger overrun flag 27" "No overrun,Overrun" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun flag 26" "No overrun,Overrun" bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun flag 25" "No overrun,Overrun" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "No overrun,Overrun" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger overrun flag 23" "No overrun,Overrun" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun flag 22" "No overrun,Overrun" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "No overrun,Overrun" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun flag 20" "No overrun,Overrun" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun flag 19" "No overrun,Overrun" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "No overrun,Overrun" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "No overrun,Overrun" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "No overrun,Overrun" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "No overrun,Overrun" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "No overrun,Overrun" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "No overrun,Overrun" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "No overrun,Overrun" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "No overrun,Overrun" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "No overrun,Overrun" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "No overrun,Overrun" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "No overrun,Overrun" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "No overrun,Overrun" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "No overrun,Overrun" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "No overrun,Overrun" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "No overrun,Overrun" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun flag 3" "No overrun,Overrun" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun flag 2" "No overrun,Overrun" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun flag 1" "No overrun,Overrun" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun flag 0" "No overrun,Overrun" group.long 0x380++0x03 line.long 0x00 "TRGORC,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC[31] ,A/D channel trigger overrun clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger overrun clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger overrun clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun clear 0" "No clear,Clear" group.long 0x370++0x03 line.long 0x00 "RCOTF,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF[31] ,Range comparator over threshold flag 31" "Less/equal,More" bitfld.long 0x00 30. " [30] ,Range comparator over threshold flag 30" "Less/equal,More" bitfld.long 0x00 29. " [29] ,Range comparator over threshold flag 29" "Less/equal,More" bitfld.long 0x00 28. " [28] ,Range comparator over threshold flag 28" "Less/equal,More" newline bitfld.long 0x00 27. " [27] ,Range comparator over threshold flag 27" "Less/equal,More" bitfld.long 0x00 26. " [26] ,Range comparator over threshold flag 26" "Less/equal,More" bitfld.long 0x00 25. " [25] ,Range comparator over threshold flag 25" "Less/equal,More" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less/equal,More" newline bitfld.long 0x00 23. " [23] ,Range comparator over threshold flag 23" "Less/equal,More" bitfld.long 0x00 22. " [22] ,Range comparator over threshold flag 22" "Less/equal,More" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less/equal,More" bitfld.long 0x00 20. " [20] ,Range comparator over threshold flag 20" "Less/equal,More" newline bitfld.long 0x00 19. " [19] ,Range comparator over threshold flag 19" "Less/equal,More" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less/equal,More" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less/equal,More" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less/equal,More" newline bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less/equal,More" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less/equal,More" bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less/equal,More" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less/equal,More" newline bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less/equal,More" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less/equal,More" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less/equal,More" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less/equal,More" newline bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less/equal,More" bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less/equal,More" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less/equal,More" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less/equal,More" newline bitfld.long 0x00 3. " [3] ,Range comparator over threshold flag 3" "Less/equal,More" bitfld.long 0x00 2. " [2] ,Range comparator over threshold flag 2" "Less/equal,More" bitfld.long 0x00 1. " [1] ,Range comparator over threshold flag 1" "Less/equal,More" bitfld.long 0x00 0. " [0] ,Range comparator over threshold flag 0" "Less/equal,More" newline group.word 0x388++0x01 line.word 0x00 "CDDS0,Conversion Done DMA Select Register 0" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38A++0x01 line.word 0x00 "CDDS1,Conversion Done DMA Select Register 1" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38C++0x01 line.word 0x00 "CDDS2,Conversion Done DMA Select Register 2" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38E++0x01 line.word 0x00 "CDDS3,Conversion Done DMA Select Register 3" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x390++0x03 line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,Resumption time" group.word 0x394++0x01 line.word 0x00 "ST0,A/D Converter Sampling Time Setting Register 0" group.word 0x396++0x01 line.word 0x00 "ST1,A/D Converter Sampling Time Setting Register 1" group.word 0x398++0x01 line.word 0x00 "ST2,A/D Converter Sampling Time Setting Register 2" group.word 0x39A++0x01 line.word 0x00 "ST3,A/D Converter Sampling Time Setting Register 3" group.word 0x39C++0x03 line.word 0x00 "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x00 0.--7. 1. " OCV ,Offset compensation value" line.word 0x02 "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x02 0.--4. " GCV ,Gain compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0000+0x3A0)&0x10)==0x10) group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" bitfld.word 0x00 6. " FSTP ,Forced stop" "No stop,Stop" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" else group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" textfld " " bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" endif rgroup.word 0x3A2++0x01 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not busy,Busy" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B0+0x01)++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B2+0x01)++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B4+0x01)++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B6+0x01)++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B8+0x01)++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3BA+0x01)++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3BC+0x01)++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3BE+0x01)++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif group.byte 0x3C0++0x00 line.byte 0x00 "MCCTRL0,A/D Multiple Conversion Channel Control Register 0" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E0++0x00 line.byte 0x00 "MCSTAT0,A/D Multiple Conversion Channel Status Register 0" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C1++0x00 line.byte 0x00 "MCCTRL1,A/D Multiple Conversion Channel Control Register 1" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E1++0x00 line.byte 0x00 "MCSTAT1,A/D Multiple Conversion Channel Status Register 1" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C2++0x00 line.byte 0x00 "MCCTRL2,A/D Multiple Conversion Channel Control Register 2" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E2++0x00 line.byte 0x00 "MCSTAT2,A/D Multiple Conversion Channel Status Register 2" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C3++0x00 line.byte 0x00 "MCCTRL3,A/D Multiple Conversion Channel Control Register 3" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E3++0x00 line.byte 0x00 "MCSTAT3,A/D Multiple Conversion Channel Status Register 3" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." width 0x0B elif (cpuis("S6J342?F*")) width 11. tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "CHCTRL0,Channel Control Register 0" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x100++0x01 line.word 0x00 "CHSTAT0,Channel Status Register 0" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x100+0x80)++0x01 hide.word 0x00 "CD0,Conversion Data Register 0" in group.long (0x0+0x100)++0x03 line.long 0x00 "PCCTRL0,Pulse Counter Control Register 0" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 1" group.long 0x4++0x03 line.long 0x00 "CHCTRL1,Channel Control Register 1" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x102++0x01 line.word 0x00 "CHSTAT1,Channel Status Register 1" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x102+0x80)++0x01 hide.word 0x00 "CD1,Conversion Data Register 1" in group.long (0x4+0x100)++0x03 line.long 0x00 "PCCTRL1,Pulse Counter Control Register 1" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 2" group.long 0x8++0x03 line.long 0x00 "CHCTRL2,Channel Control Register 2" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x104++0x01 line.word 0x00 "CHSTAT2,Channel Status Register 2" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x104+0x80)++0x01 hide.word 0x00 "CD2,Conversion Data Register 2" in group.long (0x8+0x100)++0x03 line.long 0x00 "PCCTRL2,Pulse Counter Control Register 2" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 3" group.long 0xC++0x03 line.long 0x00 "CHCTRL3,Channel Control Register 3" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x106++0x01 line.word 0x00 "CHSTAT3,Channel Status Register 3" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x106+0x80)++0x01 hide.word 0x00 "CD3,Conversion Data Register 3" in group.long (0xC+0x100)++0x03 line.long 0x00 "PCCTRL3,Pulse Counter Control Register 3" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 4" group.long 0x10++0x03 line.long 0x00 "CHCTRL4,Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x108++0x01 line.word 0x00 "CHSTAT4,Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x108+0x80)++0x01 hide.word 0x00 "CD4,Conversion Data Register 4" in group.long (0x10+0x100)++0x03 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 5" group.long 0x14++0x03 line.long 0x00 "CHCTRL5,Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10A++0x01 line.word 0x00 "CHSTAT5,Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10A+0x80)++0x01 hide.word 0x00 "CD5,Conversion Data Register 5" in group.long (0x14+0x100)++0x03 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 6" group.long 0x18++0x03 line.long 0x00 "CHCTRL6,Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10C++0x01 line.word 0x00 "CHSTAT6,Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10C+0x80)++0x01 hide.word 0x00 "CD6,Conversion Data Register 6" in group.long (0x18+0x100)++0x03 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 7" group.long 0x1C++0x03 line.long 0x00 "CHCTRL7,Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10E++0x01 line.word 0x00 "CHSTAT7,Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10E+0x80)++0x01 hide.word 0x00 "CD7,Conversion Data Register 7" in group.long (0x1C+0x100)++0x03 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 8" group.long 0x20++0x03 line.long 0x00 "CHCTRL8,Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x110++0x01 line.word 0x00 "CHSTAT8,Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x110+0x80)++0x01 hide.word 0x00 "CD8,Conversion Data Register 8" in group.long (0x20+0x100)++0x03 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 9" group.long 0x24++0x03 line.long 0x00 "CHCTRL9,Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x112++0x01 line.word 0x00 "CHSTAT9,Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x112+0x80)++0x01 hide.word 0x00 "CD9,Conversion Data Register 9" in group.long (0x24+0x100)++0x03 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 10" group.long 0x28++0x03 line.long 0x00 "CHCTRL10,Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x114++0x01 line.word 0x00 "CHSTAT10,Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x114+0x80)++0x01 hide.word 0x00 "CD10,Conversion Data Register 10" in group.long (0x28+0x100)++0x03 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 11" group.long 0x2C++0x03 line.long 0x00 "CHCTRL11,Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x116++0x01 line.word 0x00 "CHSTAT11,Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x116+0x80)++0x01 hide.word 0x00 "CD11,Conversion Data Register 11" in group.long (0x2C+0x100)++0x03 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 12" group.long 0x30++0x03 line.long 0x00 "CHCTRL12,Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x118++0x01 line.word 0x00 "CHSTAT12,Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x118+0x80)++0x01 hide.word 0x00 "CD12,Conversion Data Register 12" in group.long (0x30+0x100)++0x03 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 13" group.long 0x34++0x03 line.long 0x00 "CHCTRL13,Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11A++0x01 line.word 0x00 "CHSTAT13,Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11A+0x80)++0x01 hide.word 0x00 "CD13,Conversion Data Register 13" in group.long (0x34+0x100)++0x03 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 14" group.long 0x38++0x03 line.long 0x00 "CHCTRL14,Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11C++0x01 line.word 0x00 "CHSTAT14,Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11C+0x80)++0x01 hide.word 0x00 "CD14,Conversion Data Register 14" in group.long (0x38+0x100)++0x03 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 15" group.long 0x3C++0x03 line.long 0x00 "CHCTRL15,Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11E++0x01 line.word 0x00 "CHSTAT15,Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11E+0x80)++0x01 hide.word 0x00 "CD15,Conversion Data Register 15" in group.long (0x3C+0x100)++0x03 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 16" group.long 0x40++0x03 line.long 0x00 "CHCTRL16,Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x120++0x01 line.word 0x00 "CHSTAT16,Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x120+0x80)++0x01 hide.word 0x00 "CD16,Conversion Data Register 16" in group.long (0x40+0x100)++0x03 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 17" group.long 0x44++0x03 line.long 0x00 "CHCTRL17,Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x122++0x01 line.word 0x00 "CHSTAT17,Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x122+0x80)++0x01 hide.word 0x00 "CD17,Conversion Data Register 17" in group.long (0x44+0x100)++0x03 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 18" group.long 0x48++0x03 line.long 0x00 "CHCTRL18,Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x124++0x01 line.word 0x00 "CHSTAT18,Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x124+0x80)++0x01 hide.word 0x00 "CD18,Conversion Data Register 18" in group.long (0x48+0x100)++0x03 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 19" group.long 0x4C++0x03 line.long 0x00 "CHCTRL19,Channel Control Register 19" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x126++0x01 line.word 0x00 "CHSTAT19,Channel Status Register 19" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x126+0x80)++0x01 hide.word 0x00 "CD19,Conversion Data Register 19" in group.long (0x4C+0x100)++0x03 line.long 0x00 "PCCTRL19,Pulse Counter Control Register 19" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end newline rgroup.long 0x300++0x03 line.long 0x00 "CDONEIRQ,A/D Conversion Done Interrupt Flag Register" bitfld.long 0x00 19. " CDONEIRQ[19] ,Conversion done interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Conversion done interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Conversion done interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Conversion done interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Conversion done interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Conversion done interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Conversion done interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Conversion done interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Conversion done interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Conversion done interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Conversion done interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Conversion done interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Conversion done interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Conversion done interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Conversion done interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Conversion done interrupt flag 0" "No interrupt,Interrupt" group.long 0x308++0x03 line.long 0x00 "CDONEIRQE,A/D Conversion Done Interrupt Enable Register" bitfld.long 0x00 19. " CDONEIRQE[19] ,Conversion done interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Conversion done interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Conversion done interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Conversion done interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Conversion done interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Conversion done interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Conversion done interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Conversion done interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Conversion done interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Conversion done interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Conversion done interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Conversion done interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Conversion done interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Conversion done interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Conversion done interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Conversion done interrupt enable 0" "Disabled,Enabled" group.long 0x310++0x03 line.long 0x00 "CDONEIRQC,A/D Conversion Done Interrupt Clear Register" bitfld.long 0x00 19. " CDONEIRQC[19] ,Conversion done interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Conversion done interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Conversion done interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Conversion done interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Conversion done interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Conversion done interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Conversion done interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Conversion done interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Conversion done interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Conversion done interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Conversion done interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Conversion done interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Conversion done interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Conversion done interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Conversion done interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Conversion done interrupt clear 0" "No clear,Clear" rgroup.long 0x318++0x03 line.long 0x00 "GRPIRQ,Group Interrupted Interrupt Flag Register" bitfld.long 0x00 19. " GRPIRQ[19] ,Group interrupted interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt flag 0" "No interrupt,Interrupt" group.long 0x320++0x03 line.long 0x00 "GRPIRQE,Group Interrupted Interrupt Enable Register" bitfld.long 0x00 19. " GRPIRQE[19] ,Group interrupted interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt enable 0" "Disabled,Enabled" group.long 0x328++0x03 line.long 0x00 "GRPIRQC,Group Interrupted Interrupt Clear Register" bitfld.long 0x00 19. " GRPIRQC[19] ,Group interrupted interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt clear 0" "No clear,Clear" rgroup.long 0x330++0x03 line.long 0x00 "RCIRQ,Range Comparator Interrupt Flag Register" bitfld.long 0x00 19. " RCIRQ[19] ,Range comparator interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Range comparator interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Range comparator interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Range comparator interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Range comparator interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Range comparator interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Range comparator interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Range comparator interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Range comparator interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Range comparator interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Range comparator interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Range comparator interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Range comparator interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Range comparator interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Range comparator interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Range comparator interrupt flag 0" "No interrupt,Interrupt" group.long 0x338++0x03 line.long 0x00 "RCIRQE,Range Comparator Interrupt Enable Register" bitfld.long 0x00 19. " RCIRQE[19] ,Range comparator interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Range comparator interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Range comparator interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Range comparator interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Range comparator interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Range comparator interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Range comparator interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Range comparator interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Range comparator interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Range comparator interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Range comparator interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Range comparator interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Range comparator interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Range comparator interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Range comparator interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Range comparator interrupt enable 0" "Disabled,Enabled" group.long 0x340++0x03 line.long 0x00 "RCIRQC,Range Comparator Interrupt Clear Register" bitfld.long 0x00 19. " RCIRQC[19] ,Range comparator interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Range comparator interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Range comparator interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Range comparator interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Range comparator interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Range comparator interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Range comparator interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Range comparator interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Range comparator interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Range comparator interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Range comparator interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Range comparator interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Range comparator interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Range comparator interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Range comparator interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Range comparator interrupt clear 0" "No clear,Clear" rgroup.long 0x348++0x03 line.long 0x00 "PCIRQ,Pulse Counter Interrupt Flag Register" bitfld.long 0x00 19. " PCIRQ[19] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" group.long 0x350++0x03 line.long 0x00 "PCIRQE,Pulse Counter Interrupt Enable Register" bitfld.long 0x00 19. " PCIRQE[19] ,Pulse counter interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt enable 0" "Disabled,Enabled" group.long 0x358++0x03 line.long 0x00 "PCIRQC,Pulse Counter Interrupt Clear Register" bitfld.long 0x00 19. " PCIRQC[19] ,Pulse counter interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt clear 0" "No clear,Clear" rgroup.long 0x360++0x03 line.long 0x00 "TRGST,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 19. " TRGST[19] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 1. " [1] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,A/D channel trigger status flag" "Not requested,Requested" group.long 0x368++0x03 line.long 0x00 "TRGCL,A/D Channel Trigger Clear Register" bitfld.long 0x00 19. " TRGCL[19] ,A/D channel trigger status clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,A/D channel trigger status clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,A/D channel trigger status clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,A/D channel trigger status clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger status clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,A/D channel trigger status clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger status clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger status clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger status clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger status clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,A/D channel trigger status clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger status clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,A/D channel trigger status clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger status clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger status clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,A/D channel trigger status clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger status clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger status clear 0" "No clear,Clear" rgroup.long 0x378++0x03 line.long 0x00 "TRGOR,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 19. " TRGOR[19] ,A/D channel trigger overrun flag 19" "No overrun,Overrun" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "No overrun,Overrun" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "No overrun,Overrun" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "No overrun,Overrun" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "No overrun,Overrun" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "No overrun,Overrun" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "No overrun,Overrun" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "No overrun,Overrun" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "No overrun,Overrun" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "No overrun,Overrun" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "No overrun,Overrun" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "No overrun,Overrun" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "No overrun,Overrun" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "No overrun,Overrun" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "No overrun,Overrun" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "No overrun,Overrun" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun flag 3" "No overrun,Overrun" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun flag 2" "No overrun,Overrun" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun flag 1" "No overrun,Overrun" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun flag 0" "No overrun,Overrun" group.long 0x380++0x03 line.long 0x00 "TRGORC,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 19. " TRGORC[19] ,A/D channel trigger overrun clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun clear 0" "No clear,Clear" group.long 0x370++0x03 line.long 0x00 "RCOTF,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 19. " RCOTF[19] ,Range comparator over threshold flag 19" "Less/equal,More" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less/equal,More" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less/equal,More" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less/equal,More" newline bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less/equal,More" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less/equal,More" bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less/equal,More" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less/equal,More" newline bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less/equal,More" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less/equal,More" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less/equal,More" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less/equal,More" newline bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less/equal,More" bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less/equal,More" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less/equal,More" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less/equal,More" newline bitfld.long 0x00 3. " [3] ,Range comparator over threshold flag 3" "Less/equal,More" bitfld.long 0x00 2. " [2] ,Range comparator over threshold flag 2" "Less/equal,More" bitfld.long 0x00 1. " [1] ,Range comparator over threshold flag 1" "Less/equal,More" bitfld.long 0x00 0. " [0] ,Range comparator over threshold flag 0" "Less/equal,More" newline group.word 0x388++0x01 line.word 0x00 "CDDS0,Conversion Done DMA Select Register 0" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38A++0x01 line.word 0x00 "CDDS1,Conversion Done DMA Select Register 1" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38C++0x01 line.word 0x00 "CDDS2,Conversion Done DMA Select Register 2" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38E++0x01 line.word 0x00 "CDDS3,Conversion Done DMA Select Register 3" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x390++0x03 line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,Resumption time" group.word 0x394++0x01 line.word 0x00 "ST0,A/D Converter Sampling Time Setting Register 0" group.word 0x396++0x01 line.word 0x00 "ST1,A/D Converter Sampling Time Setting Register 1" group.word 0x398++0x01 line.word 0x00 "ST2,A/D Converter Sampling Time Setting Register 2" group.word 0x39A++0x01 line.word 0x00 "ST3,A/D Converter Sampling Time Setting Register 3" group.word 0x39C++0x03 line.word 0x00 "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x00 0.--7. 1. " OCV ,Offset compensation value" line.word 0x02 "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x02 0.--4. " GCV ,Gain compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0000+0x3A0)&0x10)==0x10) group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" bitfld.word 0x00 6. " FSTP ,Forced stop" "No stop,Stop" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" else group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" textfld " " bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" endif rgroup.word 0x3A2++0x01 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not busy,Busy" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B0+0x01)++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B2+0x01)++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B4+0x01)++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B6+0x01)++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B8+0x01)++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3BA+0x01)++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3BC+0x01)++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3BE+0x01)++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif group.byte 0x3C0++0x00 line.byte 0x00 "MCCTRL0,A/D Multiple Conversion Channel Control Register 0" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E0++0x00 line.byte 0x00 "MCSTAT0,A/D Multiple Conversion Channel Status Register 0" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C1++0x00 line.byte 0x00 "MCCTRL1,A/D Multiple Conversion Channel Control Register 1" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E1++0x00 line.byte 0x00 "MCSTAT1,A/D Multiple Conversion Channel Status Register 1" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C2++0x00 line.byte 0x00 "MCCTRL2,A/D Multiple Conversion Channel Control Register 2" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E2++0x00 line.byte 0x00 "MCSTAT2,A/D Multiple Conversion Channel Status Register 2" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C3++0x00 line.byte 0x00 "MCCTRL3,A/D Multiple Conversion Channel Control Register 3" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E3++0x00 line.byte 0x00 "MCSTAT3,A/D Multiple Conversion Channel Status Register 3" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." width 0x0B else width 11. tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "CHCTRL0,Channel Control Register 0" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x100++0x01 line.word 0x00 "CHSTAT0,Channel Status Register 0" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x100+0x80)++0x01 hide.word 0x00 "CD0,Conversion Data Register 0" in group.long (0x0+0x100)++0x03 line.long 0x00 "PCCTRL0,Pulse Counter Control Register 0" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 1" group.long 0x4++0x03 line.long 0x00 "CHCTRL1,Channel Control Register 1" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x102++0x01 line.word 0x00 "CHSTAT1,Channel Status Register 1" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x102+0x80)++0x01 hide.word 0x00 "CD1,Conversion Data Register 1" in group.long (0x4+0x100)++0x03 line.long 0x00 "PCCTRL1,Pulse Counter Control Register 1" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 2" group.long 0x8++0x03 line.long 0x00 "CHCTRL2,Channel Control Register 2" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x104++0x01 line.word 0x00 "CHSTAT2,Channel Status Register 2" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x104+0x80)++0x01 hide.word 0x00 "CD2,Conversion Data Register 2" in group.long (0x8+0x100)++0x03 line.long 0x00 "PCCTRL2,Pulse Counter Control Register 2" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 3" group.long 0xC++0x03 line.long 0x00 "CHCTRL3,Channel Control Register 3" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x106++0x01 line.word 0x00 "CHSTAT3,Channel Status Register 3" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x106+0x80)++0x01 hide.word 0x00 "CD3,Conversion Data Register 3" in group.long (0xC+0x100)++0x03 line.long 0x00 "PCCTRL3,Pulse Counter Control Register 3" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 4" group.long 0x10++0x03 line.long 0x00 "CHCTRL4,Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x108++0x01 line.word 0x00 "CHSTAT4,Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x108+0x80)++0x01 hide.word 0x00 "CD4,Conversion Data Register 4" in group.long (0x10+0x100)++0x03 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 5" group.long 0x14++0x03 line.long 0x00 "CHCTRL5,Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10A++0x01 line.word 0x00 "CHSTAT5,Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10A+0x80)++0x01 hide.word 0x00 "CD5,Conversion Data Register 5" in group.long (0x14+0x100)++0x03 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 6" group.long 0x18++0x03 line.long 0x00 "CHCTRL6,Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10C++0x01 line.word 0x00 "CHSTAT6,Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10C+0x80)++0x01 hide.word 0x00 "CD6,Conversion Data Register 6" in group.long (0x18+0x100)++0x03 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 7" group.long 0x1C++0x03 line.long 0x00 "CHCTRL7,Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10E++0x01 line.word 0x00 "CHSTAT7,Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10E+0x80)++0x01 hide.word 0x00 "CD7,Conversion Data Register 7" in group.long (0x1C+0x100)++0x03 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 8" group.long 0x20++0x03 line.long 0x00 "CHCTRL8,Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x110++0x01 line.word 0x00 "CHSTAT8,Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x110+0x80)++0x01 hide.word 0x00 "CD8,Conversion Data Register 8" in group.long (0x20+0x100)++0x03 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 9" group.long 0x24++0x03 line.long 0x00 "CHCTRL9,Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x112++0x01 line.word 0x00 "CHSTAT9,Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x112+0x80)++0x01 hide.word 0x00 "CD9,Conversion Data Register 9" in group.long (0x24+0x100)++0x03 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 10" group.long 0x28++0x03 line.long 0x00 "CHCTRL10,Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x114++0x01 line.word 0x00 "CHSTAT10,Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x114+0x80)++0x01 hide.word 0x00 "CD10,Conversion Data Register 10" in group.long (0x28+0x100)++0x03 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 11" group.long 0x2C++0x03 line.long 0x00 "CHCTRL11,Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x116++0x01 line.word 0x00 "CHSTAT11,Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x116+0x80)++0x01 hide.word 0x00 "CD11,Conversion Data Register 11" in group.long (0x2C+0x100)++0x03 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 12" group.long 0x30++0x03 line.long 0x00 "CHCTRL12,Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x118++0x01 line.word 0x00 "CHSTAT12,Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x118+0x80)++0x01 hide.word 0x00 "CD12,Conversion Data Register 12" in group.long (0x30+0x100)++0x03 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 13" group.long 0x34++0x03 line.long 0x00 "CHCTRL13,Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11A++0x01 line.word 0x00 "CHSTAT13,Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11A+0x80)++0x01 hide.word 0x00 "CD13,Conversion Data Register 13" in group.long (0x34+0x100)++0x03 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 14" group.long 0x38++0x03 line.long 0x00 "CHCTRL14,Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11C++0x01 line.word 0x00 "CHSTAT14,Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11C+0x80)++0x01 hide.word 0x00 "CD14,Conversion Data Register 14" in group.long (0x38+0x100)++0x03 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 15" group.long 0x3C++0x03 line.long 0x00 "CHCTRL15,Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11E++0x01 line.word 0x00 "CHSTAT15,Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11E+0x80)++0x01 hide.word 0x00 "CD15,Conversion Data Register 15" in group.long (0x3C+0x100)++0x03 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 16" group.long 0x40++0x03 line.long 0x00 "CHCTRL16,Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x120++0x01 line.word 0x00 "CHSTAT16,Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x120+0x80)++0x01 hide.word 0x00 "CD16,Conversion Data Register 16" in group.long (0x40+0x100)++0x03 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 17" group.long 0x44++0x03 line.long 0x00 "CHCTRL17,Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x122++0x01 line.word 0x00 "CHSTAT17,Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x122+0x80)++0x01 hide.word 0x00 "CD17,Conversion Data Register 17" in group.long (0x44+0x100)++0x03 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 18" group.long 0x48++0x03 line.long 0x00 "CHCTRL18,Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x124++0x01 line.word 0x00 "CHSTAT18,Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x124+0x80)++0x01 hide.word 0x00 "CD18,Conversion Data Register 18" in group.long (0x48+0x100)++0x03 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 19" group.long 0x4C++0x03 line.long 0x00 "CHCTRL19,Channel Control Register 19" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x126++0x01 line.word 0x00 "CHSTAT19,Channel Status Register 19" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x126+0x80)++0x01 hide.word 0x00 "CD19,Conversion Data Register 19" in group.long (0x4C+0x100)++0x03 line.long 0x00 "PCCTRL19,Pulse Counter Control Register 19" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 20" group.long 0x50++0x03 line.long 0x00 "CHCTRL20,Channel Control Register 20" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x128++0x01 line.word 0x00 "CHSTAT20,Channel Status Register 20" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x128+0x80)++0x01 hide.word 0x00 "CD20,Conversion Data Register 20" in group.long (0x50+0x100)++0x03 line.long 0x00 "PCCTRL20,Pulse Counter Control Register 20" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 21" group.long 0x54++0x03 line.long 0x00 "CHCTRL21,Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12A++0x01 line.word 0x00 "CHSTAT21,Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12A+0x80)++0x01 hide.word 0x00 "CD21,Conversion Data Register 21" in group.long (0x54+0x100)++0x03 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 22" group.long 0x58++0x03 line.long 0x00 "CHCTRL22,Channel Control Register 22" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12C++0x01 line.word 0x00 "CHSTAT22,Channel Status Register 22" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12C+0x80)++0x01 hide.word 0x00 "CD22,Conversion Data Register 22" in group.long (0x58+0x100)++0x03 line.long 0x00 "PCCTRL22,Pulse Counter Control Register 22" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 23" group.long 0x5C++0x03 line.long 0x00 "CHCTRL23,Channel Control Register 23" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12E++0x01 line.word 0x00 "CHSTAT23,Channel Status Register 23" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12E+0x80)++0x01 hide.word 0x00 "CD23,Conversion Data Register 23" in group.long (0x5C+0x100)++0x03 line.long 0x00 "PCCTRL23,Pulse Counter Control Register 23" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 24" group.long 0x60++0x03 line.long 0x00 "CHCTRL24,Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x130++0x01 line.word 0x00 "CHSTAT24,Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x130+0x80)++0x01 hide.word 0x00 "CD24,Conversion Data Register 24" in group.long (0x60+0x100)++0x03 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 25" group.long 0x64++0x03 line.long 0x00 "CHCTRL25,Channel Control Register 25" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x132++0x01 line.word 0x00 "CHSTAT25,Channel Status Register 25" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x132+0x80)++0x01 hide.word 0x00 "CD25,Conversion Data Register 25" in group.long (0x64+0x100)++0x03 line.long 0x00 "PCCTRL25,Pulse Counter Control Register 25" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 26" group.long 0x68++0x03 line.long 0x00 "CHCTRL26,Channel Control Register 26" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x134++0x01 line.word 0x00 "CHSTAT26,Channel Status Register 26" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x134+0x80)++0x01 hide.word 0x00 "CD26,Conversion Data Register 26" in group.long (0x68+0x100)++0x03 line.long 0x00 "PCCTRL26,Pulse Counter Control Register 26" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 27" group.long 0x6C++0x03 line.long 0x00 "CHCTRL27,Channel Control Register 27" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x136++0x01 line.word 0x00 "CHSTAT27,Channel Status Register 27" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x136+0x80)++0x01 hide.word 0x00 "CD27,Conversion Data Register 27" in group.long (0x6C+0x100)++0x03 line.long 0x00 "PCCTRL27,Pulse Counter Control Register 27" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 28" group.long 0x70++0x03 line.long 0x00 "CHCTRL28,Channel Control Register 28" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x138++0x01 line.word 0x00 "CHSTAT28,Channel Status Register 28" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x138+0x80)++0x01 hide.word 0x00 "CD28,Conversion Data Register 28" in group.long (0x70+0x100)++0x03 line.long 0x00 "PCCTRL28,Pulse Counter Control Register 28" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 29" group.long 0x74++0x03 line.long 0x00 "CHCTRL29,Channel Control Register 29" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x13A++0x01 line.word 0x00 "CHSTAT29,Channel Status Register 29" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x13A+0x80)++0x01 hide.word 0x00 "CD29,Conversion Data Register 29" in group.long (0x74+0x100)++0x03 line.long 0x00 "PCCTRL29,Pulse Counter Control Register 29" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 30" group.long 0x78++0x03 line.long 0x00 "CHCTRL30,Channel Control Register 30" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x13C++0x01 line.word 0x00 "CHSTAT30,Channel Status Register 30" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x13C+0x80)++0x01 hide.word 0x00 "CD30,Conversion Data Register 30" in group.long (0x78+0x100)++0x03 line.long 0x00 "PCCTRL30,Pulse Counter Control Register 30" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 31" group.long 0x7C++0x03 line.long 0x00 "CHCTRL31,Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x13E++0x01 line.word 0x00 "CHSTAT31,Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x13E+0x80)++0x01 hide.word 0x00 "CD31,Conversion Data Register 31" in group.long (0x7C+0x100)++0x03 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end newline rgroup.long 0x300++0x03 line.long 0x00 "CDONEIRQ,A/D Conversion Done Interrupt Flag Register" bitfld.long 0x00 31. " CDONEIRQ[31] ,Conversion done interrupt flag 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Conversion done interrupt flag 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Conversion done interrupt flag 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Conversion done interrupt flag 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Conversion done interrupt flag 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Conversion done interrupt flag 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Conversion done interrupt flag 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Conversion done interrupt flag 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Conversion done interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Conversion done interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Conversion done interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Conversion done interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Conversion done interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Conversion done interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Conversion done interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Conversion done interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Conversion done interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Conversion done interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Conversion done interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Conversion done interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Conversion done interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Conversion done interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Conversion done interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Conversion done interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Conversion done interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Conversion done interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Conversion done interrupt flag 0" "No interrupt,Interrupt" group.long 0x308++0x03 line.long 0x00 "CDONEIRQE,A/D Conversion Done Interrupt Enable Register" bitfld.long 0x00 31. " CDONEIRQE[31] ,Conversion done interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Conversion done interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Conversion done interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Conversion done interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Conversion done interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Conversion done interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Conversion done interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Conversion done interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Conversion done interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Conversion done interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Conversion done interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Conversion done interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Conversion done interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Conversion done interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Conversion done interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Conversion done interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Conversion done interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Conversion done interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Conversion done interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Conversion done interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Conversion done interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Conversion done interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Conversion done interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Conversion done interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Conversion done interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Conversion done interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Conversion done interrupt enable 0" "Disabled,Enabled" group.long 0x310++0x03 line.long 0x00 "CDONEIRQC,A/D Conversion Done Interrupt Clear Register" bitfld.long 0x00 31. " CDONEIRQC[31] ,Conversion done interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Conversion done interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Conversion done interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Conversion done interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Conversion done interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Conversion done interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Conversion done interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Conversion done interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Conversion done interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Conversion done interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Conversion done interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Conversion done interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Conversion done interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Conversion done interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Conversion done interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Conversion done interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Conversion done interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Conversion done interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Conversion done interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Conversion done interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Conversion done interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Conversion done interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Conversion done interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Conversion done interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Conversion done interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Conversion done interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Conversion done interrupt clear 0" "No clear,Clear" rgroup.long 0x318++0x03 line.long 0x00 "GRPIRQ,Group Interrupted Interrupt Flag Register" bitfld.long 0x00 31. " GRPIRQ[31] ,Group interrupted interrupt flag 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Group interrupted interrupt flag 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Group interrupted interrupt flag 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Group interrupted interrupt flag 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Group interrupted interrupt flag 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Group interrupted interrupt flag 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Group interrupted interrupt flag 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Group interrupted interrupt flag 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Group interrupted interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt flag 0" "No interrupt,Interrupt" group.long 0x320++0x03 line.long 0x00 "GRPIRQE,Group Interrupted Interrupt Enable Register" bitfld.long 0x00 31. " GRPIRQE[31] ,Group interrupted interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Group interrupted interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Group interrupted interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Group interrupted interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Group interrupted interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Group interrupted interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Group interrupted interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Group interrupted interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Group interrupted interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt enable 0" "Disabled,Enabled" group.long 0x328++0x03 line.long 0x00 "GRPIRQC,Group Interrupted Interrupt Clear Register" bitfld.long 0x00 31. " GRPIRQC[31] ,Group interrupted interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Group interrupted interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Group interrupted interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Group interrupted interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Group interrupted interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Group interrupted interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Group interrupted interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Group interrupted interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Group interrupted interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt clear 0" "No clear,Clear" rgroup.long 0x330++0x03 line.long 0x00 "RCIRQ,Range Comparator Interrupt Flag Register" bitfld.long 0x00 31. " RCIRQ[31] ,Range comparator interrupt flag 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Range comparator interrupt flag 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Range comparator interrupt flag 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Range comparator interrupt flag 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Range comparator interrupt flag 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Range comparator interrupt flag 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Range comparator interrupt flag 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Range comparator interrupt flag 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Range comparator interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Range comparator interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Range comparator interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Range comparator interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Range comparator interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Range comparator interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Range comparator interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Range comparator interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Range comparator interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Range comparator interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Range comparator interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Range comparator interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Range comparator interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Range comparator interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Range comparator interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Range comparator interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Range comparator interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Range comparator interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Range comparator interrupt flag 0" "No interrupt,Interrupt" group.long 0x338++0x03 line.long 0x00 "RCIRQE,Range Comparator Interrupt Enable Register" bitfld.long 0x00 31. " RCIRQE[31] ,Range comparator interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Range comparator interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Range comparator interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Range comparator interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Range comparator interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Range comparator interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Range comparator interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Range comparator interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Range comparator interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Range comparator interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Range comparator interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Range comparator interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Range comparator interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Range comparator interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Range comparator interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Range comparator interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Range comparator interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Range comparator interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Range comparator interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Range comparator interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Range comparator interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Range comparator interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Range comparator interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Range comparator interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Range comparator interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Range comparator interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Range comparator interrupt enable 0" "Disabled,Enabled" group.long 0x340++0x03 line.long 0x00 "RCIRQC,Range Comparator Interrupt Clear Register" bitfld.long 0x00 31. " RCIRQC[31] ,Range comparator interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Range comparator interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Range comparator interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Range comparator interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Range comparator interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Range comparator interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Range comparator interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Range comparator interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Range comparator interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Range comparator interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Range comparator interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Range comparator interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Range comparator interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Range comparator interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Range comparator interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Range comparator interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Range comparator interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Range comparator interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Range comparator interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Range comparator interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Range comparator interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Range comparator interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Range comparator interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Range comparator interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Range comparator interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Range comparator interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Range comparator interrupt clear 0" "No clear,Clear" rgroup.long 0x348++0x03 line.long 0x00 "PCIRQ,Pulse Counter Interrupt Flag Register" bitfld.long 0x00 31. " PCIRQ[31] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" group.long 0x350++0x03 line.long 0x00 "PCIRQE,Pulse Counter Interrupt Enable Register" bitfld.long 0x00 31. " PCIRQE[31] ,Pulse counter interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Pulse counter interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Pulse counter interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Pulse counter interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Pulse counter interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Pulse counter interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Pulse counter interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Pulse counter interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Pulse counter interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt enable 0" "Disabled,Enabled" group.long 0x358++0x03 line.long 0x00 "PCIRQC,Pulse Counter Interrupt Clear Register" bitfld.long 0x00 31. " PCIRQC[31] ,Pulse counter interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Pulse counter interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Pulse counter interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Pulse counter interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Pulse counter interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Pulse counter interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Pulse counter interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Pulse counter interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Pulse counter interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt clear 0" "No clear,Clear" rgroup.long 0x360++0x03 line.long 0x00 "TRGST,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST[31] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 25. " [25] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 1. " [1] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,A/D channel trigger status flag" "Not requested,Requested" group.long 0x368++0x03 line.long 0x00 "TRGCL,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL[31] ,A/D channel trigger status clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,A/D channel trigger status clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,A/D channel trigger status clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,A/D channel trigger status clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger status clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,A/D channel trigger status clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,A/D channel trigger status clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,A/D channel trigger status clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger status clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,A/D channel trigger status clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,A/D channel trigger status clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,A/D channel trigger status clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger status clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,A/D channel trigger status clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,A/D channel trigger status clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,A/D channel trigger status clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger status clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,A/D channel trigger status clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger status clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger status clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger status clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger status clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,A/D channel trigger status clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger status clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,A/D channel trigger status clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger status clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger status clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,A/D channel trigger status clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger status clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger status clear 0" "No clear,Clear" rgroup.long 0x378++0x03 line.long 0x00 "TRGOR,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR[31] ,A/D channel trigger overrun flag 31" "No overrun,Overrun" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun flag 30" "No overrun,Overrun" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun flag 29" "No overrun,Overrun" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun flag 28" "No overrun,Overrun" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger overrun flag 27" "No overrun,Overrun" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun flag 26" "No overrun,Overrun" bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun flag 25" "No overrun,Overrun" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "No overrun,Overrun" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger overrun flag 23" "No overrun,Overrun" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun flag 22" "No overrun,Overrun" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "No overrun,Overrun" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun flag 20" "No overrun,Overrun" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun flag 19" "No overrun,Overrun" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "No overrun,Overrun" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "No overrun,Overrun" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "No overrun,Overrun" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "No overrun,Overrun" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "No overrun,Overrun" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "No overrun,Overrun" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "No overrun,Overrun" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "No overrun,Overrun" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "No overrun,Overrun" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "No overrun,Overrun" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "No overrun,Overrun" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "No overrun,Overrun" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "No overrun,Overrun" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "No overrun,Overrun" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "No overrun,Overrun" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun flag 3" "No overrun,Overrun" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun flag 2" "No overrun,Overrun" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun flag 1" "No overrun,Overrun" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun flag 0" "No overrun,Overrun" group.long 0x380++0x03 line.long 0x00 "TRGORC,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC[31] ,A/D channel trigger overrun clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger overrun clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger overrun clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun clear 0" "No clear,Clear" group.long 0x370++0x03 line.long 0x00 "RCOTF,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF[31] ,Range comparator over threshold flag 31" "Less/equal,More" bitfld.long 0x00 30. " [30] ,Range comparator over threshold flag 30" "Less/equal,More" bitfld.long 0x00 29. " [29] ,Range comparator over threshold flag 29" "Less/equal,More" bitfld.long 0x00 28. " [28] ,Range comparator over threshold flag 28" "Less/equal,More" newline bitfld.long 0x00 27. " [27] ,Range comparator over threshold flag 27" "Less/equal,More" bitfld.long 0x00 26. " [26] ,Range comparator over threshold flag 26" "Less/equal,More" bitfld.long 0x00 25. " [25] ,Range comparator over threshold flag 25" "Less/equal,More" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less/equal,More" newline bitfld.long 0x00 23. " [23] ,Range comparator over threshold flag 23" "Less/equal,More" bitfld.long 0x00 22. " [22] ,Range comparator over threshold flag 22" "Less/equal,More" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less/equal,More" bitfld.long 0x00 20. " [20] ,Range comparator over threshold flag 20" "Less/equal,More" newline bitfld.long 0x00 19. " [19] ,Range comparator over threshold flag 19" "Less/equal,More" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less/equal,More" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less/equal,More" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less/equal,More" newline bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less/equal,More" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less/equal,More" bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less/equal,More" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less/equal,More" newline bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less/equal,More" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less/equal,More" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less/equal,More" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less/equal,More" newline bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less/equal,More" bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less/equal,More" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less/equal,More" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less/equal,More" newline bitfld.long 0x00 3. " [3] ,Range comparator over threshold flag 3" "Less/equal,More" bitfld.long 0x00 2. " [2] ,Range comparator over threshold flag 2" "Less/equal,More" bitfld.long 0x00 1. " [1] ,Range comparator over threshold flag 1" "Less/equal,More" bitfld.long 0x00 0. " [0] ,Range comparator over threshold flag 0" "Less/equal,More" newline group.word 0x388++0x01 line.word 0x00 "CDDS0,Conversion Done DMA Select Register 0" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38A++0x01 line.word 0x00 "CDDS1,Conversion Done DMA Select Register 1" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38C++0x01 line.word 0x00 "CDDS2,Conversion Done DMA Select Register 2" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38E++0x01 line.word 0x00 "CDDS3,Conversion Done DMA Select Register 3" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x390++0x03 line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,Resumption time" group.word 0x394++0x01 line.word 0x00 "ST0,A/D Converter Sampling Time Setting Register 0" group.word 0x396++0x01 line.word 0x00 "ST1,A/D Converter Sampling Time Setting Register 1" group.word 0x398++0x01 line.word 0x00 "ST2,A/D Converter Sampling Time Setting Register 2" group.word 0x39A++0x01 line.word 0x00 "ST3,A/D Converter Sampling Time Setting Register 3" group.word 0x39C++0x03 line.word 0x00 "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x00 0.--7. 1. " OCV ,Offset compensation value" line.word 0x02 "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x02 0.--4. " GCV ,Gain compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0000+0x3A0)&0x10)==0x10) group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" bitfld.word 0x00 6. " FSTP ,Forced stop" "No stop,Stop" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" else group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" textfld " " bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" endif rgroup.word 0x3A2++0x01 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not busy,Busy" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B0+0x01)++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B2+0x01)++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B4+0x01)++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B6+0x01)++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3B8+0x01)++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3BA+0x01)++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3BC+0x01)++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0000+0x3A0)&0x20)==0x20) group.byte (0x3BE+0x01)++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else if ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x03) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0000+0x3A0)&0x03)==0x01) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif group.byte 0x3C0++0x00 line.byte 0x00 "MCCTRL0,A/D Multiple Conversion Channel Control Register 0" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E0++0x00 line.byte 0x00 "MCSTAT0,A/D Multiple Conversion Channel Status Register 0" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C1++0x00 line.byte 0x00 "MCCTRL1,A/D Multiple Conversion Channel Control Register 1" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E1++0x00 line.byte 0x00 "MCSTAT1,A/D Multiple Conversion Channel Status Register 1" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C2++0x00 line.byte 0x00 "MCCTRL2,A/D Multiple Conversion Channel Control Register 2" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E2++0x00 line.byte 0x00 "MCSTAT2,A/D Multiple Conversion Channel Status Register 2" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C3++0x00 line.byte 0x00 "MCCTRL3,A/D Multiple Conversion Channel Control Register 3" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E3++0x00 line.byte 0x00 "MCSTAT3,A/D Multiple Conversion Channel Status Register 3" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." width 0x0B endif tree.end tree "ADC12B1" base ad:0xB48C0400 sif (cpuis("S6J342?H*")) width 11. tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "CHCTRL0,Channel Control Register 0" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x100++0x01 line.word 0x00 "CHSTAT0,Channel Status Register 0" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x100+0x80)++0x01 hide.word 0x00 "CD0,Conversion Data Register 0" in group.long (0x0+0x100)++0x03 line.long 0x00 "PCCTRL0,Pulse Counter Control Register 0" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 1" group.long 0x4++0x03 line.long 0x00 "CHCTRL1,Channel Control Register 1" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x102++0x01 line.word 0x00 "CHSTAT1,Channel Status Register 1" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x102+0x80)++0x01 hide.word 0x00 "CD1,Conversion Data Register 1" in group.long (0x4+0x100)++0x03 line.long 0x00 "PCCTRL1,Pulse Counter Control Register 1" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 2" group.long 0x8++0x03 line.long 0x00 "CHCTRL2,Channel Control Register 2" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x104++0x01 line.word 0x00 "CHSTAT2,Channel Status Register 2" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x104+0x80)++0x01 hide.word 0x00 "CD2,Conversion Data Register 2" in group.long (0x8+0x100)++0x03 line.long 0x00 "PCCTRL2,Pulse Counter Control Register 2" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 3" group.long 0xC++0x03 line.long 0x00 "CHCTRL3,Channel Control Register 3" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x106++0x01 line.word 0x00 "CHSTAT3,Channel Status Register 3" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x106+0x80)++0x01 hide.word 0x00 "CD3,Conversion Data Register 3" in group.long (0xC+0x100)++0x03 line.long 0x00 "PCCTRL3,Pulse Counter Control Register 3" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 4" group.long 0x10++0x03 line.long 0x00 "CHCTRL4,Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x108++0x01 line.word 0x00 "CHSTAT4,Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x108+0x80)++0x01 hide.word 0x00 "CD4,Conversion Data Register 4" in group.long (0x10+0x100)++0x03 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 5" group.long 0x14++0x03 line.long 0x00 "CHCTRL5,Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10A++0x01 line.word 0x00 "CHSTAT5,Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10A+0x80)++0x01 hide.word 0x00 "CD5,Conversion Data Register 5" in group.long (0x14+0x100)++0x03 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 6" group.long 0x18++0x03 line.long 0x00 "CHCTRL6,Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10C++0x01 line.word 0x00 "CHSTAT6,Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10C+0x80)++0x01 hide.word 0x00 "CD6,Conversion Data Register 6" in group.long (0x18+0x100)++0x03 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 7" group.long 0x1C++0x03 line.long 0x00 "CHCTRL7,Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10E++0x01 line.word 0x00 "CHSTAT7,Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10E+0x80)++0x01 hide.word 0x00 "CD7,Conversion Data Register 7" in group.long (0x1C+0x100)++0x03 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 8" group.long 0x20++0x03 line.long 0x00 "CHCTRL8,Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x110++0x01 line.word 0x00 "CHSTAT8,Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x110+0x80)++0x01 hide.word 0x00 "CD8,Conversion Data Register 8" in group.long (0x20+0x100)++0x03 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 9" group.long 0x24++0x03 line.long 0x00 "CHCTRL9,Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x112++0x01 line.word 0x00 "CHSTAT9,Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x112+0x80)++0x01 hide.word 0x00 "CD9,Conversion Data Register 9" in group.long (0x24+0x100)++0x03 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 10" group.long 0x28++0x03 line.long 0x00 "CHCTRL10,Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x114++0x01 line.word 0x00 "CHSTAT10,Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x114+0x80)++0x01 hide.word 0x00 "CD10,Conversion Data Register 10" in group.long (0x28+0x100)++0x03 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 11" group.long 0x2C++0x03 line.long 0x00 "CHCTRL11,Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x116++0x01 line.word 0x00 "CHSTAT11,Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x116+0x80)++0x01 hide.word 0x00 "CD11,Conversion Data Register 11" in group.long (0x2C+0x100)++0x03 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 12" group.long 0x30++0x03 line.long 0x00 "CHCTRL12,Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x118++0x01 line.word 0x00 "CHSTAT12,Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x118+0x80)++0x01 hide.word 0x00 "CD12,Conversion Data Register 12" in group.long (0x30+0x100)++0x03 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 13" group.long 0x34++0x03 line.long 0x00 "CHCTRL13,Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11A++0x01 line.word 0x00 "CHSTAT13,Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11A+0x80)++0x01 hide.word 0x00 "CD13,Conversion Data Register 13" in group.long (0x34+0x100)++0x03 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 14" group.long 0x38++0x03 line.long 0x00 "CHCTRL14,Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11C++0x01 line.word 0x00 "CHSTAT14,Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11C+0x80)++0x01 hide.word 0x00 "CD14,Conversion Data Register 14" in group.long (0x38+0x100)++0x03 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 15" group.long 0x3C++0x03 line.long 0x00 "CHCTRL15,Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11E++0x01 line.word 0x00 "CHSTAT15,Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11E+0x80)++0x01 hide.word 0x00 "CD15,Conversion Data Register 15" in group.long (0x3C+0x100)++0x03 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 16" group.long 0x40++0x03 line.long 0x00 "CHCTRL16,Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x120++0x01 line.word 0x00 "CHSTAT16,Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x120+0x80)++0x01 hide.word 0x00 "CD16,Conversion Data Register 16" in group.long (0x40+0x100)++0x03 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 17" group.long 0x44++0x03 line.long 0x00 "CHCTRL17,Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x122++0x01 line.word 0x00 "CHSTAT17,Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x122+0x80)++0x01 hide.word 0x00 "CD17,Conversion Data Register 17" in group.long (0x44+0x100)++0x03 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 18" group.long 0x48++0x03 line.long 0x00 "CHCTRL18,Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x124++0x01 line.word 0x00 "CHSTAT18,Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x124+0x80)++0x01 hide.word 0x00 "CD18,Conversion Data Register 18" in group.long (0x48+0x100)++0x03 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 19" group.long 0x4C++0x03 line.long 0x00 "CHCTRL19,Channel Control Register 19" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x126++0x01 line.word 0x00 "CHSTAT19,Channel Status Register 19" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x126+0x80)++0x01 hide.word 0x00 "CD19,Conversion Data Register 19" in group.long (0x4C+0x100)++0x03 line.long 0x00 "PCCTRL19,Pulse Counter Control Register 19" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 20" group.long 0x50++0x03 line.long 0x00 "CHCTRL20,Channel Control Register 20" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x128++0x01 line.word 0x00 "CHSTAT20,Channel Status Register 20" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x128+0x80)++0x01 hide.word 0x00 "CD20,Conversion Data Register 20" in group.long (0x50+0x100)++0x03 line.long 0x00 "PCCTRL20,Pulse Counter Control Register 20" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 21" group.long 0x54++0x03 line.long 0x00 "CHCTRL21,Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12A++0x01 line.word 0x00 "CHSTAT21,Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12A+0x80)++0x01 hide.word 0x00 "CD21,Conversion Data Register 21" in group.long (0x54+0x100)++0x03 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 22" group.long 0x58++0x03 line.long 0x00 "CHCTRL22,Channel Control Register 22" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12C++0x01 line.word 0x00 "CHSTAT22,Channel Status Register 22" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12C+0x80)++0x01 hide.word 0x00 "CD22,Conversion Data Register 22" in group.long (0x58+0x100)++0x03 line.long 0x00 "PCCTRL22,Pulse Counter Control Register 22" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 23" group.long 0x5C++0x03 line.long 0x00 "CHCTRL23,Channel Control Register 23" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12E++0x01 line.word 0x00 "CHSTAT23,Channel Status Register 23" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12E+0x80)++0x01 hide.word 0x00 "CD23,Conversion Data Register 23" in group.long (0x5C+0x100)++0x03 line.long 0x00 "PCCTRL23,Pulse Counter Control Register 23" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end newline rgroup.long 0x300++0x03 line.long 0x00 "CDONEIRQ,A/D Conversion Done Interrupt Flag Register" bitfld.long 0x00 23. " CDONEIRQ[23] ,Conversion done interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Conversion done interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Conversion done interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Conversion done interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Conversion done interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Conversion done interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Conversion done interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Conversion done interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Conversion done interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Conversion done interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Conversion done interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Conversion done interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Conversion done interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Conversion done interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Conversion done interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Conversion done interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Conversion done interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Conversion done interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Conversion done interrupt flag 0" "No interrupt,Interrupt" group.long 0x308++0x03 line.long 0x00 "CDONEIRQE,A/D Conversion Done Interrupt Enable Register" bitfld.long 0x00 23. " CDONEIRQE[23] ,Conversion done interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Conversion done interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Conversion done interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Conversion done interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Conversion done interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Conversion done interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Conversion done interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Conversion done interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Conversion done interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Conversion done interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Conversion done interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Conversion done interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Conversion done interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Conversion done interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Conversion done interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Conversion done interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Conversion done interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Conversion done interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Conversion done interrupt enable 0" "Disabled,Enabled" group.long 0x310++0x03 line.long 0x00 "CDONEIRQC,A/D Conversion Done Interrupt Clear Register" bitfld.long 0x00 23. " CDONEIRQC[23] ,Conversion done interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Conversion done interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Conversion done interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Conversion done interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Conversion done interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Conversion done interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Conversion done interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Conversion done interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Conversion done interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Conversion done interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Conversion done interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Conversion done interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Conversion done interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Conversion done interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Conversion done interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Conversion done interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Conversion done interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Conversion done interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Conversion done interrupt clear 0" "No clear,Clear" rgroup.long 0x318++0x03 line.long 0x00 "GRPIRQ,Group Interrupted Interrupt Flag Register" bitfld.long 0x00 23. " GRPIRQ[23] ,Group interrupted interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt flag 0" "No interrupt,Interrupt" group.long 0x320++0x03 line.long 0x00 "GRPIRQE,Group Interrupted Interrupt Enable Register" bitfld.long 0x00 23. " GRPIRQE[23] ,Group interrupted interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt enable 0" "Disabled,Enabled" group.long 0x328++0x03 line.long 0x00 "GRPIRQC,Group Interrupted Interrupt Clear Register" bitfld.long 0x00 23. " GRPIRQC[23] ,Group interrupted interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt clear 0" "No clear,Clear" rgroup.long 0x330++0x03 line.long 0x00 "RCIRQ,Range Comparator Interrupt Flag Register" bitfld.long 0x00 23. " RCIRQ[23] ,Range comparator interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Range comparator interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Range comparator interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Range comparator interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Range comparator interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Range comparator interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Range comparator interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Range comparator interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Range comparator interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Range comparator interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Range comparator interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Range comparator interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Range comparator interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Range comparator interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Range comparator interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Range comparator interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Range comparator interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Range comparator interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Range comparator interrupt flag 0" "No interrupt,Interrupt" group.long 0x338++0x03 line.long 0x00 "RCIRQE,Range Comparator Interrupt Enable Register" bitfld.long 0x00 23. " RCIRQE[23] ,Range comparator interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Range comparator interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Range comparator interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Range comparator interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Range comparator interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Range comparator interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Range comparator interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Range comparator interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Range comparator interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Range comparator interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Range comparator interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Range comparator interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Range comparator interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Range comparator interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Range comparator interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Range comparator interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Range comparator interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Range comparator interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Range comparator interrupt enable 0" "Disabled,Enabled" group.long 0x340++0x03 line.long 0x00 "RCIRQC,Range Comparator Interrupt Clear Register" bitfld.long 0x00 23. " RCIRQC[23] ,Range comparator interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Range comparator interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Range comparator interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Range comparator interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Range comparator interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Range comparator interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Range comparator interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Range comparator interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Range comparator interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Range comparator interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Range comparator interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Range comparator interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Range comparator interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Range comparator interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Range comparator interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Range comparator interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Range comparator interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Range comparator interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Range comparator interrupt clear 0" "No clear,Clear" rgroup.long 0x348++0x03 line.long 0x00 "PCIRQ,Pulse Counter Interrupt Flag Register" bitfld.long 0x00 23. " PCIRQ[23] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" group.long 0x350++0x03 line.long 0x00 "PCIRQE,Pulse Counter Interrupt Enable Register" bitfld.long 0x00 23. " PCIRQE[23] ,Pulse counter interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt enable 0" "Disabled,Enabled" group.long 0x358++0x03 line.long 0x00 "PCIRQC,Pulse Counter Interrupt Clear Register" bitfld.long 0x00 23. " PCIRQC[23] ,Pulse counter interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt clear 0" "No clear,Clear" rgroup.long 0x360++0x03 line.long 0x00 "TRGST,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 23. " TRGST[23] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 1. " [1] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,A/D channel trigger status flag" "Not requested,Requested" group.long 0x368++0x03 line.long 0x00 "TRGCL,A/D Channel Trigger Clear Register" bitfld.long 0x00 23. " TRGCL[23] ,A/D channel trigger status clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,A/D channel trigger status clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,A/D channel trigger status clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,A/D channel trigger status clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger status clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,A/D channel trigger status clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,A/D channel trigger status clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,A/D channel trigger status clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger status clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,A/D channel trigger status clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger status clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger status clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger status clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger status clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,A/D channel trigger status clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger status clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,A/D channel trigger status clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger status clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger status clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,A/D channel trigger status clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger status clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger status clear 0" "No clear,Clear" rgroup.long 0x378++0x03 line.long 0x00 "TRGOR,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 23. " TRGOR[23] ,A/D channel trigger overrun flag 23" "No overrun,Overrun" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun flag 22" "No overrun,Overrun" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "No overrun,Overrun" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun flag 20" "No overrun,Overrun" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun flag 19" "No overrun,Overrun" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "No overrun,Overrun" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "No overrun,Overrun" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "No overrun,Overrun" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "No overrun,Overrun" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "No overrun,Overrun" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "No overrun,Overrun" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "No overrun,Overrun" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "No overrun,Overrun" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "No overrun,Overrun" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "No overrun,Overrun" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "No overrun,Overrun" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "No overrun,Overrun" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "No overrun,Overrun" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "No overrun,Overrun" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "No overrun,Overrun" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun flag 3" "No overrun,Overrun" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun flag 2" "No overrun,Overrun" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun flag 1" "No overrun,Overrun" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun flag 0" "No overrun,Overrun" group.long 0x380++0x03 line.long 0x00 "TRGORC,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 23. " TRGORC[23] ,A/D channel trigger overrun clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun clear 0" "No clear,Clear" group.long 0x370++0x03 line.long 0x00 "RCOTF,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 23. " RCOTF[23] ,Range comparator over threshold flag 23" "Less/equal,More" bitfld.long 0x00 22. " [22] ,Range comparator over threshold flag 22" "Less/equal,More" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less/equal,More" bitfld.long 0x00 20. " [20] ,Range comparator over threshold flag 20" "Less/equal,More" newline bitfld.long 0x00 19. " [19] ,Range comparator over threshold flag 19" "Less/equal,More" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less/equal,More" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less/equal,More" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less/equal,More" newline bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less/equal,More" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less/equal,More" bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less/equal,More" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less/equal,More" newline bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less/equal,More" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less/equal,More" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less/equal,More" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less/equal,More" newline bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less/equal,More" bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less/equal,More" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less/equal,More" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less/equal,More" newline bitfld.long 0x00 3. " [3] ,Range comparator over threshold flag 3" "Less/equal,More" bitfld.long 0x00 2. " [2] ,Range comparator over threshold flag 2" "Less/equal,More" bitfld.long 0x00 1. " [1] ,Range comparator over threshold flag 1" "Less/equal,More" bitfld.long 0x00 0. " [0] ,Range comparator over threshold flag 0" "Less/equal,More" newline group.word 0x388++0x01 line.word 0x00 "CDDS0,Conversion Done DMA Select Register 0" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38A++0x01 line.word 0x00 "CDDS1,Conversion Done DMA Select Register 1" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38C++0x01 line.word 0x00 "CDDS2,Conversion Done DMA Select Register 2" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38E++0x01 line.word 0x00 "CDDS3,Conversion Done DMA Select Register 3" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x390++0x03 line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,Resumption time" group.word 0x394++0x01 line.word 0x00 "ST0,A/D Converter Sampling Time Setting Register 0" group.word 0x396++0x01 line.word 0x00 "ST1,A/D Converter Sampling Time Setting Register 1" group.word 0x398++0x01 line.word 0x00 "ST2,A/D Converter Sampling Time Setting Register 2" group.word 0x39A++0x01 line.word 0x00 "ST3,A/D Converter Sampling Time Setting Register 3" group.word 0x39C++0x03 line.word 0x00 "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x00 0.--7. 1. " OCV ,Offset compensation value" line.word 0x02 "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x02 0.--4. " GCV ,Gain compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0400+0x3A0)&0x10)==0x10) group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" bitfld.word 0x00 6. " FSTP ,Forced stop" "No stop,Stop" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" else group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" textfld " " bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" endif rgroup.word 0x3A2++0x01 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not busy,Busy" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B0+0x01)++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B2+0x01)++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B4+0x01)++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B6+0x01)++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B8+0x01)++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3BA+0x01)++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3BC+0x01)++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3BE+0x01)++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif group.byte 0x3C0++0x00 line.byte 0x00 "MCCTRL0,A/D Multiple Conversion Channel Control Register 0" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E0++0x00 line.byte 0x00 "MCSTAT0,A/D Multiple Conversion Channel Status Register 0" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C1++0x00 line.byte 0x00 "MCCTRL1,A/D Multiple Conversion Channel Control Register 1" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E1++0x00 line.byte 0x00 "MCSTAT1,A/D Multiple Conversion Channel Status Register 1" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C2++0x00 line.byte 0x00 "MCCTRL2,A/D Multiple Conversion Channel Control Register 2" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E2++0x00 line.byte 0x00 "MCSTAT2,A/D Multiple Conversion Channel Status Register 2" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C3++0x00 line.byte 0x00 "MCCTRL3,A/D Multiple Conversion Channel Control Register 3" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E3++0x00 line.byte 0x00 "MCSTAT3,A/D Multiple Conversion Channel Status Register 3" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." width 0x0B elif (cpuis("S6J342?F*")) width 11. tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "CHCTRL0,Channel Control Register 0" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x100++0x01 line.word 0x00 "CHSTAT0,Channel Status Register 0" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x100+0x80)++0x01 hide.word 0x00 "CD0,Conversion Data Register 0" in group.long (0x0+0x100)++0x03 line.long 0x00 "PCCTRL0,Pulse Counter Control Register 0" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 1" group.long 0x4++0x03 line.long 0x00 "CHCTRL1,Channel Control Register 1" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x102++0x01 line.word 0x00 "CHSTAT1,Channel Status Register 1" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x102+0x80)++0x01 hide.word 0x00 "CD1,Conversion Data Register 1" in group.long (0x4+0x100)++0x03 line.long 0x00 "PCCTRL1,Pulse Counter Control Register 1" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 2" group.long 0x8++0x03 line.long 0x00 "CHCTRL2,Channel Control Register 2" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x104++0x01 line.word 0x00 "CHSTAT2,Channel Status Register 2" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x104+0x80)++0x01 hide.word 0x00 "CD2,Conversion Data Register 2" in group.long (0x8+0x100)++0x03 line.long 0x00 "PCCTRL2,Pulse Counter Control Register 2" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 3" group.long 0xC++0x03 line.long 0x00 "CHCTRL3,Channel Control Register 3" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x106++0x01 line.word 0x00 "CHSTAT3,Channel Status Register 3" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x106+0x80)++0x01 hide.word 0x00 "CD3,Conversion Data Register 3" in group.long (0xC+0x100)++0x03 line.long 0x00 "PCCTRL3,Pulse Counter Control Register 3" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 4" group.long 0x10++0x03 line.long 0x00 "CHCTRL4,Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x108++0x01 line.word 0x00 "CHSTAT4,Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x108+0x80)++0x01 hide.word 0x00 "CD4,Conversion Data Register 4" in group.long (0x10+0x100)++0x03 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 5" group.long 0x14++0x03 line.long 0x00 "CHCTRL5,Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10A++0x01 line.word 0x00 "CHSTAT5,Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10A+0x80)++0x01 hide.word 0x00 "CD5,Conversion Data Register 5" in group.long (0x14+0x100)++0x03 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 6" group.long 0x18++0x03 line.long 0x00 "CHCTRL6,Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10C++0x01 line.word 0x00 "CHSTAT6,Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10C+0x80)++0x01 hide.word 0x00 "CD6,Conversion Data Register 6" in group.long (0x18+0x100)++0x03 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 7" group.long 0x1C++0x03 line.long 0x00 "CHCTRL7,Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10E++0x01 line.word 0x00 "CHSTAT7,Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10E+0x80)++0x01 hide.word 0x00 "CD7,Conversion Data Register 7" in group.long (0x1C+0x100)++0x03 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 8" group.long 0x20++0x03 line.long 0x00 "CHCTRL8,Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x110++0x01 line.word 0x00 "CHSTAT8,Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x110+0x80)++0x01 hide.word 0x00 "CD8,Conversion Data Register 8" in group.long (0x20+0x100)++0x03 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 9" group.long 0x24++0x03 line.long 0x00 "CHCTRL9,Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x112++0x01 line.word 0x00 "CHSTAT9,Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x112+0x80)++0x01 hide.word 0x00 "CD9,Conversion Data Register 9" in group.long (0x24+0x100)++0x03 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 10" group.long 0x28++0x03 line.long 0x00 "CHCTRL10,Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x114++0x01 line.word 0x00 "CHSTAT10,Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x114+0x80)++0x01 hide.word 0x00 "CD10,Conversion Data Register 10" in group.long (0x28+0x100)++0x03 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 11" group.long 0x2C++0x03 line.long 0x00 "CHCTRL11,Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x116++0x01 line.word 0x00 "CHSTAT11,Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x116+0x80)++0x01 hide.word 0x00 "CD11,Conversion Data Register 11" in group.long (0x2C+0x100)++0x03 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 12" group.long 0x30++0x03 line.long 0x00 "CHCTRL12,Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x118++0x01 line.word 0x00 "CHSTAT12,Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x118+0x80)++0x01 hide.word 0x00 "CD12,Conversion Data Register 12" in group.long (0x30+0x100)++0x03 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 13" group.long 0x34++0x03 line.long 0x00 "CHCTRL13,Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11A++0x01 line.word 0x00 "CHSTAT13,Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11A+0x80)++0x01 hide.word 0x00 "CD13,Conversion Data Register 13" in group.long (0x34+0x100)++0x03 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 14" group.long 0x38++0x03 line.long 0x00 "CHCTRL14,Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11C++0x01 line.word 0x00 "CHSTAT14,Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11C+0x80)++0x01 hide.word 0x00 "CD14,Conversion Data Register 14" in group.long (0x38+0x100)++0x03 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end newline rgroup.long 0x300++0x03 line.long 0x00 "CDONEIRQ,A/D Conversion Done Interrupt Flag Register" bitfld.long 0x00 14. " CDONEIRQ[14] ,Conversion done interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Conversion done interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Conversion done interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Conversion done interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Conversion done interrupt flag 9" "No interrupt,Interrupt" newline bitfld.long 0x00 8. " [8] ,Conversion done interrupt flag 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " [7] ,Conversion done interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Conversion done interrupt flag 6" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " [5] ,Conversion done interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Conversion done interrupt flag 4" "No interrupt,Interrupt" bitfld.long 0x00 3. " [3] ,Conversion done interrupt flag 3" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " [2] ,Conversion done interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Conversion done interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Conversion done interrupt flag 0" "No interrupt,Interrupt" group.long 0x308++0x03 line.long 0x00 "CDONEIRQE,A/D Conversion Done Interrupt Enable Register" bitfld.long 0x00 14. " CDONEIRQE[14] ,Conversion done interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Conversion done interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Conversion done interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Conversion done interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Conversion done interrupt enable 9" "Disabled,Enabled" newline bitfld.long 0x00 8. " [8] ,Conversion done interrupt enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Conversion done interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Conversion done interrupt enable 6" "Disabled,Enabled" newline bitfld.long 0x00 5. " [5] ,Conversion done interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Conversion done interrupt enable 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Conversion done interrupt enable 3" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Conversion done interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Conversion done interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Conversion done interrupt enable 0" "Disabled,Enabled" group.long 0x310++0x03 line.long 0x00 "CDONEIRQC,A/D Conversion Done Interrupt Clear Register" bitfld.long 0x00 14. " CDONEIRQC[14] ,Conversion done interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Conversion done interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Conversion done interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Conversion done interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Conversion done interrupt clear 9" "No clear,Clear" newline bitfld.long 0x00 8. " [8] ,Conversion done interrupt clear 8" "No clear,Clear" bitfld.long 0x00 7. " [7] ,Conversion done interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Conversion done interrupt clear 6" "No clear,Clear" newline bitfld.long 0x00 5. " [5] ,Conversion done interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Conversion done interrupt clear 4" "No clear,Clear" bitfld.long 0x00 3. " [3] ,Conversion done interrupt clear 3" "No clear,Clear" newline bitfld.long 0x00 2. " [2] ,Conversion done interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Conversion done interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Conversion done interrupt clear 0" "No clear,Clear" rgroup.long 0x318++0x03 line.long 0x00 "GRPIRQ,Group Interrupted Interrupt Flag Register" bitfld.long 0x00 14. " GRPIRQ[14] ,Group interrupted interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt flag 9" "No interrupt,Interrupt" newline bitfld.long 0x00 8. " [8] ,Group interrupted interrupt flag 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " [7] ,Group interrupted interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt flag 6" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " [5] ,Group interrupted interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt flag 4" "No interrupt,Interrupt" bitfld.long 0x00 3. " [3] ,Group interrupted interrupt flag 3" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " [2] ,Group interrupted interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt flag 0" "No interrupt,Interrupt" group.long 0x320++0x03 line.long 0x00 "GRPIRQE,Group Interrupted Interrupt Enable Register" bitfld.long 0x00 14. " GRPIRQE[14] ,Group interrupted interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt enable 9" "Disabled,Enabled" newline bitfld.long 0x00 8. " [8] ,Group interrupted interrupt enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Group interrupted interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt enable 6" "Disabled,Enabled" newline bitfld.long 0x00 5. " [5] ,Group interrupted interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt enable 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Group interrupted interrupt enable 3" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Group interrupted interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt enable 0" "Disabled,Enabled" group.long 0x328++0x03 line.long 0x00 "GRPIRQC,Group Interrupted Interrupt Clear Register" bitfld.long 0x00 14. " GRPIRQC[14] ,Group interrupted interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt clear 9" "No clear,Clear" newline bitfld.long 0x00 8. " [8] ,Group interrupted interrupt clear 8" "No clear,Clear" bitfld.long 0x00 7. " [7] ,Group interrupted interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt clear 6" "No clear,Clear" newline bitfld.long 0x00 5. " [5] ,Group interrupted interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt clear 4" "No clear,Clear" bitfld.long 0x00 3. " [3] ,Group interrupted interrupt clear 3" "No clear,Clear" newline bitfld.long 0x00 2. " [2] ,Group interrupted interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt clear 0" "No clear,Clear" rgroup.long 0x330++0x03 line.long 0x00 "RCIRQ,Range Comparator Interrupt Flag Register" bitfld.long 0x00 14. " RCIRQ[14] ,Range comparator interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Range comparator interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Range comparator interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Range comparator interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Range comparator interrupt flag 9" "No interrupt,Interrupt" newline bitfld.long 0x00 8. " [8] ,Range comparator interrupt flag 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " [7] ,Range comparator interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Range comparator interrupt flag 6" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " [5] ,Range comparator interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Range comparator interrupt flag 4" "No interrupt,Interrupt" bitfld.long 0x00 3. " [3] ,Range comparator interrupt flag 3" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " [2] ,Range comparator interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Range comparator interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Range comparator interrupt flag 0" "No interrupt,Interrupt" group.long 0x338++0x03 line.long 0x00 "RCIRQE,Range Comparator Interrupt Enable Register" bitfld.long 0x00 14. " RCIRQE[14] ,Range comparator interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Range comparator interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Range comparator interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Range comparator interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Range comparator interrupt enable 9" "Disabled,Enabled" newline bitfld.long 0x00 8. " [8] ,Range comparator interrupt enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Range comparator interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Range comparator interrupt enable 6" "Disabled,Enabled" newline bitfld.long 0x00 5. " [5] ,Range comparator interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Range comparator interrupt enable 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Range comparator interrupt enable 3" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Range comparator interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Range comparator interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Range comparator interrupt enable 0" "Disabled,Enabled" group.long 0x340++0x03 line.long 0x00 "RCIRQC,Range Comparator Interrupt Clear Register" bitfld.long 0x00 14. " RCIRQC[14] ,Range comparator interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Range comparator interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Range comparator interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Range comparator interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Range comparator interrupt clear 9" "No clear,Clear" newline bitfld.long 0x00 8. " [8] ,Range comparator interrupt clear 8" "No clear,Clear" bitfld.long 0x00 7. " [7] ,Range comparator interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Range comparator interrupt clear 6" "No clear,Clear" newline bitfld.long 0x00 5. " [5] ,Range comparator interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Range comparator interrupt clear 4" "No clear,Clear" bitfld.long 0x00 3. " [3] ,Range comparator interrupt clear 3" "No clear,Clear" newline bitfld.long 0x00 2. " [2] ,Range comparator interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Range comparator interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Range comparator interrupt clear 0" "No clear,Clear" rgroup.long 0x348++0x03 line.long 0x00 "PCIRQ,Pulse Counter Interrupt Flag Register" bitfld.long 0x00 14. " PCIRQ[14] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 8. " [8] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 7. " [7] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " [5] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 3. " [3] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " [2] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" group.long 0x350++0x03 line.long 0x00 "PCIRQE,Pulse Counter Interrupt Enable Register" bitfld.long 0x00 14. " PCIRQE[14] ,Pulse counter interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt enable 9" "Disabled,Enabled" newline bitfld.long 0x00 8. " [8] ,Pulse counter interrupt enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Pulse counter interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt enable 6" "Disabled,Enabled" newline bitfld.long 0x00 5. " [5] ,Pulse counter interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt enable 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Pulse counter interrupt enable 3" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Pulse counter interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt enable 0" "Disabled,Enabled" group.long 0x358++0x03 line.long 0x00 "PCIRQC,Pulse Counter Interrupt Clear Register" bitfld.long 0x00 14. " PCIRQC[14] ,Pulse counter interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt clear 9" "No clear,Clear" newline bitfld.long 0x00 8. " [8] ,Pulse counter interrupt clear 8" "No clear,Clear" bitfld.long 0x00 7. " [7] ,Pulse counter interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt clear 6" "No clear,Clear" newline bitfld.long 0x00 5. " [5] ,Pulse counter interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt clear 4" "No clear,Clear" bitfld.long 0x00 3. " [3] ,Pulse counter interrupt clear 3" "No clear,Clear" newline bitfld.long 0x00 2. " [2] ,Pulse counter interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt clear 0" "No clear,Clear" rgroup.long 0x360++0x03 line.long 0x00 "TRGST,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 14. " TRGST[14] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 3. " [3] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 2. " [2] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 1. " [1] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,A/D channel trigger status flag" "Not requested,Requested" group.long 0x368++0x03 line.long 0x00 "TRGCL,A/D Channel Trigger Clear Register" bitfld.long 0x00 14. " TRGCL[14] ,A/D channel trigger status clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger status clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger status clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger status clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger status clear 9" "No clear,Clear" newline bitfld.long 0x00 8. " [8] ,A/D channel trigger status clear 8" "No clear,Clear" bitfld.long 0x00 7. " [7] ,A/D channel trigger status clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger status clear 6" "No clear,Clear" newline bitfld.long 0x00 5. " [5] ,A/D channel trigger status clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger status clear 4" "No clear,Clear" bitfld.long 0x00 3. " [3] ,A/D channel trigger status clear 3" "No clear,Clear" newline bitfld.long 0x00 2. " [2] ,A/D channel trigger status clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger status clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger status clear 0" "No clear,Clear" rgroup.long 0x378++0x03 line.long 0x00 "TRGOR,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 14. " TRGOR[14] ,A/D channel trigger overrun flag 14" "No overrun,Overrun" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "No overrun,Overrun" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "No overrun,Overrun" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "No overrun,Overrun" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "No overrun,Overrun" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "No overrun,Overrun" newline bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "No overrun,Overrun" bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "No overrun,Overrun" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "No overrun,Overrun" newline bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "No overrun,Overrun" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "No overrun,Overrun" bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun flag 3" "No overrun,Overrun" newline bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun flag 2" "No overrun,Overrun" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun flag 1" "No overrun,Overrun" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun flag 0" "No overrun,Overrun" group.long 0x380++0x03 line.long 0x00 "TRGORC,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 14. " TRGORC[14] ,A/D channel trigger overrun clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun clear 9" "No clear,Clear" newline bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun clear 8" "No clear,Clear" bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun clear 6" "No clear,Clear" newline bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun clear 4" "No clear,Clear" bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun clear 3" "No clear,Clear" newline bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun clear 0" "No clear,Clear" group.long 0x370++0x03 line.long 0x00 "RCOTF,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 14. " RCOTF[14] ,Range comparator over threshold flag 14" "Less/equal,More" bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less/equal,More" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less/equal,More" newline bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less/equal,More" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less/equal,More" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less/equal,More" newline bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less/equal,More" bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less/equal,More" bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less/equal,More" newline bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less/equal,More" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less/equal,More" bitfld.long 0x00 3. " [3] ,Range comparator over threshold flag 3" "Less/equal,More" newline bitfld.long 0x00 2. " [2] ,Range comparator over threshold flag 2" "Less/equal,More" bitfld.long 0x00 1. " [1] ,Range comparator over threshold flag 1" "Less/equal,More" bitfld.long 0x00 0. " [0] ,Range comparator over threshold flag 0" "Less/equal,More" newline group.word 0x388++0x01 line.word 0x00 "CDDS0,Conversion Done DMA Select Register 0" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38A++0x01 line.word 0x00 "CDDS1,Conversion Done DMA Select Register 1" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38C++0x01 line.word 0x00 "CDDS2,Conversion Done DMA Select Register 2" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38E++0x01 line.word 0x00 "CDDS3,Conversion Done DMA Select Register 3" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x390++0x03 line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,Resumption time" group.word 0x394++0x01 line.word 0x00 "ST0,A/D Converter Sampling Time Setting Register 0" group.word 0x396++0x01 line.word 0x00 "ST1,A/D Converter Sampling Time Setting Register 1" group.word 0x398++0x01 line.word 0x00 "ST2,A/D Converter Sampling Time Setting Register 2" group.word 0x39A++0x01 line.word 0x00 "ST3,A/D Converter Sampling Time Setting Register 3" group.word 0x39C++0x03 line.word 0x00 "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x00 0.--7. 1. " OCV ,Offset compensation value" line.word 0x02 "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x02 0.--4. " GCV ,Gain compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0400+0x3A0)&0x10)==0x10) group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" bitfld.word 0x00 6. " FSTP ,Forced stop" "No stop,Stop" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" else group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" textfld " " bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" endif rgroup.word 0x3A2++0x01 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not busy,Busy" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B0+0x01)++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B2+0x01)++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B4+0x01)++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B6+0x01)++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B8+0x01)++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3BA+0x01)++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3BC+0x01)++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3BE+0x01)++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif group.byte 0x3C0++0x00 line.byte 0x00 "MCCTRL0,A/D Multiple Conversion Channel Control Register 0" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E0++0x00 line.byte 0x00 "MCSTAT0,A/D Multiple Conversion Channel Status Register 0" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C1++0x00 line.byte 0x00 "MCCTRL1,A/D Multiple Conversion Channel Control Register 1" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E1++0x00 line.byte 0x00 "MCSTAT1,A/D Multiple Conversion Channel Status Register 1" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C2++0x00 line.byte 0x00 "MCCTRL2,A/D Multiple Conversion Channel Control Register 2" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E2++0x00 line.byte 0x00 "MCSTAT2,A/D Multiple Conversion Channel Status Register 2" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C3++0x00 line.byte 0x00 "MCCTRL3,A/D Multiple Conversion Channel Control Register 3" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E3++0x00 line.byte 0x00 "MCSTAT3,A/D Multiple Conversion Channel Status Register 3" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." width 0x0B else width 11. tree "Channel 0" group.long 0x0++0x03 line.long 0x00 "CHCTRL0,Channel Control Register 0" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x100++0x01 line.word 0x00 "CHSTAT0,Channel Status Register 0" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x100+0x80)++0x01 hide.word 0x00 "CD0,Conversion Data Register 0" in group.long (0x0+0x100)++0x03 line.long 0x00 "PCCTRL0,Pulse Counter Control Register 0" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 1" group.long 0x4++0x03 line.long 0x00 "CHCTRL1,Channel Control Register 1" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x102++0x01 line.word 0x00 "CHSTAT1,Channel Status Register 1" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x102+0x80)++0x01 hide.word 0x00 "CD1,Conversion Data Register 1" in group.long (0x4+0x100)++0x03 line.long 0x00 "PCCTRL1,Pulse Counter Control Register 1" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 2" group.long 0x8++0x03 line.long 0x00 "CHCTRL2,Channel Control Register 2" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x104++0x01 line.word 0x00 "CHSTAT2,Channel Status Register 2" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x104+0x80)++0x01 hide.word 0x00 "CD2,Conversion Data Register 2" in group.long (0x8+0x100)++0x03 line.long 0x00 "PCCTRL2,Pulse Counter Control Register 2" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 3" group.long 0xC++0x03 line.long 0x00 "CHCTRL3,Channel Control Register 3" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x106++0x01 line.word 0x00 "CHSTAT3,Channel Status Register 3" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x106+0x80)++0x01 hide.word 0x00 "CD3,Conversion Data Register 3" in group.long (0xC+0x100)++0x03 line.long 0x00 "PCCTRL3,Pulse Counter Control Register 3" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 4" group.long 0x10++0x03 line.long 0x00 "CHCTRL4,Channel Control Register 4" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x108++0x01 line.word 0x00 "CHSTAT4,Channel Status Register 4" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x108+0x80)++0x01 hide.word 0x00 "CD4,Conversion Data Register 4" in group.long (0x10+0x100)++0x03 line.long 0x00 "PCCTRL4,Pulse Counter Control Register 4" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 5" group.long 0x14++0x03 line.long 0x00 "CHCTRL5,Channel Control Register 5" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10A++0x01 line.word 0x00 "CHSTAT5,Channel Status Register 5" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10A+0x80)++0x01 hide.word 0x00 "CD5,Conversion Data Register 5" in group.long (0x14+0x100)++0x03 line.long 0x00 "PCCTRL5,Pulse Counter Control Register 5" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 6" group.long 0x18++0x03 line.long 0x00 "CHCTRL6,Channel Control Register 6" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10C++0x01 line.word 0x00 "CHSTAT6,Channel Status Register 6" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10C+0x80)++0x01 hide.word 0x00 "CD6,Conversion Data Register 6" in group.long (0x18+0x100)++0x03 line.long 0x00 "PCCTRL6,Pulse Counter Control Register 6" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 7" group.long 0x1C++0x03 line.long 0x00 "CHCTRL7,Channel Control Register 7" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x10E++0x01 line.word 0x00 "CHSTAT7,Channel Status Register 7" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x10E+0x80)++0x01 hide.word 0x00 "CD7,Conversion Data Register 7" in group.long (0x1C+0x100)++0x03 line.long 0x00 "PCCTRL7,Pulse Counter Control Register 7" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 8" group.long 0x20++0x03 line.long 0x00 "CHCTRL8,Channel Control Register 8" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x110++0x01 line.word 0x00 "CHSTAT8,Channel Status Register 8" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x110+0x80)++0x01 hide.word 0x00 "CD8,Conversion Data Register 8" in group.long (0x20+0x100)++0x03 line.long 0x00 "PCCTRL8,Pulse Counter Control Register 8" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 9" group.long 0x24++0x03 line.long 0x00 "CHCTRL9,Channel Control Register 9" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x112++0x01 line.word 0x00 "CHSTAT9,Channel Status Register 9" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x112+0x80)++0x01 hide.word 0x00 "CD9,Conversion Data Register 9" in group.long (0x24+0x100)++0x03 line.long 0x00 "PCCTRL9,Pulse Counter Control Register 9" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 10" group.long 0x28++0x03 line.long 0x00 "CHCTRL10,Channel Control Register 10" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x114++0x01 line.word 0x00 "CHSTAT10,Channel Status Register 10" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x114+0x80)++0x01 hide.word 0x00 "CD10,Conversion Data Register 10" in group.long (0x28+0x100)++0x03 line.long 0x00 "PCCTRL10,Pulse Counter Control Register 10" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 11" group.long 0x2C++0x03 line.long 0x00 "CHCTRL11,Channel Control Register 11" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x116++0x01 line.word 0x00 "CHSTAT11,Channel Status Register 11" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x116+0x80)++0x01 hide.word 0x00 "CD11,Conversion Data Register 11" in group.long (0x2C+0x100)++0x03 line.long 0x00 "PCCTRL11,Pulse Counter Control Register 11" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 12" group.long 0x30++0x03 line.long 0x00 "CHCTRL12,Channel Control Register 12" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x118++0x01 line.word 0x00 "CHSTAT12,Channel Status Register 12" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x118+0x80)++0x01 hide.word 0x00 "CD12,Conversion Data Register 12" in group.long (0x30+0x100)++0x03 line.long 0x00 "PCCTRL12,Pulse Counter Control Register 12" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 13" group.long 0x34++0x03 line.long 0x00 "CHCTRL13,Channel Control Register 13" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11A++0x01 line.word 0x00 "CHSTAT13,Channel Status Register 13" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11A+0x80)++0x01 hide.word 0x00 "CD13,Conversion Data Register 13" in group.long (0x34+0x100)++0x03 line.long 0x00 "PCCTRL13,Pulse Counter Control Register 13" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 14" group.long 0x38++0x03 line.long 0x00 "CHCTRL14,Channel Control Register 14" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11C++0x01 line.word 0x00 "CHSTAT14,Channel Status Register 14" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11C+0x80)++0x01 hide.word 0x00 "CD14,Conversion Data Register 14" in group.long (0x38+0x100)++0x03 line.long 0x00 "PCCTRL14,Pulse Counter Control Register 14" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 15" group.long 0x3C++0x03 line.long 0x00 "CHCTRL15,Channel Control Register 15" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x11E++0x01 line.word 0x00 "CHSTAT15,Channel Status Register 15" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x11E+0x80)++0x01 hide.word 0x00 "CD15,Conversion Data Register 15" in group.long (0x3C+0x100)++0x03 line.long 0x00 "PCCTRL15,Pulse Counter Control Register 15" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 16" group.long 0x40++0x03 line.long 0x00 "CHCTRL16,Channel Control Register 16" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x120++0x01 line.word 0x00 "CHSTAT16,Channel Status Register 16" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x120+0x80)++0x01 hide.word 0x00 "CD16,Conversion Data Register 16" in group.long (0x40+0x100)++0x03 line.long 0x00 "PCCTRL16,Pulse Counter Control Register 16" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 17" group.long 0x44++0x03 line.long 0x00 "CHCTRL17,Channel Control Register 17" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x122++0x01 line.word 0x00 "CHSTAT17,Channel Status Register 17" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x122+0x80)++0x01 hide.word 0x00 "CD17,Conversion Data Register 17" in group.long (0x44+0x100)++0x03 line.long 0x00 "PCCTRL17,Pulse Counter Control Register 17" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 18" group.long 0x48++0x03 line.long 0x00 "CHCTRL18,Channel Control Register 18" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x124++0x01 line.word 0x00 "CHSTAT18,Channel Status Register 18" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x124+0x80)++0x01 hide.word 0x00 "CD18,Conversion Data Register 18" in group.long (0x48+0x100)++0x03 line.long 0x00 "PCCTRL18,Pulse Counter Control Register 18" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 19" group.long 0x4C++0x03 line.long 0x00 "CHCTRL19,Channel Control Register 19" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x126++0x01 line.word 0x00 "CHSTAT19,Channel Status Register 19" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x126+0x80)++0x01 hide.word 0x00 "CD19,Conversion Data Register 19" in group.long (0x4C+0x100)++0x03 line.long 0x00 "PCCTRL19,Pulse Counter Control Register 19" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 20" group.long 0x50++0x03 line.long 0x00 "CHCTRL20,Channel Control Register 20" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x128++0x01 line.word 0x00 "CHSTAT20,Channel Status Register 20" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x128+0x80)++0x01 hide.word 0x00 "CD20,Conversion Data Register 20" in group.long (0x50+0x100)++0x03 line.long 0x00 "PCCTRL20,Pulse Counter Control Register 20" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 21" group.long 0x54++0x03 line.long 0x00 "CHCTRL21,Channel Control Register 21" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12A++0x01 line.word 0x00 "CHSTAT21,Channel Status Register 21" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12A+0x80)++0x01 hide.word 0x00 "CD21,Conversion Data Register 21" in group.long (0x54+0x100)++0x03 line.long 0x00 "PCCTRL21,Pulse Counter Control Register 21" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 22" group.long 0x58++0x03 line.long 0x00 "CHCTRL22,Channel Control Register 22" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12C++0x01 line.word 0x00 "CHSTAT22,Channel Status Register 22" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12C+0x80)++0x01 hide.word 0x00 "CD22,Conversion Data Register 22" in group.long (0x58+0x100)++0x03 line.long 0x00 "PCCTRL22,Pulse Counter Control Register 22" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 23" group.long 0x5C++0x03 line.long 0x00 "CHCTRL23,Channel Control Register 23" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x12E++0x01 line.word 0x00 "CHSTAT23,Channel Status Register 23" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x12E+0x80)++0x01 hide.word 0x00 "CD23,Conversion Data Register 23" in group.long (0x5C+0x100)++0x03 line.long 0x00 "PCCTRL23,Pulse Counter Control Register 23" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 24" group.long 0x60++0x03 line.long 0x00 "CHCTRL24,Channel Control Register 24" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x130++0x01 line.word 0x00 "CHSTAT24,Channel Status Register 24" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x130+0x80)++0x01 hide.word 0x00 "CD24,Conversion Data Register 24" in group.long (0x60+0x100)++0x03 line.long 0x00 "PCCTRL24,Pulse Counter Control Register 24" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 25" group.long 0x64++0x03 line.long 0x00 "CHCTRL25,Channel Control Register 25" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x132++0x01 line.word 0x00 "CHSTAT25,Channel Status Register 25" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x132+0x80)++0x01 hide.word 0x00 "CD25,Conversion Data Register 25" in group.long (0x64+0x100)++0x03 line.long 0x00 "PCCTRL25,Pulse Counter Control Register 25" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 26" group.long 0x68++0x03 line.long 0x00 "CHCTRL26,Channel Control Register 26" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x134++0x01 line.word 0x00 "CHSTAT26,Channel Status Register 26" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x134+0x80)++0x01 hide.word 0x00 "CD26,Conversion Data Register 26" in group.long (0x68+0x100)++0x03 line.long 0x00 "PCCTRL26,Pulse Counter Control Register 26" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 27" group.long 0x6C++0x03 line.long 0x00 "CHCTRL27,Channel Control Register 27" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x136++0x01 line.word 0x00 "CHSTAT27,Channel Status Register 27" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x136+0x80)++0x01 hide.word 0x00 "CD27,Conversion Data Register 27" in group.long (0x6C+0x100)++0x03 line.long 0x00 "PCCTRL27,Pulse Counter Control Register 27" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 28" group.long 0x70++0x03 line.long 0x00 "CHCTRL28,Channel Control Register 28" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x138++0x01 line.word 0x00 "CHSTAT28,Channel Status Register 28" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x138+0x80)++0x01 hide.word 0x00 "CD28,Conversion Data Register 28" in group.long (0x70+0x100)++0x03 line.long 0x00 "PCCTRL28,Pulse Counter Control Register 28" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 29" group.long 0x74++0x03 line.long 0x00 "CHCTRL29,Channel Control Register 29" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x13A++0x01 line.word 0x00 "CHSTAT29,Channel Status Register 29" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x13A+0x80)++0x01 hide.word 0x00 "CD29,Conversion Data Register 29" in group.long (0x74+0x100)++0x03 line.long 0x00 "PCCTRL29,Pulse Counter Control Register 29" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 30" group.long 0x78++0x03 line.long 0x00 "CHCTRL30,Channel Control Register 30" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x13C++0x01 line.word 0x00 "CHSTAT30,Channel Status Register 30" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x13C+0x80)++0x01 hide.word 0x00 "CD30,Conversion Data Register 30" in group.long (0x78+0x100)++0x03 line.long 0x00 "PCCTRL30,Pulse Counter Control Register 30" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end tree "Channel 31" group.long 0x7C++0x03 line.long 0x00 "CHCTRL31,Channel Control Register 31" bitfld.long 0x00 25. " TRGCL ,Trigger status clear bit" "No clear,Clear" bitfld.long 0x00 24. " SWTRG ,Software trigger bit" "Not triggered,Triggered" bitfld.long 0x00 23. " RCEN ,Range comparator enable bit" "Disabled,Enabled" bitfld.long 0x00 22. " RCINVSEL ,Range comparator inverted range selection bit" "Outside,Inside" newline bitfld.long 0x00 18.--20. " RCSEL ,Range comparator select bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " SMTIME ,Sampling time select bits" "ST0,ST1,ST2,ST3" bitfld.long 0x00 14. " DP ,Data protection enable bit" "Disabled,Enabled" bitfld.long 0x00 12.--13. " RSMRST ,Resume/restart/stop select bits" "Stop,Resume,Restart,?..." newline bitfld.long 0x00 8.--11. " CHPRI ,Logical channel priority" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Lowest" bitfld.long 0x00 6.--7. " TRGTYP ,Trigger type bits" "SW,SW/HW,Done,Idle" sif (cpuis("S6J342?H*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,AN004,AN005,AN006,,AN008,AN009,AN010,AN011,,AN013,AN014,,,AN017,AN018,AN019,AN020,AN021,AN022,,,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" elif (cpuis("S6J342?F*")) bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,,,AN003,,AN005,,,AN008,,AN010,,,AN013,AN014,,,AN017,,AN019,,AN021,AN022,,,AN025,,AN027,AN028,,AN030,,AN100,,AN102,,,,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,,,,AN118,AN119,AN120,AN121,,AN123,,AN125,,AN127,AN128,AN129,?..." else bitfld.long 0x00 0.--5. " ANIN ,Analog input selection bits" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,AN028,AN029,AN030,AN031,AN100,AN101,AN102,AN103,AN104,AN105,AN106,AN107,AN108,AN109,AN110,AN111,AN112,AN113,AN114,AN115,AN116,AN117,AN118,AN119,AN120,AN121,AN122,AN123,AN124,AN125,AN126,AN127,AN128,AN129,AN130,AN131" endif rgroup.word 0x13E++0x01 line.word 0x00 "CHSTAT31,Channel Status Register 31" bitfld.word 0x00 5. " RCOTF ,Range comparator over threshold flag" "Less/equal,More" bitfld.word 0x00 4. " PCIRQ ,Pulse counter interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " RCIRQ ,Range comparator interrupt flag" "No interrupt,Interrupt" newline bitfld.word 0x00 2. " GRPIRQ ,Group interrupted interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " CDONEIRQ ,Conversion done interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " TRGST ,Trigger status flag" "Not triggered,Triggered" hgroup.word (0x13E+0x80)++0x01 hide.word 0x00 "CD31,Conversion Data Register 31" in group.long (0x7C+0x100)++0x03 line.long 0x00 "PCCTRL31,Pulse Counter Control Register 31" rbitfld.long 0x00 24.--28. " PCTNCT ,Pulse negative counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PCTNRL ,Pulse negative counter reload value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 8.--15. 1. " PCTPCT ,Pulse positive counter value" hexmask.long.byte 0x00 0.--7. 1. " PCTPRL ,Pulse positive counter reload value" tree.end newline rgroup.long 0x300++0x03 line.long 0x00 "CDONEIRQ,A/D Conversion Done Interrupt Flag Register" bitfld.long 0x00 31. " CDONEIRQ[31] ,Conversion done interrupt flag 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Conversion done interrupt flag 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Conversion done interrupt flag 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Conversion done interrupt flag 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Conversion done interrupt flag 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Conversion done interrupt flag 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Conversion done interrupt flag 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Conversion done interrupt flag 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Conversion done interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Conversion done interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Conversion done interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Conversion done interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Conversion done interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Conversion done interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Conversion done interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Conversion done interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Conversion done interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Conversion done interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Conversion done interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Conversion done interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Conversion done interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Conversion done interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Conversion done interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Conversion done interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Conversion done interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Conversion done interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Conversion done interrupt flag 0" "No interrupt,Interrupt" group.long 0x308++0x03 line.long 0x00 "CDONEIRQE,A/D Conversion Done Interrupt Enable Register" bitfld.long 0x00 31. " CDONEIRQE[31] ,Conversion done interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Conversion done interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Conversion done interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Conversion done interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Conversion done interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Conversion done interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Conversion done interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Conversion done interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Conversion done interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Conversion done interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Conversion done interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Conversion done interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Conversion done interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Conversion done interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Conversion done interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Conversion done interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Conversion done interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Conversion done interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Conversion done interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Conversion done interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Conversion done interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Conversion done interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Conversion done interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Conversion done interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Conversion done interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Conversion done interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Conversion done interrupt enable 0" "Disabled,Enabled" group.long 0x310++0x03 line.long 0x00 "CDONEIRQC,A/D Conversion Done Interrupt Clear Register" bitfld.long 0x00 31. " CDONEIRQC[31] ,Conversion done interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Conversion done interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Conversion done interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Conversion done interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Conversion done interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Conversion done interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Conversion done interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Conversion done interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Conversion done interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Conversion done interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Conversion done interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Conversion done interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Conversion done interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Conversion done interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Conversion done interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Conversion done interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Conversion done interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Conversion done interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Conversion done interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Conversion done interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Conversion done interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Conversion done interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Conversion done interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Conversion done interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Conversion done interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Conversion done interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Conversion done interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Conversion done interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Conversion done interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Conversion done interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Conversion done interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Conversion done interrupt clear 0" "No clear,Clear" rgroup.long 0x318++0x03 line.long 0x00 "GRPIRQ,Group Interrupted Interrupt Flag Register" bitfld.long 0x00 31. " GRPIRQ[31] ,Group interrupted interrupt flag 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Group interrupted interrupt flag 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Group interrupted interrupt flag 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Group interrupted interrupt flag 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Group interrupted interrupt flag 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Group interrupted interrupt flag 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Group interrupted interrupt flag 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Group interrupted interrupt flag 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Group interrupted interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt flag 0" "No interrupt,Interrupt" group.long 0x320++0x03 line.long 0x00 "GRPIRQE,Group Interrupted Interrupt Enable Register" bitfld.long 0x00 31. " GRPIRQE[31] ,Group interrupted interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Group interrupted interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Group interrupted interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Group interrupted interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Group interrupted interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Group interrupted interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Group interrupted interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Group interrupted interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Group interrupted interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt enable 0" "Disabled,Enabled" group.long 0x328++0x03 line.long 0x00 "GRPIRQC,Group Interrupted Interrupt Clear Register" bitfld.long 0x00 31. " GRPIRQC[31] ,Group interrupted interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Group interrupted interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Group interrupted interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Group interrupted interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Group interrupted interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Group interrupted interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Group interrupted interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Group interrupted interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Group interrupted interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Group interrupted interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Group interrupted interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Group interrupted interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Group interrupted interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Group interrupted interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Group interrupted interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Group interrupted interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Group interrupted interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Group interrupted interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Group interrupted interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Group interrupted interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Group interrupted interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Group interrupted interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Group interrupted interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Group interrupted interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Group interrupted interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Group interrupted interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Group interrupted interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Group interrupted interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Group interrupted interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Group interrupted interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Group interrupted interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Group interrupted interrupt clear 0" "No clear,Clear" rgroup.long 0x330++0x03 line.long 0x00 "RCIRQ,Range Comparator Interrupt Flag Register" bitfld.long 0x00 31. " RCIRQ[31] ,Range comparator interrupt flag 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Range comparator interrupt flag 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Range comparator interrupt flag 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Range comparator interrupt flag 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Range comparator interrupt flag 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Range comparator interrupt flag 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Range comparator interrupt flag 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Range comparator interrupt flag 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Range comparator interrupt flag 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Range comparator interrupt flag 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Range comparator interrupt flag 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Range comparator interrupt flag 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt flag 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Range comparator interrupt flag 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Range comparator interrupt flag 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Range comparator interrupt flag 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt flag 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Range comparator interrupt flag 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Range comparator interrupt flag 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Range comparator interrupt flag 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt flag 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Range comparator interrupt flag 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Range comparator interrupt flag 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Range comparator interrupt flag 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt flag 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Range comparator interrupt flag 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Range comparator interrupt flag 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Range comparator interrupt flag 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt flag 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Range comparator interrupt flag 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Range comparator interrupt flag 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Range comparator interrupt flag 0" "No interrupt,Interrupt" group.long 0x338++0x03 line.long 0x00 "RCIRQE,Range Comparator Interrupt Enable Register" bitfld.long 0x00 31. " RCIRQE[31] ,Range comparator interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Range comparator interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Range comparator interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Range comparator interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Range comparator interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Range comparator interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Range comparator interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Range comparator interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Range comparator interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Range comparator interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Range comparator interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Range comparator interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Range comparator interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Range comparator interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Range comparator interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Range comparator interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Range comparator interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Range comparator interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Range comparator interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Range comparator interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Range comparator interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Range comparator interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Range comparator interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Range comparator interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Range comparator interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Range comparator interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Range comparator interrupt enable 0" "Disabled,Enabled" group.long 0x340++0x03 line.long 0x00 "RCIRQC,Range Comparator Interrupt Clear Register" bitfld.long 0x00 31. " RCIRQC[31] ,Range comparator interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Range comparator interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Range comparator interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Range comparator interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Range comparator interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Range comparator interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Range comparator interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Range comparator interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Range comparator interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Range comparator interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Range comparator interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Range comparator interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Range comparator interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Range comparator interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Range comparator interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Range comparator interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Range comparator interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Range comparator interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Range comparator interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Range comparator interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Range comparator interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Range comparator interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Range comparator interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Range comparator interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Range comparator interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Range comparator interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Range comparator interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Range comparator interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Range comparator interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Range comparator interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Range comparator interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Range comparator interrupt clear 0" "No clear,Clear" rgroup.long 0x348++0x03 line.long 0x00 "PCIRQ,Pulse Counter Interrupt Flag Register" bitfld.long 0x00 31. " PCIRQ[31] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 27. " [27] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 23. " [23] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt flag $1" "No interrupt,Interrupt" group.long 0x350++0x03 line.long 0x00 "PCIRQE,Pulse Counter Interrupt Enable Register" bitfld.long 0x00 31. " PCIRQE[31] ,Pulse counter interrupt enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Pulse counter interrupt enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Pulse counter interrupt enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Pulse counter interrupt enable 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Pulse counter interrupt enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Pulse counter interrupt enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Pulse counter interrupt enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Pulse counter interrupt enable 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Pulse counter interrupt enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt enable 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt enable 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt enable 0" "Disabled,Enabled" group.long 0x358++0x03 line.long 0x00 "PCIRQC,Pulse Counter Interrupt Clear Register" bitfld.long 0x00 31. " PCIRQC[31] ,Pulse counter interrupt clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,Pulse counter interrupt clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,Pulse counter interrupt clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,Pulse counter interrupt clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,Pulse counter interrupt clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,Pulse counter interrupt clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,Pulse counter interrupt clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,Pulse counter interrupt clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,Pulse counter interrupt clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,Pulse counter interrupt clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,Pulse counter interrupt clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,Pulse counter interrupt clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,Pulse counter interrupt clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,Pulse counter interrupt clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,Pulse counter interrupt clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,Pulse counter interrupt clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,Pulse counter interrupt clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,Pulse counter interrupt clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,Pulse counter interrupt clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,Pulse counter interrupt clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,Pulse counter interrupt clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,Pulse counter interrupt clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,Pulse counter interrupt clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,Pulse counter interrupt clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,Pulse counter interrupt clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,Pulse counter interrupt clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,Pulse counter interrupt clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,Pulse counter interrupt clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,Pulse counter interrupt clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,Pulse counter interrupt clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,Pulse counter interrupt clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,Pulse counter interrupt clear 0" "No clear,Clear" rgroup.long 0x360++0x03 line.long 0x00 "TRGST,A/D Channel Trigger Status Flag Register" bitfld.long 0x00 31. " TRGST[31] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 30. " [30] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 29. " [29] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 28. " [28] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 26. " [26] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 25. " [25] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 24. " [24] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 22. " [22] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 21. " [21] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 20. " [20] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 18. " [18] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 17. " [17] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 16. " [16] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 14. " [14] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 13. " [13] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 12. " [12] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 10. " [10] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 9. " [9] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 8. " [8] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 6. " [6] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 5. " [5] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 4. " [4] ,A/D channel trigger status flag" "Not requested,Requested" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 2. " [2] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 1. " [1] ,A/D channel trigger status flag" "Not requested,Requested" bitfld.long 0x00 0. " [0] ,A/D channel trigger status flag" "Not requested,Requested" group.long 0x368++0x03 line.long 0x00 "TRGCL,A/D Channel Trigger Clear Register" bitfld.long 0x00 31. " TRGCL[31] ,A/D channel trigger status clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,A/D channel trigger status clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,A/D channel trigger status clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,A/D channel trigger status clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger status clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,A/D channel trigger status clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,A/D channel trigger status clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,A/D channel trigger status clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger status clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,A/D channel trigger status clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,A/D channel trigger status clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,A/D channel trigger status clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger status clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,A/D channel trigger status clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,A/D channel trigger status clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,A/D channel trigger status clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger status clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,A/D channel trigger status clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger status clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger status clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger status clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger status clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger status clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,A/D channel trigger status clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger status clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger status clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,A/D channel trigger status clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger status clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger status clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,A/D channel trigger status clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger status clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger status clear 0" "No clear,Clear" rgroup.long 0x378++0x03 line.long 0x00 "TRGOR,A/D Channel Trigger Overrun Flag Register" bitfld.long 0x00 31. " TRGOR[31] ,A/D channel trigger overrun flag 31" "No overrun,Overrun" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun flag 30" "No overrun,Overrun" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun flag 29" "No overrun,Overrun" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun flag 28" "No overrun,Overrun" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger overrun flag 27" "No overrun,Overrun" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun flag 26" "No overrun,Overrun" bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun flag 25" "No overrun,Overrun" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun flag 24" "No overrun,Overrun" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger overrun flag 23" "No overrun,Overrun" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun flag 22" "No overrun,Overrun" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun flag 21" "No overrun,Overrun" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun flag 20" "No overrun,Overrun" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun flag 19" "No overrun,Overrun" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun flag 18" "No overrun,Overrun" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun flag 17" "No overrun,Overrun" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun flag 16" "No overrun,Overrun" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun flag 15" "No overrun,Overrun" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun flag 14" "No overrun,Overrun" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun flag 13" "No overrun,Overrun" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun flag 12" "No overrun,Overrun" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun flag 11" "No overrun,Overrun" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun flag 10" "No overrun,Overrun" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun flag 9" "No overrun,Overrun" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun flag 8" "No overrun,Overrun" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun flag 7" "No overrun,Overrun" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun flag 6" "No overrun,Overrun" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun flag 5" "No overrun,Overrun" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun flag 4" "No overrun,Overrun" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun flag 3" "No overrun,Overrun" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun flag 2" "No overrun,Overrun" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun flag 1" "No overrun,Overrun" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun flag 0" "No overrun,Overrun" group.long 0x380++0x03 line.long 0x00 "TRGORC,A/D Channel Trigger Overrun Clear Register" bitfld.long 0x00 31. " TRGORC[31] ,A/D channel trigger overrun clear 31" "No clear,Clear" bitfld.long 0x00 30. " [30] ,A/D channel trigger overrun clear 30" "No clear,Clear" bitfld.long 0x00 29. " [29] ,A/D channel trigger overrun clear 29" "No clear,Clear" bitfld.long 0x00 28. " [28] ,A/D channel trigger overrun clear 28" "No clear,Clear" newline bitfld.long 0x00 27. " [27] ,A/D channel trigger overrun clear 27" "No clear,Clear" bitfld.long 0x00 26. " [26] ,A/D channel trigger overrun clear 26" "No clear,Clear" bitfld.long 0x00 25. " [25] ,A/D channel trigger overrun clear 25" "No clear,Clear" bitfld.long 0x00 24. " [24] ,A/D channel trigger overrun clear 24" "No clear,Clear" newline bitfld.long 0x00 23. " [23] ,A/D channel trigger overrun clear 23" "No clear,Clear" bitfld.long 0x00 22. " [22] ,A/D channel trigger overrun clear 22" "No clear,Clear" bitfld.long 0x00 21. " [21] ,A/D channel trigger overrun clear 21" "No clear,Clear" bitfld.long 0x00 20. " [20] ,A/D channel trigger overrun clear 20" "No clear,Clear" newline bitfld.long 0x00 19. " [19] ,A/D channel trigger overrun clear 19" "No clear,Clear" bitfld.long 0x00 18. " [18] ,A/D channel trigger overrun clear 18" "No clear,Clear" bitfld.long 0x00 17. " [17] ,A/D channel trigger overrun clear 17" "No clear,Clear" bitfld.long 0x00 16. " [16] ,A/D channel trigger overrun clear 16" "No clear,Clear" newline bitfld.long 0x00 15. " [15] ,A/D channel trigger overrun clear 15" "No clear,Clear" bitfld.long 0x00 14. " [14] ,A/D channel trigger overrun clear 14" "No clear,Clear" bitfld.long 0x00 13. " [13] ,A/D channel trigger overrun clear 13" "No clear,Clear" bitfld.long 0x00 12. " [12] ,A/D channel trigger overrun clear 12" "No clear,Clear" newline bitfld.long 0x00 11. " [11] ,A/D channel trigger overrun clear 11" "No clear,Clear" bitfld.long 0x00 10. " [10] ,A/D channel trigger overrun clear 10" "No clear,Clear" bitfld.long 0x00 9. " [9] ,A/D channel trigger overrun clear 9" "No clear,Clear" bitfld.long 0x00 8. " [8] ,A/D channel trigger overrun clear 8" "No clear,Clear" newline bitfld.long 0x00 7. " [7] ,A/D channel trigger overrun clear 7" "No clear,Clear" bitfld.long 0x00 6. " [6] ,A/D channel trigger overrun clear 6" "No clear,Clear" bitfld.long 0x00 5. " [5] ,A/D channel trigger overrun clear 5" "No clear,Clear" bitfld.long 0x00 4. " [4] ,A/D channel trigger overrun clear 4" "No clear,Clear" newline bitfld.long 0x00 3. " [3] ,A/D channel trigger overrun clear 3" "No clear,Clear" bitfld.long 0x00 2. " [2] ,A/D channel trigger overrun clear 2" "No clear,Clear" bitfld.long 0x00 1. " [1] ,A/D channel trigger overrun clear 1" "No clear,Clear" bitfld.long 0x00 0. " [0] ,A/D channel trigger overrun clear 0" "No clear,Clear" group.long 0x370++0x03 line.long 0x00 "RCOTF,Range Comparator Over Threshold Flag Register" bitfld.long 0x00 31. " RCOTF[31] ,Range comparator over threshold flag 31" "Less/equal,More" bitfld.long 0x00 30. " [30] ,Range comparator over threshold flag 30" "Less/equal,More" bitfld.long 0x00 29. " [29] ,Range comparator over threshold flag 29" "Less/equal,More" bitfld.long 0x00 28. " [28] ,Range comparator over threshold flag 28" "Less/equal,More" newline bitfld.long 0x00 27. " [27] ,Range comparator over threshold flag 27" "Less/equal,More" bitfld.long 0x00 26. " [26] ,Range comparator over threshold flag 26" "Less/equal,More" bitfld.long 0x00 25. " [25] ,Range comparator over threshold flag 25" "Less/equal,More" bitfld.long 0x00 24. " [24] ,Range comparator over threshold flag 24" "Less/equal,More" newline bitfld.long 0x00 23. " [23] ,Range comparator over threshold flag 23" "Less/equal,More" bitfld.long 0x00 22. " [22] ,Range comparator over threshold flag 22" "Less/equal,More" bitfld.long 0x00 21. " [21] ,Range comparator over threshold flag 21" "Less/equal,More" bitfld.long 0x00 20. " [20] ,Range comparator over threshold flag 20" "Less/equal,More" newline bitfld.long 0x00 19. " [19] ,Range comparator over threshold flag 19" "Less/equal,More" bitfld.long 0x00 18. " [18] ,Range comparator over threshold flag 18" "Less/equal,More" bitfld.long 0x00 17. " [17] ,Range comparator over threshold flag 17" "Less/equal,More" bitfld.long 0x00 16. " [16] ,Range comparator over threshold flag 16" "Less/equal,More" newline bitfld.long 0x00 15. " [15] ,Range comparator over threshold flag 15" "Less/equal,More" bitfld.long 0x00 14. " [14] ,Range comparator over threshold flag 14" "Less/equal,More" bitfld.long 0x00 13. " [13] ,Range comparator over threshold flag 13" "Less/equal,More" bitfld.long 0x00 12. " [12] ,Range comparator over threshold flag 12" "Less/equal,More" newline bitfld.long 0x00 11. " [11] ,Range comparator over threshold flag 11" "Less/equal,More" bitfld.long 0x00 10. " [10] ,Range comparator over threshold flag 10" "Less/equal,More" bitfld.long 0x00 9. " [9] ,Range comparator over threshold flag 9" "Less/equal,More" bitfld.long 0x00 8. " [8] ,Range comparator over threshold flag 8" "Less/equal,More" newline bitfld.long 0x00 7. " [7] ,Range comparator over threshold flag 7" "Less/equal,More" bitfld.long 0x00 6. " [6] ,Range comparator over threshold flag 6" "Less/equal,More" bitfld.long 0x00 5. " [5] ,Range comparator over threshold flag 5" "Less/equal,More" bitfld.long 0x00 4. " [4] ,Range comparator over threshold flag 4" "Less/equal,More" newline bitfld.long 0x00 3. " [3] ,Range comparator over threshold flag 3" "Less/equal,More" bitfld.long 0x00 2. " [2] ,Range comparator over threshold flag 2" "Less/equal,More" bitfld.long 0x00 1. " [1] ,Range comparator over threshold flag 1" "Less/equal,More" bitfld.long 0x00 0. " [0] ,Range comparator over threshold flag 0" "Less/equal,More" newline group.word 0x388++0x01 line.word 0x00 "CDDS0,Conversion Done DMA Select Register 0" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38A++0x01 line.word 0x00 "CDDS1,Conversion Done DMA Select Register 1" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38C++0x01 line.word 0x00 "CDDS2,Conversion Done DMA Select Register 2" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x38E++0x01 line.word 0x00 "CDDS3,Conversion Done DMA Select Register 3" bitfld.word 0x00 6. " CDCHEN ,Channel conversion done DMA dedicated interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0.--5. " CDCHNUM ,Number of logical channel selected for conversion done interrupt for triggering DMA request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." group.word 0x390++0x03 line.word 0x00 "CT,A/D Converter Comparison Time Setting Register" line.word 0x02 "RT,A/D Converter Resumption Time Setting Register" hexmask.word.byte 0x02 0.--7. 1. " RT ,Resumption time" group.word 0x394++0x01 line.word 0x00 "ST0,A/D Converter Sampling Time Setting Register 0" group.word 0x396++0x01 line.word 0x00 "ST1,A/D Converter Sampling Time Setting Register 1" group.word 0x398++0x01 line.word 0x00 "ST2,A/D Converter Sampling Time Setting Register 2" group.word 0x39A++0x01 line.word 0x00 "ST3,A/D Converter Sampling Time Setting Register 3" group.word 0x39C++0x03 line.word 0x00 "OCV,A/D Converter Offset Compensation Setting Register" hexmask.word.byte 0x00 0.--7. 1. " OCV ,Offset compensation value" line.word 0x02 "GCV,A/D Converter Gain Compensation Setting Register" bitfld.word 0x02 0.--4. " GCV ,Gain compensation value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.w(ad:0xB48C0400+0x3A0)&0x10)==0x10) group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" bitfld.word 0x00 6. " FSTP ,Forced stop" "No stop,Stop" bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" else group.word 0x3A0++0x01 line.word 0x00 "CTRL,A/D Converter Global Control Register" bitfld.word 0x00 7. " PDDMD ,Power-down disable mode" "No,Yes" textfld " " bitfld.word 0x00 5. " FRCMD ,Full range comparator mode" "8 bit,12 bit" bitfld.word 0x00 4. " FSMD ,Forced stop mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " ACHMD ,ACH register mode" "Direct,Latched" bitfld.word 0x00 2. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " RES ,A/D conversion resolution" "12 bit,10 bit,12 bit,8 bit" endif rgroup.word 0x3A2++0x01 line.word 0x00 "STAT,A/D Converter Global Status Register" bitfld.word 0x00 6. " BUSY ,A/D converter busy flag" "Not busy,Busy" bitfld.word 0x00 0.--5. " ACH ,Converted logical channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B0+0x01)++0x00 line.byte 0x00 "RCOH0,Range Comparator Upper Threshold Register 0" group.byte 0x3B0++0x00 line.byte 0x00 "RCOL0,Range Comparator Lower Threshold Register 0" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D0+0x10)++0x01 line.word 0x00 "FRCOH0,Full Range Comparator Upper Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D0++0x01 line.word 0x00 "FRCOL0,Full Range Comparator Lower Threshold Register 0" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B2+0x01)++0x00 line.byte 0x00 "RCOH1,Range Comparator Upper Threshold Register 1" group.byte 0x3B2++0x00 line.byte 0x00 "RCOL1,Range Comparator Lower Threshold Register 1" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D2+0x10)++0x01 line.word 0x00 "FRCOH1,Full Range Comparator Upper Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D2++0x01 line.word 0x00 "FRCOL1,Full Range Comparator Lower Threshold Register 1" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B4+0x01)++0x00 line.byte 0x00 "RCOH2,Range Comparator Upper Threshold Register 2" group.byte 0x3B4++0x00 line.byte 0x00 "RCOL2,Range Comparator Lower Threshold Register 2" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D4+0x10)++0x01 line.word 0x00 "FRCOH2,Full Range Comparator Upper Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D4++0x01 line.word 0x00 "FRCOL2,Full Range Comparator Lower Threshold Register 2" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B6+0x01)++0x00 line.byte 0x00 "RCOH3,Range Comparator Upper Threshold Register 3" group.byte 0x3B6++0x00 line.byte 0x00 "RCOL3,Range Comparator Lower Threshold Register 3" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D6+0x10)++0x01 line.word 0x00 "FRCOH3,Full Range Comparator Upper Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D6++0x01 line.word 0x00 "FRCOL3,Full Range Comparator Lower Threshold Register 3" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3B8+0x01)++0x00 line.byte 0x00 "RCOH4,Range Comparator Upper Threshold Register 4" group.byte 0x3B8++0x00 line.byte 0x00 "RCOL4,Range Comparator Lower Threshold Register 4" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3D8+0x10)++0x01 line.word 0x00 "FRCOH4,Full Range Comparator Upper Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3D8++0x01 line.word 0x00 "FRCOL4,Full Range Comparator Lower Threshold Register 4" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3BA+0x01)++0x00 line.byte 0x00 "RCOH5,Range Comparator Upper Threshold Register 5" group.byte 0x3BA++0x00 line.byte 0x00 "RCOL5,Range Comparator Lower Threshold Register 5" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DA+0x10)++0x01 line.word 0x00 "FRCOH5,Full Range Comparator Upper Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DA++0x01 line.word 0x00 "FRCOL5,Full Range Comparator Lower Threshold Register 5" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3BC+0x01)++0x00 line.byte 0x00 "RCOH6,Range Comparator Upper Threshold Register 6" group.byte 0x3BC++0x00 line.byte 0x00 "RCOL6,Range Comparator Lower Threshold Register 6" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DC+0x10)++0x01 line.word 0x00 "FRCOH6,Full Range Comparator Upper Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DC++0x01 line.word 0x00 "FRCOL6,Full Range Comparator Lower Threshold Register 6" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif if ((per.w(ad:0xB48C0400+0x3A0)&0x20)==0x20) group.byte (0x3BE+0x01)++0x00 line.byte 0x00 "RCOH7,Range Comparator Upper Threshold Register 7" group.byte 0x3BE++0x00 line.byte 0x00 "RCOL7,Range Comparator Lower Threshold Register 7" else if ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x03) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word.byte 0x00 0.--7. 1. " FRCOL ,Full range comparator lower threshold value" elif ((per.w(ad:0xB48C0400+0x3A0)&0x03)==0x01) group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--9. 1. " FRCOL ,Full range comparator lower threshold value" else group.word (0x3DE+0x10)++0x01 line.word 0x00 "FRCOH7,Full Range Comparator Upper Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOH ,Full range comparator upper threshold value" group.word 0x3DE++0x01 line.word 0x00 "FRCOL7,Full Range Comparator Lower Threshold Register 7" hexmask.word 0x00 0.--11. 1. " FRCOL ,Full range comparator lower threshold value" endif endif group.byte 0x3C0++0x00 line.byte 0x00 "MCCTRL0,A/D Multiple Conversion Channel Control Register 0" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E0++0x00 line.byte 0x00 "MCSTAT0,A/D Multiple Conversion Channel Status Register 0" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C1++0x00 line.byte 0x00 "MCCTRL1,A/D Multiple Conversion Channel Control Register 1" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E1++0x00 line.byte 0x00 "MCSTAT1,A/D Multiple Conversion Channel Status Register 1" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C2++0x00 line.byte 0x00 "MCCTRL2,A/D Multiple Conversion Channel Control Register 2" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E2++0x00 line.byte 0x00 "MCSTAT2,A/D Multiple Conversion Channel Status Register 2" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." group.byte 0x3C3++0x00 line.byte 0x00 "MCCTRL3,A/D Multiple Conversion Channel Control Register 3" bitfld.byte 0x00 6. " AVRHSEL ,A/D reference voltage AVRH select" "Not selected,Selected" bitfld.byte 0x00 5. " AVRLSEL ,A/D reference voltage AVRL select" "Not selected,Selected" bitfld.byte 0x00 4. " ICIRQY ,Intra channel interrupt ability for multiple conversion logical channel disable" "No,Yes" bitfld.byte 0x00 0.--3. " CNVNUM ,Number of conversion for multiple conversion channel" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.byte 0x3E3++0x00 line.byte 0x00 "MCSTAT3,A/D Multiple Conversion Channel Status Register 3" bitfld.byte 0x00 0.--4. " MCCNT ,Multiple conversion counter" "None,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." width 0x0B endif tree.end tree.end tree "PWU (Partial Wakeup Control)" base ad:0xB48C0800 width 7. group.byte 0x00++0x00 line.byte 0x00 "PWUC,PWU Control Register" bitfld.byte 0x00 7. " PWUE ,PWU mode enable" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " ADSTS ,A/D conversion start time setting bits" sif cpuis("S6J351*") group.word 0x04++0x01 line.word 0x00 "ADTC,A/D Conversion Request Trigger Control Register" bitfld.word 0x00 15. " ADHWTS ,A/D conversion hardware trigger select bit" "RIC_RESIN.RESSEL,PWU_ADT" bitfld.word 0x00 8.--12. " ADSTCH ,A/D conversion start channel setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.byte 0x01++0x00 line.byte 0x00 "ADTC,A/D Conversion Request Trigger Control Register" bitfld.byte 0x00 7. " ADHWTS ,A/D conversion hardware trigger select bit" "RIC_RESIN.RESSEL,PWU_ADT" bitfld.byte 0x00 0.--4. " ADSTCH ,A/D conversion start channel setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x04++0x00 line.byte 0x00 "ADOCS,A/D Conversion Offset Compensation Value Select Register" bitfld.byte 0x00 1. " OCVSEL[1] ,A/D converter offset compensation value select" "OCV,Proper trim" bitfld.byte 0x00 0. " [0] ,A/D converter offset compensation value select" "OCV,Proper trim" endif width 0x0B tree.end tree "PRGCRC (Programmable CRC)" base ad:0xB8018000 width 6. if ((per.l(ad:0xB8018000+0x0C)&0x10000000)==0x00) group.long 0x00++0x17 line.long 0x00 "POLY,CRC Polynomial Register" line.long 0x04 "SEED,CRC Seed Register" line.long 0x08 "FXOR,CRC Final XOR Register" line.long 0x0C "CFG,CRC Configuration Register" rbitfld.long 0x0C 28. " LOCK ,CRC engine status bit" "Ready,Busy" bitfld.long 0x0C 26. " CDEN ,DMA request enable bit" "Disabled,Enabled" bitfld.long 0x0C 25. " CIEN ,CRC interrupt enable bit to CPU" "Disabled,Enabled" rbitfld.long 0x0C 24. " CIRQ ,CRC interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x0C 22.--23. " SZ ,CRC input data size configuration bits" "8,16,24,32" bitfld.long 0x0C 16.--21. " LEN ,CRC polynomial/checksum length configuration bits" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x0C 11. " RIBIT ,Reflect input bits" "Disabled,Enabled" bitfld.long 0x0C 10. " RIBYT ,Reflect input bytes" "Disabled,Enabled" newline bitfld.long 0x0C 9. " ROBIT ,Reflect output bits" "Disabled,Enabled" bitfld.long 0x0C 8. " ROBYT ,Reflect output bytes" "Disabled,Enabled" bitfld.long 0x0C 0. " CIRQCLR ,Interrupt clear" "No clear,Clear" line.long 0x10 "WR,CRC Write Register" line.long 0x14 "RD,CRC Read Register" else rgroup.long 0x00++0x17 line.long 0x00 "POLY,CRC Polynomial Register" line.long 0x04 "SEED,CRC Seed Register" line.long 0x08 "FXOR,CRC Final XOR Register" line.long 0x0C "CFG,CRC Configuration Register" rbitfld.long 0x0C 28. " LOCK ,CRC engine status bit" "Ready,Busy" bitfld.long 0x0C 26. " CDEN ,DMA request enable bit" "Disabled,Enabled" bitfld.long 0x0C 25. " CIEN ,CRC interrupt enable bit to CPU" "Disabled,Enabled" rbitfld.long 0x0C 24. " CIRQ ,CRC interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x0C 22.--23. " SZ ,CRC input data size configuration bits" "8,16,24,32" bitfld.long 0x0C 16.--21. " LEN ,CRC polynomial/checksum length configuration bits" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x0C 11. " RIBIT ,Reflect input bits" "Disabled,Enabled" bitfld.long 0x0C 10. " RIBYT ,Reflect input bytes" "Disabled,Enabled" newline bitfld.long 0x0C 9. " ROBIT ,Reflect output bits" "Disabled,Enabled" bitfld.long 0x0C 8. " ROBYT ,Reflect output bytes" "Disabled,Enabled" bitfld.long 0x0C 0. " CIRQCLR ,Interrupt clear" "No clear,Clear" line.long 0x10 "WR,CRC Write Register" line.long 0x14 "RD,CRC Read Register" endif width 0x0B tree.end tree "CM (Clock Monitor)" base ad:0xB0643000 width 10. group.long 0x00++0x03 line.long 0x00 "CKOTCNTR,Clock Output Function Control Register" bitfld.long 0x00 24. " ENCLKO ,Clock output enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " CKOUTDIV ,Clock division bits" "Not divided,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 0.--3. " CKSEL ,Clock select bits" "Fast-CR,Slow-CR,Main,Sub,PLL0,CLK_CAN,CLK_LCP0,CLK_LCP0A,SSCG PPL0,CLK_LCP1,CLK_LCP1A,CLK_SYSC0H,,,,Tied to low" width 0x0B tree.end tree "BUSDF (Bus Diagnosis Function)" base ad:0xB4719000 width 11. if ((per.w(ad:0xB4719000+0)&0xFF02)>0x00) group.word 0x0++0x01 "Common PERI #0" line.word 0x00 "BUSDIGSR0,Bus Diagnosis Status Register 0" rbitfld.word 0x00 15. " DER[3] ,Bits 31:24 data parity error" "No error,Error" rbitfld.word 0x00 14. " DER[2] ,Bits 23:16 data parity error" "No error,Error" rbitfld.word 0x00 13. " DER[1] ,Bits 15:8 data parity error" "No error,Error" rbitfld.word 0x00 12. " DER[0] ,Bits 7:0 data parity error" "No error,Error" newline rbitfld.word 0x00 11. " AER[3] ,Bits 31:24 address parity error" "No error,Error" rbitfld.word 0x00 10. " AER[2] ,Bits 23:16 address parity error" "No error,Error" rbitfld.word 0x00 9. " AER[1] ,Bits 15:8 address parity error" "No error,Error" rbitfld.word 0x00 8. " AER[0] ,Bits 7:0 address parity error" "No error,Error" newline bitfld.word 0x00 7. " PECLR ,Parity error clear" "No clear,Clear" rbitfld.word 0x00 1. " CNER ,Control parity error" "No error,Error" rbitfld.word 0x00 0. " RDWR ,Data direction" "Read,Write" else group.word 0x0++0x01 "Common PERI #0" line.word 0x00 "BUSDIGSR0,Bus Diagnosis Status Register 0" rbitfld.word 0x00 15. " DER[3] ,Bits 31:24 data parity error" "No error,Error" rbitfld.word 0x00 14. " DER[2] ,Bits 23:16 data parity error" "No error,Error" rbitfld.word 0x00 13. " DER[1] ,Bits 15:8 data parity error" "No error,Error" rbitfld.word 0x00 12. " DER[0] ,Bits 7:0 data parity error" "No error,Error" newline rbitfld.word 0x00 11. " AER[3] ,Bits 31:24 address parity error" "No error,Error" rbitfld.word 0x00 10. " AER[2] ,Bits 23:16 address parity error" "No error,Error" rbitfld.word 0x00 9. " AER[1] ,Bits 15:8 address parity error" "No error,Error" rbitfld.word 0x00 8. " AER[0] ,Bits 7:0 address parity error" "No error,Error" newline bitfld.word 0x00 7. " PECLR ,Parity error clear" "No clear,Clear" rbitfld.word 0x00 1. " CNER ,Control parity error" "No error,Error" endif group.word (0x0+0x06)++0x01 line.word 0x00 "BUSTSTR0,Bus Diagnosis Test Register 0" bitfld.word 0x00 14.--15. " KEY ,Key" "0,1,2,3" bitfld.word 0x00 11. " CEN ,Control error" "No error,Error" bitfld.word 0x00 8. " AHBEN ,AHB parity error generation enable" "Disabled,Enabled" newline bitfld.word 0x00 7. " DEN[3] ,Bits 31:24 data parity error" "No error,Error" bitfld.word 0x00 6. " DEN[2] ,Bits 23:16 data parity error" "No error,Error" bitfld.word 0x00 5. " DEN[1] ,Bits 15:8 data parity error" "No error,Error" bitfld.word 0x00 4. " DEN[0] ,Bits 7:0 data parity error" "No error,Error" newline bitfld.word 0x00 3. " AEN[3] ,Bits 31:24 address parity error" "No error,Error" bitfld.word 0x00 2. " AEN[2] ,Bits 23:16 address parity error" "No error,Error" bitfld.word 0x00 1. " AEN[1] ,Bits 15:8 address parity error" "No error,Error" bitfld.word 0x00 0. " AEN[0] ,Bits 7:0 address parity error" "No error,Error" if ((per.w(ad:0xB4719000+0x0)&0xFF02)>0x00) rgroup.long (0x0+0x08)++0x03 line.long 0x00 "BUSADR0,Bus Diagnosis Address Register 0" else hgroup.long (0x0+0x08)++0x03 hide.long 0x00 "BUSADR0,Bus Diagnosis Address Register 0" endif if ((per.w(ad:0xB4719000+1)&0xFF02)>0x00) group.word 0x14++0x01 "Common PERI #1" line.word 0x00 "BUSDIGSR1,Bus Diagnosis Status Register 1" rbitfld.word 0x00 15. " DER[3] ,Bits 31:24 data parity error" "No error,Error" rbitfld.word 0x00 14. " DER[2] ,Bits 23:16 data parity error" "No error,Error" rbitfld.word 0x00 13. " DER[1] ,Bits 15:8 data parity error" "No error,Error" rbitfld.word 0x00 12. " DER[0] ,Bits 7:0 data parity error" "No error,Error" newline rbitfld.word 0x00 11. " AER[3] ,Bits 31:24 address parity error" "No error,Error" rbitfld.word 0x00 10. " AER[2] ,Bits 23:16 address parity error" "No error,Error" rbitfld.word 0x00 9. " AER[1] ,Bits 15:8 address parity error" "No error,Error" rbitfld.word 0x00 8. " AER[0] ,Bits 7:0 address parity error" "No error,Error" newline bitfld.word 0x00 7. " PECLR ,Parity error clear" "No clear,Clear" rbitfld.word 0x00 1. " CNER ,Control parity error" "No error,Error" rbitfld.word 0x00 0. " RDWR ,Data direction" "Read,Write" else group.word 0x14++0x01 "Common PERI #1" line.word 0x00 "BUSDIGSR1,Bus Diagnosis Status Register 1" rbitfld.word 0x00 15. " DER[3] ,Bits 31:24 data parity error" "No error,Error" rbitfld.word 0x00 14. " DER[2] ,Bits 23:16 data parity error" "No error,Error" rbitfld.word 0x00 13. " DER[1] ,Bits 15:8 data parity error" "No error,Error" rbitfld.word 0x00 12. " DER[0] ,Bits 7:0 data parity error" "No error,Error" newline rbitfld.word 0x00 11. " AER[3] ,Bits 31:24 address parity error" "No error,Error" rbitfld.word 0x00 10. " AER[2] ,Bits 23:16 address parity error" "No error,Error" rbitfld.word 0x00 9. " AER[1] ,Bits 15:8 address parity error" "No error,Error" rbitfld.word 0x00 8. " AER[0] ,Bits 7:0 address parity error" "No error,Error" newline bitfld.word 0x00 7. " PECLR ,Parity error clear" "No clear,Clear" rbitfld.word 0x00 1. " CNER ,Control parity error" "No error,Error" endif group.word (0x14+0x06)++0x01 line.word 0x00 "BUSTSTR1,Bus Diagnosis Test Register 1" bitfld.word 0x00 14.--15. " KEY ,Key" "0,1,2,3" bitfld.word 0x00 11. " CEN ,Control error" "No error,Error" bitfld.word 0x00 8. " AHBEN ,AHB parity error generation enable" "Disabled,Enabled" newline bitfld.word 0x00 7. " DEN[3] ,Bits 31:24 data parity error" "No error,Error" bitfld.word 0x00 6. " DEN[2] ,Bits 23:16 data parity error" "No error,Error" bitfld.word 0x00 5. " DEN[1] ,Bits 15:8 data parity error" "No error,Error" bitfld.word 0x00 4. " DEN[0] ,Bits 7:0 data parity error" "No error,Error" newline bitfld.word 0x00 3. " AEN[3] ,Bits 31:24 address parity error" "No error,Error" bitfld.word 0x00 2. " AEN[2] ,Bits 23:16 address parity error" "No error,Error" bitfld.word 0x00 1. " AEN[1] ,Bits 15:8 address parity error" "No error,Error" bitfld.word 0x00 0. " AEN[0] ,Bits 7:0 address parity error" "No error,Error" if ((per.w(ad:0xB4719000+0x14)&0xFF02)>0x00) rgroup.long (0x14+0x08)++0x03 line.long 0x00 "BUSADR1,Bus Diagnosis Address Register 1" else hgroup.long (0x14+0x08)++0x03 hide.long 0x00 "BUSADR1,Bus Diagnosis Address Register 1" endif if ((per.w(ad:0xB4719000+2)&0xFF02)>0x00) group.word 0x28++0x01 "MCU Config Group" line.word 0x00 "BUSDIGSR2,Bus Diagnosis Status Register 2" rbitfld.word 0x00 15. " DER[3] ,Bits 31:24 data parity error" "No error,Error" rbitfld.word 0x00 14. " DER[2] ,Bits 23:16 data parity error" "No error,Error" rbitfld.word 0x00 13. " DER[1] ,Bits 15:8 data parity error" "No error,Error" rbitfld.word 0x00 12. " DER[0] ,Bits 7:0 data parity error" "No error,Error" newline rbitfld.word 0x00 11. " AER[3] ,Bits 31:24 address parity error" "No error,Error" rbitfld.word 0x00 10. " AER[2] ,Bits 23:16 address parity error" "No error,Error" rbitfld.word 0x00 9. " AER[1] ,Bits 15:8 address parity error" "No error,Error" rbitfld.word 0x00 8. " AER[0] ,Bits 7:0 address parity error" "No error,Error" newline bitfld.word 0x00 7. " PECLR ,Parity error clear" "No clear,Clear" rbitfld.word 0x00 1. " CNER ,Control parity error" "No error,Error" rbitfld.word 0x00 0. " RDWR ,Data direction" "Read,Write" else group.word 0x28++0x01 "MCU Config Group" line.word 0x00 "BUSDIGSR2,Bus Diagnosis Status Register 2" rbitfld.word 0x00 15. " DER[3] ,Bits 31:24 data parity error" "No error,Error" rbitfld.word 0x00 14. " DER[2] ,Bits 23:16 data parity error" "No error,Error" rbitfld.word 0x00 13. " DER[1] ,Bits 15:8 data parity error" "No error,Error" rbitfld.word 0x00 12. " DER[0] ,Bits 7:0 data parity error" "No error,Error" newline rbitfld.word 0x00 11. " AER[3] ,Bits 31:24 address parity error" "No error,Error" rbitfld.word 0x00 10. " AER[2] ,Bits 23:16 address parity error" "No error,Error" rbitfld.word 0x00 9. " AER[1] ,Bits 15:8 address parity error" "No error,Error" rbitfld.word 0x00 8. " AER[0] ,Bits 7:0 address parity error" "No error,Error" newline bitfld.word 0x00 7. " PECLR ,Parity error clear" "No clear,Clear" rbitfld.word 0x00 1. " CNER ,Control parity error" "No error,Error" endif group.word (0x28+0x06)++0x01 line.word 0x00 "BUSTSTR2,Bus Diagnosis Test Register 2" bitfld.word 0x00 14.--15. " KEY ,Key" "0,1,2,3" bitfld.word 0x00 11. " CEN ,Control error" "No error,Error" bitfld.word 0x00 8. " AHBEN ,AHB parity error generation enable" "Disabled,Enabled" newline bitfld.word 0x00 7. " DEN[3] ,Bits 31:24 data parity error" "No error,Error" bitfld.word 0x00 6. " DEN[2] ,Bits 23:16 data parity error" "No error,Error" bitfld.word 0x00 5. " DEN[1] ,Bits 15:8 data parity error" "No error,Error" bitfld.word 0x00 4. " DEN[0] ,Bits 7:0 data parity error" "No error,Error" newline bitfld.word 0x00 3. " AEN[3] ,Bits 31:24 address parity error" "No error,Error" bitfld.word 0x00 2. " AEN[2] ,Bits 23:16 address parity error" "No error,Error" bitfld.word 0x00 1. " AEN[1] ,Bits 15:8 address parity error" "No error,Error" bitfld.word 0x00 0. " AEN[0] ,Bits 7:0 address parity error" "No error,Error" if ((per.w(ad:0xB4719000+0x28)&0xFF02)>0x00) rgroup.long (0x28+0x08)++0x03 line.long 0x00 "BUSADR2,Bus Diagnosis Address Register 2" else hgroup.long (0x28+0x08)++0x03 hide.long 0x00 "BUSADR2,Bus Diagnosis Address Register 2" endif width 0x0B tree.end newline